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| #define _XENIRQSTAT_needs_eoi (0) |
| #define _XENIRQSTAT_shared (1) |
| #define MAP_PIRQ_TYPE_GSI 0x1 |
| #define MAP_PIRQ_TYPE_MSI 0x0 |
| #define MAP_PIRQ_TYPE_MSI_SEG 0x3 |
| #define MAP_PIRQ_TYPE_UNKNOWN 0x2 |
| #define PHYSDEVOP_alloc_irq_vector 10 |
| #define PHYSDEVOP_apic_read 8 |
| #define PHYSDEVOP_apic_write 9 |
| #define PHYSDEVOP_DBGP_BUS_PCI 1 |
| #define PHYSDEVOP_DBGP_BUS_UNKNOWN 0 |
| #define PHYSDEVOP_dbgp_op 29 |
| #define PHYSDEVOP_DBGP_RESET_DONE 2 |
| #define PHYSDEVOP_DBGP_RESET_PREPARE 1 |
| #define PHYSDEVOP_free_irq_vector 11 |
| #define PHYSDEVOP_get_free_pirq 23 |
| #define PHYSDEVOP_get_nr_pirqs 22 |
| #define PHYSDEVOP_irq_status_query 5 |
| #define PHYSDEVOP_IRQ_UNMASK_NOTIFY 4 |
| #define PHYSDEVOP_manage_pci_add 15 |
| #define PHYSDEVOP_manage_pci_add_ext 20 |
| #define PHYSDEVOP_manage_pci_remove 16 |
| #define PHYSDEVOP_map_pirq 13 |
| #define PHYSDEVOP_pci_device_add 25 |
| #define PHYSDEVOP_pci_device_remove 26 |
| #define PHYSDEVOP_pirq_eoi_gmfn_v1 17 |
| #define PHYSDEVOP_pirq_eoi_gmfn_v2 28 |
| #define PHYSDEVOP_restore_msi 19 |
| #define PHYSDEVOP_restore_msi_ext 27 |
| #define PHYSDEVOP_set_iobitmap 7 |
| #define PHYSDEVOP_set_iopl 6 |
| #define PHYSDEVOP_setup_gsi 21 |
| #define PHYSDEVOP_unmap_pirq 14 |
| #define XEN_PCI_DEV_EXTFN 0x1 |
| #define XEN_PCI_DEV_PXM 0x4 |
| #define XEN_PCI_DEV_VIRTFN 0x2 |
| #define XENIRQSTAT_needs_eoi (1U<<_XENIRQSTAT_needs_eoi) |
| #define XENIRQSTAT_shared (1U<<_XENIRQSTAT_shared) |