Linux Kernel
3.7.1
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Macros | |
#define | SPA_STATUS_OK 0 |
#define | SPA_STATUS_ICV_FAIL 1 |
#define | SPA_STATUS_MEMORY_ERROR 2 |
#define | SPA_STATUS_BLOCK_ERROR 3 |
#define | SPA_IRQ_CTRL_STAT_CNT_OFFSET 16 |
#define | SPA_IRQ_STAT_STAT_MASK (1 << 4) |
#define | SPA_FIFO_STAT_STAT_OFFSET 16 |
#define | SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET) |
#define | SPA_STATUS_RES_CODE_OFFSET 24 |
#define | SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET) |
#define | SPA_KEY_SZ_CTX_INDEX_OFFSET 8 |
#define | SPA_KEY_SZ_CIPHER_OFFSET 31 |
#define | SPA_IRQ_EN_REG_OFFSET 0x00000000 |
#define | SPA_IRQ_STAT_REG_OFFSET 0x00000004 |
#define | SPA_IRQ_CTRL_REG_OFFSET 0x00000008 |
#define | SPA_FIFO_STAT_REG_OFFSET 0x0000000C |
#define | SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010 |
#define | SPA_SRC_PTR_REG_OFFSET 0x00000020 |
#define | SPA_DST_PTR_REG_OFFSET 0x00000024 |
#define | SPA_OFFSET_REG_OFFSET 0x00000028 |
#define | SPA_AAD_LEN_REG_OFFSET 0x0000002C |
#define | SPA_PROC_LEN_REG_OFFSET 0x00000030 |
#define | SPA_ICV_LEN_REG_OFFSET 0x00000034 |
#define | SPA_ICV_OFFSET_REG_OFFSET 0x00000038 |
#define | SPA_SW_CTRL_REG_OFFSET 0x0000003C |
#define | SPA_CTRL_REG_OFFSET 0x00000040 |
#define | SPA_AUX_INFO_REG_OFFSET 0x0000004C |
#define | SPA_STAT_POP_REG_OFFSET 0x00000050 |
#define | SPA_STATUS_REG_OFFSET 0x00000054 |
#define | SPA_KEY_SZ_REG_OFFSET 0x00000100 |
#define | SPA_CIPH_KEY_BASE_REG_OFFSET 0x00004000 |
#define | SPA_HASH_KEY_BASE_REG_OFFSET 0x00008000 |
#define | SPA_RC4_CTX_BASE_REG_OFFSET 0x00020000 |
#define | SPA_IRQ_EN_REG_RESET 0x00000000 |
#define | SPA_IRQ_CTRL_REG_RESET 0x00000000 |
#define | SPA_FIFO_STAT_REG_RESET 0x00000000 |
#define | SPA_SDMA_BRST_SZ_REG_RESET 0x00000000 |
#define | SPA_SRC_PTR_REG_RESET 0x00000000 |
#define | SPA_DST_PTR_REG_RESET 0x00000000 |
#define | SPA_OFFSET_REG_RESET 0x00000000 |
#define | SPA_AAD_LEN_REG_RESET 0x00000000 |
#define | SPA_PROC_LEN_REG_RESET 0x00000000 |
#define | SPA_ICV_LEN_REG_RESET 0x00000000 |
#define | SPA_ICV_OFFSET_REG_RESET 0x00000000 |
#define | SPA_SW_CTRL_REG_RESET 0x00000000 |
#define | SPA_CTRL_REG_RESET 0x00000000 |
#define | SPA_AUX_INFO_REG_RESET 0x00000000 |
#define | SPA_STAT_POP_REG_RESET 0x00000000 |
#define | SPA_STATUS_REG_RESET 0x00000000 |
#define | SPA_KEY_SZ_REG_RESET 0x00000000 |
#define | SPA_CTRL_HASH_ALG_IDX 4 |
#define | SPA_CTRL_CIPH_MODE_IDX 8 |
#define | SPA_CTRL_HASH_MODE_IDX 12 |
#define | SPA_CTRL_CTX_IDX 16 |
#define | SPA_CTRL_ENCRYPT_IDX 24 |
#define | SPA_CTRL_AAD_COPY 25 |
#define | SPA_CTRL_ICV_PT 26 |
#define | SPA_CTRL_ICV_ENC 27 |
#define | SPA_CTRL_ICV_APPEND 28 |
#define | SPA_CTRL_KEY_EXP 29 |
#define | SPA_KEY_SZ_CXT_IDX 8 |
#define | SPA_KEY_SZ_CIPHER_IDX 31 |
#define | SPA_IRQ_EN_CMD0_EN (1 << 0) |
#define | SPA_IRQ_EN_STAT_EN (1 << 4) |
#define | SPA_IRQ_EN_GLBL_EN (1 << 31) |
#define | SPA_CTRL_CIPH_ALG_NULL 0x00 |
#define | SPA_CTRL_CIPH_ALG_DES 0x01 |
#define | SPA_CTRL_CIPH_ALG_AES 0x02 |
#define | SPA_CTRL_CIPH_ALG_RC4 0x03 |
#define | SPA_CTRL_CIPH_ALG_MULTI2 0x04 |
#define | SPA_CTRL_CIPH_ALG_KASUMI 0x05 |
#define | SPA_CTRL_HASH_ALG_NULL (0x00 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_HASH_ALG_MD5 (0x01 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_HASH_ALG_SHA (0x02 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_HASH_ALG_SHA224 (0x03 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_HASH_ALG_SHA256 (0x04 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_HASH_ALG_SHA384 (0x05 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_HASH_ALG_SHA512 (0x06 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_HASH_ALG_AESMAC (0x07 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_HASH_ALG_AESCMAC (0x08 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_HASH_ALG_KASF9 (0x09 << SPA_CTRL_HASH_ALG_IDX) |
#define | SPA_CTRL_CIPH_MODE_NULL (0x00 << SPA_CTRL_CIPH_MODE_IDX) |
#define | SPA_CTRL_CIPH_MODE_ECB (0x00 << SPA_CTRL_CIPH_MODE_IDX) |
#define | SPA_CTRL_CIPH_MODE_CBC (0x01 << SPA_CTRL_CIPH_MODE_IDX) |
#define | SPA_CTRL_CIPH_MODE_CTR (0x02 << SPA_CTRL_CIPH_MODE_IDX) |
#define | SPA_CTRL_CIPH_MODE_CCM (0x03 << SPA_CTRL_CIPH_MODE_IDX) |
#define | SPA_CTRL_CIPH_MODE_GCM (0x05 << SPA_CTRL_CIPH_MODE_IDX) |
#define | SPA_CTRL_CIPH_MODE_OFB (0x07 << SPA_CTRL_CIPH_MODE_IDX) |
#define | SPA_CTRL_CIPH_MODE_CFB (0x08 << SPA_CTRL_CIPH_MODE_IDX) |
#define | SPA_CTRL_CIPH_MODE_F8 (0x09 << SPA_CTRL_CIPH_MODE_IDX) |
#define | SPA_CTRL_HASH_MODE_RAW (0x00 << SPA_CTRL_HASH_MODE_IDX) |
#define | SPA_CTRL_HASH_MODE_SSLMAC (0x01 << SPA_CTRL_HASH_MODE_IDX) |
#define | SPA_CTRL_HASH_MODE_HMAC (0x02 << SPA_CTRL_HASH_MODE_IDX) |
#define | SPA_FIFO_STAT_EMPTY (1 << 31) |
#define | SPA_FIFO_CMD_FULL (1 << 7) |
#define SPA_AAD_LEN_REG_OFFSET 0x0000002C |
Definition at line 43 of file picoxcell_crypto_regs.h.
#define SPA_AAD_LEN_REG_RESET 0x00000000 |
Definition at line 64 of file picoxcell_crypto_regs.h.
#define SPA_AUX_INFO_REG_OFFSET 0x0000004C |
Definition at line 49 of file picoxcell_crypto_regs.h.
#define SPA_AUX_INFO_REG_RESET 0x00000000 |
Definition at line 70 of file picoxcell_crypto_regs.h.
#define SPA_CIPH_KEY_BASE_REG_OFFSET 0x00004000 |
Definition at line 53 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_AAD_COPY 25 |
Definition at line 80 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_ALG_AES 0x02 |
Definition at line 95 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_ALG_DES 0x01 |
Definition at line 94 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_ALG_KASUMI 0x05 |
Definition at line 98 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_ALG_MULTI2 0x04 |
Definition at line 97 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_ALG_NULL 0x00 |
Definition at line 93 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_ALG_RC4 0x03 |
Definition at line 96 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_CBC (0x01 << SPA_CTRL_CIPH_MODE_IDX) |
Definition at line 113 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_CCM (0x03 << SPA_CTRL_CIPH_MODE_IDX) |
Definition at line 115 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_CFB (0x08 << SPA_CTRL_CIPH_MODE_IDX) |
Definition at line 118 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_CTR (0x02 << SPA_CTRL_CIPH_MODE_IDX) |
Definition at line 114 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_ECB (0x00 << SPA_CTRL_CIPH_MODE_IDX) |
Definition at line 112 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_F8 (0x09 << SPA_CTRL_CIPH_MODE_IDX) |
Definition at line 119 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_GCM (0x05 << SPA_CTRL_CIPH_MODE_IDX) |
Definition at line 116 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_IDX 8 |
Definition at line 76 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_NULL (0x00 << SPA_CTRL_CIPH_MODE_IDX) |
Definition at line 111 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CIPH_MODE_OFB (0x07 << SPA_CTRL_CIPH_MODE_IDX) |
Definition at line 117 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_CTX_IDX 16 |
Definition at line 78 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_ENCRYPT_IDX 24 |
Definition at line 79 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_AESCMAC (0x08 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 108 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_AESMAC (0x07 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 107 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_IDX 4 |
Definition at line 75 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_KASF9 (0x09 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 109 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_MD5 (0x01 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 101 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_NULL (0x00 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 100 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_SHA (0x02 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 102 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_SHA224 (0x03 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 103 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_SHA256 (0x04 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 104 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_SHA384 (0x05 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 105 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_ALG_SHA512 (0x06 << SPA_CTRL_HASH_ALG_IDX) |
Definition at line 106 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_MODE_HMAC (0x02 << SPA_CTRL_HASH_MODE_IDX) |
Definition at line 123 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_MODE_IDX 12 |
Definition at line 77 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_MODE_RAW (0x00 << SPA_CTRL_HASH_MODE_IDX) |
Definition at line 121 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_HASH_MODE_SSLMAC (0x01 << SPA_CTRL_HASH_MODE_IDX) |
Definition at line 122 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_ICV_APPEND 28 |
Definition at line 83 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_ICV_ENC 27 |
Definition at line 82 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_ICV_PT 26 |
Definition at line 81 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_KEY_EXP 29 |
Definition at line 84 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_REG_OFFSET 0x00000040 |
Definition at line 48 of file picoxcell_crypto_regs.h.
#define SPA_CTRL_REG_RESET 0x00000000 |
Definition at line 69 of file picoxcell_crypto_regs.h.
#define SPA_DST_PTR_REG_OFFSET 0x00000024 |
Definition at line 41 of file picoxcell_crypto_regs.h.
#define SPA_DST_PTR_REG_RESET 0x00000000 |
Definition at line 62 of file picoxcell_crypto_regs.h.
#define SPA_FIFO_CMD_FULL (1 << 7) |
Definition at line 126 of file picoxcell_crypto_regs.h.
#define SPA_FIFO_STAT_EMPTY (1 << 31) |
Definition at line 125 of file picoxcell_crypto_regs.h.
#define SPA_FIFO_STAT_REG_OFFSET 0x0000000C |
Definition at line 38 of file picoxcell_crypto_regs.h.
#define SPA_FIFO_STAT_REG_RESET 0x00000000 |
Definition at line 59 of file picoxcell_crypto_regs.h.
#define SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET) |
Definition at line 29 of file picoxcell_crypto_regs.h.
#define SPA_FIFO_STAT_STAT_OFFSET 16 |
Definition at line 28 of file picoxcell_crypto_regs.h.
#define SPA_HASH_KEY_BASE_REG_OFFSET 0x00008000 |
Definition at line 54 of file picoxcell_crypto_regs.h.
#define SPA_ICV_LEN_REG_OFFSET 0x00000034 |
Definition at line 45 of file picoxcell_crypto_regs.h.
#define SPA_ICV_LEN_REG_RESET 0x00000000 |
Definition at line 66 of file picoxcell_crypto_regs.h.
#define SPA_ICV_OFFSET_REG_OFFSET 0x00000038 |
Definition at line 46 of file picoxcell_crypto_regs.h.
#define SPA_ICV_OFFSET_REG_RESET 0x00000000 |
Definition at line 67 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_CTRL_REG_OFFSET 0x00000008 |
Definition at line 37 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_CTRL_REG_RESET 0x00000000 |
Definition at line 58 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_CTRL_STAT_CNT_OFFSET 16 |
Definition at line 26 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_EN_CMD0_EN (1 << 0) |
Definition at line 89 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_EN_GLBL_EN (1 << 31) |
Definition at line 91 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_EN_REG_OFFSET 0x00000000 |
Definition at line 35 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_EN_REG_RESET 0x00000000 |
Definition at line 57 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_EN_STAT_EN (1 << 4) |
Definition at line 90 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_STAT_REG_OFFSET 0x00000004 |
Definition at line 36 of file picoxcell_crypto_regs.h.
#define SPA_IRQ_STAT_STAT_MASK (1 << 4) |
Definition at line 27 of file picoxcell_crypto_regs.h.
#define SPA_KEY_SZ_CIPHER_IDX 31 |
Definition at line 87 of file picoxcell_crypto_regs.h.
#define SPA_KEY_SZ_CIPHER_OFFSET 31 |
Definition at line 33 of file picoxcell_crypto_regs.h.
#define SPA_KEY_SZ_CTX_INDEX_OFFSET 8 |
Definition at line 32 of file picoxcell_crypto_regs.h.
#define SPA_KEY_SZ_CXT_IDX 8 |
Definition at line 86 of file picoxcell_crypto_regs.h.
#define SPA_KEY_SZ_REG_OFFSET 0x00000100 |
Definition at line 52 of file picoxcell_crypto_regs.h.
#define SPA_KEY_SZ_REG_RESET 0x00000000 |
Definition at line 73 of file picoxcell_crypto_regs.h.
#define SPA_OFFSET_REG_OFFSET 0x00000028 |
Definition at line 42 of file picoxcell_crypto_regs.h.
#define SPA_OFFSET_REG_RESET 0x00000000 |
Definition at line 63 of file picoxcell_crypto_regs.h.
#define SPA_PROC_LEN_REG_OFFSET 0x00000030 |
Definition at line 44 of file picoxcell_crypto_regs.h.
#define SPA_PROC_LEN_REG_RESET 0x00000000 |
Definition at line 65 of file picoxcell_crypto_regs.h.
#define SPA_RC4_CTX_BASE_REG_OFFSET 0x00020000 |
Definition at line 55 of file picoxcell_crypto_regs.h.
#define SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010 |
Definition at line 39 of file picoxcell_crypto_regs.h.
#define SPA_SDMA_BRST_SZ_REG_RESET 0x00000000 |
Definition at line 60 of file picoxcell_crypto_regs.h.
#define SPA_SRC_PTR_REG_OFFSET 0x00000020 |
Definition at line 40 of file picoxcell_crypto_regs.h.
#define SPA_SRC_PTR_REG_RESET 0x00000000 |
Definition at line 61 of file picoxcell_crypto_regs.h.
#define SPA_STAT_POP_REG_OFFSET 0x00000050 |
Definition at line 50 of file picoxcell_crypto_regs.h.
#define SPA_STAT_POP_REG_RESET 0x00000000 |
Definition at line 71 of file picoxcell_crypto_regs.h.
#define SPA_STATUS_BLOCK_ERROR 3 |
Definition at line 24 of file picoxcell_crypto_regs.h.
#define SPA_STATUS_ICV_FAIL 1 |
Definition at line 22 of file picoxcell_crypto_regs.h.
#define SPA_STATUS_MEMORY_ERROR 2 |
Definition at line 23 of file picoxcell_crypto_regs.h.
#define SPA_STATUS_OK 0 |
Definition at line 21 of file picoxcell_crypto_regs.h.
#define SPA_STATUS_REG_OFFSET 0x00000054 |
Definition at line 51 of file picoxcell_crypto_regs.h.
#define SPA_STATUS_REG_RESET 0x00000000 |
Definition at line 72 of file picoxcell_crypto_regs.h.
#define SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET) |
Definition at line 31 of file picoxcell_crypto_regs.h.
#define SPA_STATUS_RES_CODE_OFFSET 24 |
Definition at line 30 of file picoxcell_crypto_regs.h.
#define SPA_SW_CTRL_REG_OFFSET 0x0000003C |
Definition at line 47 of file picoxcell_crypto_regs.h.
#define SPA_SW_CTRL_REG_RESET 0x00000000 |
Definition at line 68 of file picoxcell_crypto_regs.h.