pinctrl-spear1340.c File Reference

#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"

Go to the source code of this file.

Macros
#define	DRIVER_NAME   "spear1340-pinmux"
#define	PAD_FUNCTION_EN_1   0x668
#define	PAD_FUNCTION_EN_2   0x66C
#define	PAD_FUNCTION_EN_3   0x670
#define	PAD_FUNCTION_EN_4   0x674
#define	PAD_FUNCTION_EN_5   0x690
#define	PAD_FUNCTION_EN_6   0x694
#define	PAD_FUNCTION_EN_7   0x698
#define	PAD_FUNCTION_EN_8   0x69C
#define	PAD_SHARED_IP_EN_1   0x6A0
#define	PAD_SHARED_IP_EN_2   0x6A4
#define	PADS_AS_GPIO_REG0_MASK   0xFFFFFFFE
#define	PADS_AS_GPIO_REGS_MASK   0xFFFFFFFF
#define	PADS_AS_GPIO_REG7_MASK   0x07FFFFFF
#define	FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK   0x00000FFE
#define	UART0_ENH_AND_GPT_REG0_MASK   0x0003F000
#define	PWM1_AND_KBD_COL5_REG0_MASK   0x00040000
#define	I2C1_REG0_MASK   0x01080000
#define	SPDIF_IN_REG0_MASK   0x00100000
#define	PWM2_AND_GPT0_TMR0_CPT_REG0_MASK   0x00400000
#define	PWM3_AND_GPT0_TMR1_CLK_REG0_MASK   0x00800000
#define	PWM0_AND_SSP0_CS1_REG0_MASK   0x02000000
#define	VIP_AND_CAM3_REG0_MASK   0xFC200000
#define	VIP_AND_CAM3_REG1_MASK   0x0000000F
#define	VIP_REG1_MASK   0x00001EF0
#define	VIP_AND_CAM2_REG1_MASK   0x007FE100
#define	VIP_AND_CAM1_REG1_MASK   0xFF800000
#define	VIP_AND_CAM1_REG2_MASK   0x00000003
#define	VIP_AND_CAM0_REG2_MASK   0x00001FFC
#define	SMI_REG2_MASK   0x0021E000
#define	SSP0_REG2_MASK   0x001E0000
#define	TS_AND_SSP0_CS2_REG2_MASK   0x00400000
#define	UART0_REG2_MASK   0x01800000
#define	UART1_REG2_MASK   0x06000000
#define	I2S_IN_REG2_MASK   0xF8000000
#define	DEVS_GRP_AND_MIPHY_DBG_REG3_MASK   0x000001FE
#define	I2S_OUT_REG3_MASK   0x000001EF
#define	I2S_IN_REG3_MASK   0x00000010
#define	GMAC_REG3_MASK   0xFFFFFE00
#define	GMAC_REG4_MASK   0x0000001F
#define	DEVS_GRP_AND_MIPHY_DBG_REG4_MASK   0x7FFFFF20
#define	SSP0_CS3_REG4_MASK   0x00000020
#define	I2C0_REG4_MASK   0x000000C0
#define	CEC0_REG4_MASK   0x00000100
#define	CEC1_REG4_MASK   0x00000200
#define	SPDIF_OUT_REG4_MASK   0x00000400
#define	CLCD_REG4_MASK   0x7FFFF800
#define	CLCD_AND_ARM_TRACE_REG4_MASK   0x80000000
#define	CLCD_AND_ARM_TRACE_REG5_MASK   0xFFFFFFFF
#define	CLCD_AND_ARM_TRACE_REG6_MASK   0x00000001
#define	FSMC_PNOR_AND_MCIF_REG6_MASK   0x073FFFFE
#define	MCIF_REG6_MASK   0xF8C00000
#define	MCIF_REG7_MASK   0x000043FF
#define	FSMC_8BIT_REG7_MASK   0x07FFBC00
#define	PERIP_CFG   0x42C
#define	SSP_CS_CTL_HW   0
#define	SSP_CS_CTL_SW   1
#define	SSP_CS_CTL_MASK   1
#define	SSP_CS_CTL_SHIFT   21
#define	SSP_CS_VAL_MASK   1
#define	SSP_CS_VAL_SHIFT   20
#define	SSP_CS_SEL_CS0   0
#define	SSP_CS_SEL_CS1   1
#define	SSP_CS_SEL_CS2   2
#define	SSP_CS_SEL_MASK   3
#define	SSP_CS_SEL_SHIFT   18
#define	I2S_CHNL_2_0   (0)
#define	I2S_CHNL_3_1   (1)
#define	I2S_CHNL_5_1   (2)
#define	I2S_CHNL_7_1   (3)
#define	I2S_CHNL_PLAY_SHIFT   (4)
#define	I2S_CHNL_PLAY_MASK   (3 << 4)
#define	I2S_CHNL_REC_SHIFT   (6)
#define	I2S_CHNL_REC_MASK   (3 << 6)
#define	SPDIF_OUT_ENB_MASK   (1 << 2)
#define	SPDIF_OUT_ENB_SHIFT   2
#define	MCIF_SEL_SD   1
#define	MCIF_SEL_CF   2
#define	MCIF_SEL_XD   3
#define	MCIF_SEL_MASK   3
#define	MCIF_SEL_SHIFT   0
#define	GMAC_CLK_CFG   0x248
#define	GMAC_PHY_IF_GMII_VAL   (0 << 3)
#define	GMAC_PHY_IF_RGMII_VAL   (1 << 3)
#define	GMAC_PHY_IF_SGMII_VAL   (2 << 3)
#define	GMAC_PHY_IF_RMII_VAL   (4 << 3)
#define	GMAC_PHY_IF_SEL_MASK   (7 << 3)
#define	GMAC_PHY_INPUT_ENB_VAL   0
#define	GMAC_PHY_SYNT_ENB_VAL   1
#define	GMAC_PHY_CLK_MASK   1
#define	GMAC_PHY_CLK_SHIFT   2
#define	GMAC_PHY_125M_PAD_VAL   0
#define	GMAC_PHY_PLL2_VAL   1
#define	GMAC_PHY_OSC3_VAL   2
#define	GMAC_PHY_INPUT_CLK_MASK   3
#define	GMAC_PHY_INPUT_CLK_SHIFT   0
#define	PCIE_SATA_CFG   0x424
#define	PCIE_CFG_DEVICE_PRESENT   (1 << 11)
#define	PCIE_CFG_POWERUP_RESET   (1 << 10)
#define	PCIE_CFG_CORE_CLK_EN   (1 << 9)
#define	PCIE_CFG_AUX_CLK_EN   (1 << 8)
#define	SATA_CFG_TX_CLK_EN   (1 << 4)
#define	SATA_CFG_RX_CLK_EN   (1 << 3)
#define	SATA_CFG_POWERUP_RESET   (1 << 2)
#define	SATA_CFG_PM_CLK_EN   (1 << 1)
#define	PCIE_SATA_SEL_PCIE   (0)
#define	PCIE_SATA_SEL_SATA   (1)
#define	SATA_PCIE_CFG_MASK   0xF1F
#define	PCIE_CFG_VAL
#define	SATA_CFG_VAL
#define	KBD_ROW_COL_MASK   (1 << 0)
#define	GPT_MASK   (1 << 1) /* Only clk & cpt */
#define	KBD_COL5_MASK   (1 << 2)
#define	GPT0_TMR0_CPT_MASK   (1 << 3) /* Only clk & cpt */
#define	GPT0_TMR1_CLK_MASK   (1 << 4) /* Only clk & cpt */
#define	SSP0_CS1_MASK   (1 << 5)
#define	CAM3_MASK   (1 << 6)
#define	CAM2_MASK   (1 << 7)
#define	CAM1_MASK   (1 << 8)
#define	CAM0_MASK   (1 << 9)
#define	SSP0_CS2_MASK   (1 << 10)
#define	MCIF_MASK   (1 << 11)
#define	ARM_TRACE_MASK   (1 << 12)
#define	MIPHY_DBG_MASK   (1 << 13)
#define	GMAC_MUXREG
#define	MCIF_MUXREG

Functions
	arch_initcall (spear1340_pinctrl_init)
	module_exit (spear1340_pinctrl_exit)
	MODULE_AUTHOR ("Viresh Kumar <[email protected]>")
	MODULE_DESCRIPTION ("ST Microelectronics SPEAr1340 pinctrl driver")
	MODULE_LICENSE ("GPL v2")
	MODULE_DEVICE_TABLE (of, spear1340_pinctrl_of_match)

Macro Definition Documentation

#define ARM_TRACE_MASK   (1 << 12)

Definition at line 207 of file pinctrl-spear1340.c.

#define CAM0_MASK   (1 << 9)

Definition at line 198 of file pinctrl-spear1340.c.

#define CAM1_MASK   (1 << 8)

Definition at line 195 of file pinctrl-spear1340.c.

#define CAM2_MASK   (1 << 7)

Definition at line 192 of file pinctrl-spear1340.c.

#define CAM3_MASK   (1 << 6)

Definition at line 189 of file pinctrl-spear1340.c.

#define CEC0_REG4_MASK   0x00000100

Definition at line 88 of file pinctrl-spear1340.c.

#define CEC1_REG4_MASK   0x00000200

Definition at line 89 of file pinctrl-spear1340.c.

#define CLCD_AND_ARM_TRACE_REG4_MASK   0x80000000

Definition at line 92 of file pinctrl-spear1340.c.

#define CLCD_AND_ARM_TRACE_REG5_MASK   0xFFFFFFFF

Definition at line 93 of file pinctrl-spear1340.c.

#define CLCD_AND_ARM_TRACE_REG6_MASK   0x00000001

Definition at line 94 of file pinctrl-spear1340.c.

#define CLCD_REG4_MASK   0x7FFFF800

Definition at line 91 of file pinctrl-spear1340.c.

#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK   0x000001FE

Definition at line 80 of file pinctrl-spear1340.c.

#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK   0x7FFFFF20

Definition at line 85 of file pinctrl-spear1340.c.

#define DRIVER_NAME   "spear1340-pinmux"

Definition at line 19 of file pinctrl-spear1340.c.

#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK   0x00000FFE

Definition at line 59 of file pinctrl-spear1340.c.

#define FSMC_8BIT_REG7_MASK   0x07FFBC00

Definition at line 98 of file pinctrl-spear1340.c.

#define FSMC_PNOR_AND_MCIF_REG6_MASK   0x073FFFFE

Definition at line 95 of file pinctrl-spear1340.c.

#define GMAC_CLK_CFG   0x248

Definition at line 133 of file pinctrl-spear1340.c.

#define GMAC_MUXREG

Value:

{                   \
        .reg = PAD_FUNCTION_EN_4,   \
        .mask = GMAC_REG3_MASK,     \
        .val = GMAC_REG3_MASK,      \
    }, {                    \
        .reg = PAD_FUNCTION_EN_5,   \
        .mask = GMAC_REG4_MASK,     \
        .val = GMAC_REG4_MASK,      \
    }

Definition at line 1291 of file pinctrl-spear1340.c.

#define GMAC_PHY_125M_PAD_VAL   0

Definition at line 143 of file pinctrl-spear1340.c.

#define GMAC_PHY_CLK_MASK   1

Definition at line 141 of file pinctrl-spear1340.c.

#define GMAC_PHY_CLK_SHIFT   2

Definition at line 142 of file pinctrl-spear1340.c.

#define GMAC_PHY_IF_GMII_VAL   (0 << 3)

Definition at line 134 of file pinctrl-spear1340.c.

#define GMAC_PHY_IF_RGMII_VAL   (1 << 3)

Definition at line 135 of file pinctrl-spear1340.c.

#define GMAC_PHY_IF_RMII_VAL   (4 << 3)

Definition at line 137 of file pinctrl-spear1340.c.

#define GMAC_PHY_IF_SEL_MASK   (7 << 3)

Definition at line 138 of file pinctrl-spear1340.c.

#define GMAC_PHY_IF_SGMII_VAL   (2 << 3)

Definition at line 136 of file pinctrl-spear1340.c.

#define GMAC_PHY_INPUT_CLK_MASK   3

Definition at line 146 of file pinctrl-spear1340.c.

#define GMAC_PHY_INPUT_CLK_SHIFT   0

Definition at line 147 of file pinctrl-spear1340.c.

#define GMAC_PHY_INPUT_ENB_VAL   0

Definition at line 139 of file pinctrl-spear1340.c.

#define GMAC_PHY_OSC3_VAL   2

Definition at line 145 of file pinctrl-spear1340.c.

#define GMAC_PHY_PLL2_VAL   1

Definition at line 144 of file pinctrl-spear1340.c.

#define GMAC_PHY_SYNT_ENB_VAL   1

Definition at line 140 of file pinctrl-spear1340.c.

#define GMAC_REG3_MASK   0xFFFFFE00

Definition at line 83 of file pinctrl-spear1340.c.

#define GMAC_REG4_MASK   0x0000001F

Definition at line 84 of file pinctrl-spear1340.c.

#define GPT0_TMR0_CPT_MASK   (1 << 3) /* Only clk & cpt */

Definition at line 180 of file pinctrl-spear1340.c.

#define GPT0_TMR1_CLK_MASK   (1 << 4) /* Only clk & cpt */

Definition at line 183 of file pinctrl-spear1340.c.

#define GPT_MASK   (1 << 1) /* Only clk & cpt */

Definition at line 174 of file pinctrl-spear1340.c.

#define I2C0_REG4_MASK   0x000000C0

Definition at line 87 of file pinctrl-spear1340.c.

#define I2C1_REG0_MASK   0x01080000

Definition at line 62 of file pinctrl-spear1340.c.

#define I2S_CHNL_2_0   (0)

Definition at line 115 of file pinctrl-spear1340.c.

#define I2S_CHNL_3_1   (1)

Definition at line 116 of file pinctrl-spear1340.c.

#define I2S_CHNL_5_1   (2)

Definition at line 117 of file pinctrl-spear1340.c.

#define I2S_CHNL_7_1   (3)

Definition at line 118 of file pinctrl-spear1340.c.

#define I2S_CHNL_PLAY_MASK   (3 << 4)

Definition at line 120 of file pinctrl-spear1340.c.

#define I2S_CHNL_PLAY_SHIFT   (4)

Definition at line 119 of file pinctrl-spear1340.c.

#define I2S_CHNL_REC_MASK   (3 << 6)

Definition at line 122 of file pinctrl-spear1340.c.

#define I2S_CHNL_REC_SHIFT   (6)

Definition at line 121 of file pinctrl-spear1340.c.

#define I2S_IN_REG2_MASK   0xF8000000

Definition at line 79 of file pinctrl-spear1340.c.

#define I2S_IN_REG3_MASK   0x00000010

Definition at line 82 of file pinctrl-spear1340.c.

#define I2S_OUT_REG3_MASK   0x000001EF

Definition at line 81 of file pinctrl-spear1340.c.

#define KBD_COL5_MASK   (1 << 2)

Definition at line 177 of file pinctrl-spear1340.c.

#define KBD_ROW_COL_MASK   (1 << 0)

Definition at line 171 of file pinctrl-spear1340.c.

#define MCIF_MASK   (1 << 11)

Definition at line 204 of file pinctrl-spear1340.c.

#define MCIF_MUXREG

Value:

{                               \
        .reg = PAD_SHARED_IP_EN_1,              \
        .mask = MCIF_MASK,                  \
        .val = MCIF_MASK,                   \
    }, {                                \
        .reg = PAD_FUNCTION_EN_7,               \
        .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK,  \
        .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK,   \
    }, {                                \
        .reg = PAD_FUNCTION_EN_8,               \
        .mask = MCIF_REG7_MASK,                 \
        .val = MCIF_REG7_MASK,                  \
    }

Definition at line 1543 of file pinctrl-spear1340.c.

#define MCIF_REG6_MASK   0xF8C00000

Definition at line 96 of file pinctrl-spear1340.c.

#define MCIF_REG7_MASK   0x000043FF

Definition at line 97 of file pinctrl-spear1340.c.

#define MCIF_SEL_CF   2

Definition at line 128 of file pinctrl-spear1340.c.

#define MCIF_SEL_MASK   3

Definition at line 130 of file pinctrl-spear1340.c.

#define MCIF_SEL_SD   1

Definition at line 127 of file pinctrl-spear1340.c.

#define MCIF_SEL_SHIFT   0

Definition at line 131 of file pinctrl-spear1340.c.

#define MCIF_SEL_XD   3

Definition at line 129 of file pinctrl-spear1340.c.

#define MIPHY_DBG_MASK   (1 << 13)

Definition at line 210 of file pinctrl-spear1340.c.

#define PAD_FUNCTION_EN_1   0x668

Definition at line 35 of file pinctrl-spear1340.c.

#define PAD_FUNCTION_EN_2   0x66C

Definition at line 36 of file pinctrl-spear1340.c.

#define PAD_FUNCTION_EN_3   0x670

Definition at line 37 of file pinctrl-spear1340.c.

#define PAD_FUNCTION_EN_4   0x674

Definition at line 38 of file pinctrl-spear1340.c.

#define PAD_FUNCTION_EN_5   0x690

Definition at line 39 of file pinctrl-spear1340.c.

#define PAD_FUNCTION_EN_6   0x694

Definition at line 40 of file pinctrl-spear1340.c.

#define PAD_FUNCTION_EN_7   0x698

Definition at line 41 of file pinctrl-spear1340.c.

#define PAD_FUNCTION_EN_8   0x69C

Definition at line 42 of file pinctrl-spear1340.c.

#define PAD_SHARED_IP_EN_1   0x6A0

Definition at line 45 of file pinctrl-spear1340.c.

#define PAD_SHARED_IP_EN_2   0x6A4

Definition at line 46 of file pinctrl-spear1340.c.

#define PADS_AS_GPIO_REG0_MASK   0xFFFFFFFE

Definition at line 54 of file pinctrl-spear1340.c.

#define PADS_AS_GPIO_REG7_MASK   0x07FFFFFF

Definition at line 56 of file pinctrl-spear1340.c.

#define PADS_AS_GPIO_REGS_MASK   0xFFFFFFFF

Definition at line 55 of file pinctrl-spear1340.c.

#define PCIE_CFG_AUX_CLK_EN   (1 << 8)

Definition at line 154 of file pinctrl-spear1340.c.

#define PCIE_CFG_CORE_CLK_EN   (1 << 9)

Definition at line 153 of file pinctrl-spear1340.c.

#define PCIE_CFG_DEVICE_PRESENT   (1 << 11)

Definition at line 151 of file pinctrl-spear1340.c.

#define PCIE_CFG_POWERUP_RESET   (1 << 10)

Definition at line 152 of file pinctrl-spear1340.c.

#define PCIE_CFG_VAL

Value:

(PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \
                PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\
                PCIE_CFG_DEVICE_PRESENT)

Definition at line 162 of file pinctrl-spear1340.c.

#define PCIE_SATA_CFG   0x424

Definition at line 149 of file pinctrl-spear1340.c.

#define PCIE_SATA_SEL_PCIE   (0)

Definition at line 159 of file pinctrl-spear1340.c.

#define PCIE_SATA_SEL_SATA   (1)

Definition at line 160 of file pinctrl-spear1340.c.

#define PERIP_CFG   0x42C

Definition at line 101 of file pinctrl-spear1340.c.

#define PWM0_AND_SSP0_CS1_REG0_MASK   0x02000000

Definition at line 66 of file pinctrl-spear1340.c.

#define PWM1_AND_KBD_COL5_REG0_MASK   0x00040000

Definition at line 61 of file pinctrl-spear1340.c.

#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK   0x00400000

Definition at line 64 of file pinctrl-spear1340.c.

#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK   0x00800000

Definition at line 65 of file pinctrl-spear1340.c.

#define SATA_CFG_PM_CLK_EN   (1 << 1)

Definition at line 158 of file pinctrl-spear1340.c.

#define SATA_CFG_POWERUP_RESET   (1 << 2)

Definition at line 157 of file pinctrl-spear1340.c.

#define SATA_CFG_RX_CLK_EN   (1 << 3)

Definition at line 156 of file pinctrl-spear1340.c.

#define SATA_CFG_TX_CLK_EN   (1 << 4)

Definition at line 155 of file pinctrl-spear1340.c.

#define SATA_CFG_VAL

Value:

(PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \
                SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \
                SATA_CFG_TX_CLK_EN)

Definition at line 165 of file pinctrl-spear1340.c.

#define SATA_PCIE_CFG_MASK   0xF1F

Definition at line 161 of file pinctrl-spear1340.c.

#define SMI_REG2_MASK   0x0021E000

Definition at line 74 of file pinctrl-spear1340.c.

#define SPDIF_IN_REG0_MASK   0x00100000

Definition at line 63 of file pinctrl-spear1340.c.

#define SPDIF_OUT_ENB_MASK   (1 << 2)

Definition at line 124 of file pinctrl-spear1340.c.

#define SPDIF_OUT_ENB_SHIFT   2

Definition at line 125 of file pinctrl-spear1340.c.

#define SPDIF_OUT_REG4_MASK   0x00000400

Definition at line 90 of file pinctrl-spear1340.c.

#define SSP0_CS1_MASK   (1 << 5)

Definition at line 186 of file pinctrl-spear1340.c.

#define SSP0_CS2_MASK   (1 << 10)

Definition at line 201 of file pinctrl-spear1340.c.

#define SSP0_CS3_REG4_MASK   0x00000020

Definition at line 86 of file pinctrl-spear1340.c.

#define SSP0_REG2_MASK   0x001E0000

Definition at line 75 of file pinctrl-spear1340.c.

#define SSP_CS_CTL_HW   0

Definition at line 103 of file pinctrl-spear1340.c.

#define SSP_CS_CTL_MASK   1

Definition at line 105 of file pinctrl-spear1340.c.

#define SSP_CS_CTL_SHIFT   21

Definition at line 106 of file pinctrl-spear1340.c.

#define SSP_CS_CTL_SW   1

Definition at line 104 of file pinctrl-spear1340.c.

#define SSP_CS_SEL_CS0   0

Definition at line 109 of file pinctrl-spear1340.c.

#define SSP_CS_SEL_CS1   1

Definition at line 110 of file pinctrl-spear1340.c.

#define SSP_CS_SEL_CS2   2

Definition at line 111 of file pinctrl-spear1340.c.

#define SSP_CS_SEL_MASK   3

Definition at line 112 of file pinctrl-spear1340.c.

#define SSP_CS_SEL_SHIFT   18

Definition at line 113 of file pinctrl-spear1340.c.

#define SSP_CS_VAL_MASK   1

Definition at line 107 of file pinctrl-spear1340.c.

#define SSP_CS_VAL_SHIFT   20

Definition at line 108 of file pinctrl-spear1340.c.

#define TS_AND_SSP0_CS2_REG2_MASK   0x00400000

Definition at line 76 of file pinctrl-spear1340.c.

#define UART0_ENH_AND_GPT_REG0_MASK   0x0003F000

Definition at line 60 of file pinctrl-spear1340.c.

#define UART0_REG2_MASK   0x01800000

Definition at line 77 of file pinctrl-spear1340.c.

#define UART1_REG2_MASK   0x06000000

Definition at line 78 of file pinctrl-spear1340.c.

#define VIP_AND_CAM0_REG2_MASK   0x00001FFC

Definition at line 73 of file pinctrl-spear1340.c.

#define VIP_AND_CAM1_REG1_MASK   0xFF800000

Definition at line 71 of file pinctrl-spear1340.c.

#define VIP_AND_CAM1_REG2_MASK   0x00000003

Definition at line 72 of file pinctrl-spear1340.c.

#define VIP_AND_CAM2_REG1_MASK   0x007FE100

Definition at line 70 of file pinctrl-spear1340.c.

#define VIP_AND_CAM3_REG0_MASK   0xFC200000

Definition at line 67 of file pinctrl-spear1340.c.

#define VIP_AND_CAM3_REG1_MASK   0x0000000F

Definition at line 68 of file pinctrl-spear1340.c.

#define VIP_REG1_MASK   0x00001EF0

Definition at line 69 of file pinctrl-spear1340.c.

Function Documentation

arch_initcall

(

spear1340_pinctrl_init

)

MODULE_AUTHOR

(

"Viresh Kumar <[email protected]>"

)

MODULE_DESCRIPTION

(

"ST Microelectronics SPEAr1340 pinctrl driver"

)

MODULE_DEVICE_TABLE	(	of	,
		spear1340_pinctrl_of_match
	)

module_exit

(

spear1340_pinctrl_exit

)

MODULE_LICENSE

(

"GPL v2"

)