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plx9052.h
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1 /*
2  comedi/drivers/plx9052.h
3  Definitions for the PLX-9052 PCI interface chip
4 
5  Copyright (C) 2002 MEV Ltd. <http://www.mev.co.uk/>
6 
7  COMEDI - Linux Control and Measurement Device Interface
8  Copyright (C) 2000 David A. Schleef <[email protected]>
9 
10  This program is free software; you can redistribute it and/or modify
11  it under the terms of the GNU General Public License as published by
12  the Free Software Foundation; either version 2 of the License, or
13  (at your option) any later version.
14 
15  This program is distributed in the hope that it will be useful,
16  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  GNU General Public License for more details.
19 
20  You should have received a copy of the GNU General Public License
21  along with this program; if not, write to the Free Software
22  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 
24 */
25 
26 #ifndef _PLX9052_H_
27 #define _PLX9052_H_
28 
29 /*
30  * PLX PCI9052 INTCSR register.
31  */
32 #define PLX9052_INTCSR 0x4C /* Offset in Local Configuration Registers */
33 /* Local Interrupt 1 Enable */
34 #define PLX9052_INTCSR_LI1ENAB_MASK 0x0001
35 #define PLX9052_INTCSR_LI1ENAB_DISABLED 0x0000
36 #define PLX9052_INTCSR_LI1ENAB_ENABLED 0x0001
37 /* Local Interrupt 1 Polarity */
38 #define PLX9052_INTCSR_LI1POL_MASK 0x0002
39 #define PLX9052_INTCSR_LI1POL_LOW 0x0000
40 #define PLX9052_INTCSR_LI1POL_HIGH 0x0002
41 /* Local Interrupt 1 Status (read-only) */
42 #define PLX9052_INTCSR_LI1STAT_MASK 0x0004
43 #define PLX9052_INTCSR_LI1STAT_INACTIVE 0x0000
44 #define PLX9052_INTCSR_LI1STAT_ACTIVE 0x0004
45 /* Local Interrupt 2 Enable */
46 #define PLX9052_INTCSR_LI2ENAB_MASK 0x0008
47 #define PLX9052_INTCSR_LI2ENAB_DISABLED 0x0000
48 #define PLX9052_INTCSR_LI2ENAB_ENABLED 0x0008
49 /* Local Interrupt 2 Polarity */
50 #define PLX9052_INTCSR_LI2POL_MASK 0x0010
51 #define PLX9052_INTCSR_LI2POL_LOW 0x0000
52 #define PLX9052_INTCSR_LI2POL_HIGH 0x0010
53 /* Local Interrupt 2 Status (read-only) */
54 #define PLX9052_INTCSR_LI2STAT_MASK 0x0020
55 #define PLX9052_INTCSR_LI2STAT_INACTIVE 0x0000
56 #define PLX9052_INTCSR_LI2STAT_ACTIVE 0x0020
57 /* PCI Interrupt Enable */
58 #define PLX9052_INTCSR_PCIENAB_MASK 0x0040
59 #define PLX9052_INTCSR_PCIENAB_DISABLED 0x0000
60 #define PLX9052_INTCSR_PCIENAB_ENABLED 0x0040
61 /* Software Interrupt */
62 #define PLX9052_INTCSR_SOFTINT_MASK 0x0080
63 #define PLX9052_INTCSR_SOFTINT_UNASSERTED 0x0000
64 #define PLX9052_INTCSR_SOFTINT_ASSERTED 0x0080
65 /* Local Interrupt 1 Select Enable */
66 #define PLX9052_INTCSR_LI1SEL_MASK 0x0100
67 #define PLX9052_INTCSR_LI1SEL_LEVEL 0x0000
68 #define PLX9052_INTCSR_LI1SEL_EDGE 0x0100
69 /* Local Interrupt 2 Select Enable */
70 #define PLX9052_INTCSR_LI2SEL_MASK 0x0200
71 #define PLX9052_INTCSR_LI2SEL_LEVEL 0x0000
72 #define PLX9052_INTCSR_LI2SEL_EDGE 0x0200
73 /* Local Edge Triggerable Interrupt 1 Clear Bit */
74 #define PLX9052_INTCSR_LI1CLRINT_MASK 0x0400
75 #define PLX9052_INTCSR_LI1CLRINT_UNASSERTED 0x0000
76 #define PLX9052_INTCSR_LI1CLRINT_ASSERTED 0x0400
77 /* Local Edge Triggerable Interrupt 2 Clear Bit */
78 #define PLX9052_INTCSR_LI2CLRINT_MASK 0x0800
79 #define PLX9052_INTCSR_LI2CLRINT_UNASSERTED 0x0000
80 #define PLX9052_INTCSR_LI2CLRINT_ASSERTED 0x0800
81 /* ISA Interface Mode Enable (read-only over PCI bus) */
82 #define PLX9052_INTCSR_ISAMODE_MASK 0x1000
83 #define PLX9052_INTCSR_ISAMODE_DISABLED 0x0000
84 #define PLX9052_INTCSR_ISAMODE_ENABLED 0x1000
85 
86 #endif /* _PLX9052_H_ */