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#define PLX9052_INTCSR 0x4C /* Offset in Local Configuration Registers */ |
#define PLX9052_INTCSR_ISAMODE_DISABLED 0x0000 |
#define PLX9052_INTCSR_ISAMODE_ENABLED 0x1000 |
#define PLX9052_INTCSR_ISAMODE_MASK 0x1000 |
#define PLX9052_INTCSR_LI1CLRINT_ASSERTED 0x0400 |
#define PLX9052_INTCSR_LI1CLRINT_MASK 0x0400 |
#define PLX9052_INTCSR_LI1CLRINT_UNASSERTED 0x0000 |
#define PLX9052_INTCSR_LI1ENAB_DISABLED 0x0000 |
#define PLX9052_INTCSR_LI1ENAB_ENABLED 0x0001 |
#define PLX9052_INTCSR_LI1ENAB_MASK 0x0001 |
#define PLX9052_INTCSR_LI1POL_HIGH 0x0002 |
#define PLX9052_INTCSR_LI1POL_LOW 0x0000 |
#define PLX9052_INTCSR_LI1POL_MASK 0x0002 |
#define PLX9052_INTCSR_LI1SEL_EDGE 0x0100 |
#define PLX9052_INTCSR_LI1SEL_LEVEL 0x0000 |
#define PLX9052_INTCSR_LI1SEL_MASK 0x0100 |
#define PLX9052_INTCSR_LI1STAT_ACTIVE 0x0004 |
#define PLX9052_INTCSR_LI1STAT_INACTIVE 0x0000 |
#define PLX9052_INTCSR_LI1STAT_MASK 0x0004 |
#define PLX9052_INTCSR_LI2CLRINT_ASSERTED 0x0800 |
#define PLX9052_INTCSR_LI2CLRINT_MASK 0x0800 |
#define PLX9052_INTCSR_LI2CLRINT_UNASSERTED 0x0000 |
#define PLX9052_INTCSR_LI2ENAB_DISABLED 0x0000 |
#define PLX9052_INTCSR_LI2ENAB_ENABLED 0x0008 |
#define PLX9052_INTCSR_LI2ENAB_MASK 0x0008 |
#define PLX9052_INTCSR_LI2POL_HIGH 0x0010 |
#define PLX9052_INTCSR_LI2POL_LOW 0x0000 |
#define PLX9052_INTCSR_LI2POL_MASK 0x0010 |
#define PLX9052_INTCSR_LI2SEL_EDGE 0x0200 |
#define PLX9052_INTCSR_LI2SEL_LEVEL 0x0000 |
#define PLX9052_INTCSR_LI2SEL_MASK 0x0200 |
#define PLX9052_INTCSR_LI2STAT_ACTIVE 0x0020 |
#define PLX9052_INTCSR_LI2STAT_INACTIVE 0x0000 |
#define PLX9052_INTCSR_LI2STAT_MASK 0x0020 |
#define PLX9052_INTCSR_PCIENAB_DISABLED 0x0000 |
#define PLX9052_INTCSR_PCIENAB_ENABLED 0x0040 |
#define PLX9052_INTCSR_PCIENAB_MASK 0x0040 |
#define PLX9052_INTCSR_SOFTINT_ASSERTED 0x0080 |
#define PLX9052_INTCSR_SOFTINT_MASK 0x0080 |
#define PLX9052_INTCSR_SOFTINT_UNASSERTED 0x0000 |