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pmcc4_cpld.h
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1 #ifndef _INC_PMCC4_CPLD_H_
2 #define _INC_PMCC4_CPLD_H_
3 
4 /*-----------------------------------------------------------------------------
5  * pmcc4_cpld.h -
6  *
7  * Copyright (C) 2005 SBE, Inc.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * For further information, contact via email: [email protected]
20  * SBE, Inc. San Ramon, California U.S.A.
21  *-----------------------------------------------------------------------------
22  */
23 
24 #include <linux/types.h>
25 
26 /********************************/
27 /* iSPLD control chip registers */
28 /********************************/
29 
30 #if 0
31 #define CPLD_MCSR 0x0
32 #define CPLD_MCLK 0x1
33 #define CPLD_LEDS 0x2
34 #define CPLD_INTR 0x3
35 #endif
36 
37  struct c4_cpld
38  {
39  volatile u_int32_t mcsr;/* r/w: Master Clock Source Register */
40  volatile u_int32_t mclk;/* r/w: Master Clock Register */
41  volatile u_int32_t leds;/* r/w: LED Register */
42  volatile u_int32_t intr;/* r: Interrupt Register */
43  };
44 
45  typedef struct c4_cpld c4cpld_t;
46 
47 /* mcsr note: sourcing COMET must be initialized to Master Mode */
48 #define PMCC4_CPLD_MCSR_IND 0 /* ports used individual BP Clk as
49  * source, no slaves */
50 #define PMCC4_CPLD_MCSR_CMT_1 1 /* COMET 1 BP Clk is source, 2,3,4
51  * are Clk slaves */
52 #define PMCC4_CPLD_MCSR_CMT_2 2 /* COMET 2 BP Clk is source, 1,3,4
53  * are Clk slaves */
54 #define PMCC4_CPLD_MCSR_CMT_3 3 /* COMET 3 BP Clk is source, 1,2,4
55  * are Clk slaves */
56 #define PMCC4_CPLD_MCSR_CMT_4 4 /* COMET 4 BP Clk is source, 1,2,3
57  * are Clk slaves */
58 
59 #define PMCC4_CPLD_MCLK_MASK 0x0f
60 #define PMCC4_CPLD_MCLK_P1 0x1
61 #define PMCC4_CPLD_MCLK_P2 0x2
62 #define PMCC4_CPLD_MCLK_P3 0x4
63 #define PMCC4_CPLD_MCLK_P4 0x8
64 #define PMCC4_CPLD_MCLK_T1 0x00
65 #define PMCC4_CPLD_MCLK_P1_E1 0x01
66 #define PMCC4_CPLD_MCLK_P2_E1 0x02
67 #define PMCC4_CPLD_MCLK_P3_E1 0x04
68 #define PMCC4_CPLD_MCLK_P4_E1 0x08
69 
70 #define PMCC4_CPLD_LED_OFF 0
71 #define PMCC4_CPLD_LED_ON 1
72 #define PMCC4_CPLD_LED_GP0 0x01 /* port 0, green */
73 #define PMCC4_CPLD_LED_YP0 0x02 /* port 0, yellow */
74 #define PMCC4_CPLD_LED_GP1 0x04 /* port 1, green */
75 #define PMCC4_CPLD_LED_YP1 0x08 /* port 1, yellow */
76 #define PMCC4_CPLD_LED_GP2 0x10 /* port 2, green */
77 #define PMCC4_CPLD_LED_YP2 0x20 /* port 2, yellow */
78 #define PMCC4_CPLD_LED_GP3 0x40 /* port 3, green */
79 #define PMCC4_CPLD_LED_YP3 0x80 /* port 3, yellow */
80 #define PMCC4_CPLD_LED_GREEN (PMCC4_CPLD_LED_GP0 | PMCC4_CPLD_LED_GP1 | \
81  PMCC4_CPLD_LED_GP2 | PMCC4_CPLD_LED_GP3 )
82 #define PMCC4_CPLD_LED_YELLOW (PMCC4_CPLD_LED_YP0 | PMCC4_CPLD_LED_YP1 | \
83  PMCC4_CPLD_LED_YP2 | PMCC4_CPLD_LED_YP3)
84 
85 #define PMCC4_CPLD_INTR_MASK 0x0f
86 #define PMCC4_CPLD_INTR_CMT_1 0x01
87 #define PMCC4_CPLD_INTR_CMT_2 0x02
88 #define PMCC4_CPLD_INTR_CMT_3 0x04
89 #define PMCC4_CPLD_INTR_CMT_4 0x08
90 
91 #endif /* _INC_PMCC4_CPLD_H_ */