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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include <linux/types.h>Go to the source code of this file.
| #define PPC_REG_BITS 32 |
Definition at line 24 of file ppc4xx_edac.h.
| #define PPC_REG_DECODE | ( | bit, | |
| val | |||
| ) | ((val) >> ((PPC_REG_BITS - 1) - (bit))) |
Definition at line 26 of file ppc4xx_edac.h.
| #define PPC_REG_VAL | ( | bit, | |
| val | |||
| ) | ((val) << ((PPC_REG_BITS - 1) - (bit))) |
Definition at line 25 of file ppc4xx_edac.h.
| #define SDRAM_BEARH 0x03 /* Error address high */ |
Definition at line 35 of file ppc4xx_edac.h.
| #define SDRAM_BEARL 0x02 /* Error address low */ |
Definition at line 34 of file ppc4xx_edac.h.
| #define SDRAM_BESR 0x00 /* Error status (read/clear) */ |
Definition at line 32 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 1) |
Definition at line 82 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7) |
Definition at line 80 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0) |
Definition at line 81 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_AHB PPC_REG_VAL(3, SDRAM_PLB_M0ID_AHB) |
Definition at line 79 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, SDRAM_PLB_M0ID_DCU) |
Definition at line 75 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_DECODE | ( | n | ) | PPC_REG_DECODE(3, n) |
Definition at line 70 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, SDRAM_PLB_M0ID_DMA) |
Definition at line 74 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, SDRAM_PLB_M0ID_ICU) |
Definition at line 71 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, SDRAM_PLB_M0ID_MAL) |
Definition at line 77 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF) |
Definition at line 69 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, SDRAM_PLB_M0ID_OPB) |
Definition at line 76 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE0) |
Definition at line 72 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE1) |
Definition at line 73 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, SDRAM_PLB_M0ID_SEC) |
Definition at line 78 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0RW_MASK PPC_REG_VAL(7, 1) |
Definition at line 83 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0RW_READ PPC_REG_VAL(7, 1) |
Definition at line 85 of file ppc4xx_edac.h.
| #define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0) |
Definition at line 84 of file ppc4xx_edac.h.
| #define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF) |
Definition at line 68 of file ppc4xx_edac.h.
| #define SDRAM_BESRT 0x01 /* Error statuss (test/set) */ |
Definition at line 33 of file ppc4xx_edac.h.
| #define SDRAM_ECCCR 0x98 /* ECC error status */ |
Definition at line 45 of file ppc4xx_edac.h.
| #define SDRAM_ECCES SDRAM_ECCCR |
Definition at line 46 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1) |
Definition at line 169 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1) |
Definition at line 170 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3) |
Definition at line 168 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_BNCE_ENCODE | ( | lane | ) | PPC_REG_VAL(((lane) & 0xF), 1) |
Definition at line 159 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF) |
Definition at line 158 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_CE PPC_REG_VAL(18, 1) |
Definition at line 166 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2) |
Definition at line 162 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1) |
Definition at line 163 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3) |
Definition at line 165 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2) |
Definition at line 164 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3) |
Definition at line 160 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0) |
Definition at line 161 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF) |
Definition at line 157 of file ppc4xx_edac.h.
| #define SDRAM_ECCES_UE PPC_REG_VAL(19, 1) |
Definition at line 167 of file ppc4xx_edac.h.
| #define SDRAM_MB0CF SDRAM_MBXCF(0) |
Definition at line 41 of file ppc4xx_edac.h.
| #define SDRAM_MB1CF SDRAM_MBXCF(1) |
Definition at line 42 of file ppc4xx_edac.h.
| #define SDRAM_MB2CF SDRAM_MBXCF(2) |
Definition at line 43 of file ppc4xx_edac.h.
| #define SDRAM_MB3CF SDRAM_MBXCF(3) |
Definition at line 44 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MASK PPC_REG_VAL(23, 0xF) |
Definition at line 139 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE0 PPC_REG_VAL(23, 0x0) |
Definition at line 140 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE1 PPC_REG_VAL(23, 0x1) |
Definition at line 141 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE2 PPC_REG_VAL(23, 0x2) |
Definition at line 142 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE3 PPC_REG_VAL(23, 0x3) |
Definition at line 143 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE4 PPC_REG_VAL(23, 0x4) |
Definition at line 144 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE5 PPC_REG_VAL(23, 0x5) |
Definition at line 145 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE6 PPC_REG_VAL(23, 0x6) |
Definition at line 146 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE7 PPC_REG_VAL(23, 0x7) |
Definition at line 147 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE8 PPC_REG_VAL(23, 0x8) |
Definition at line 148 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_AM_MODE9 PPC_REG_VAL(23, 0x9) |
Definition at line 149 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_BA_MASK PPC_REG_VAL(12, 0x1FFF) |
Definition at line 124 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_BE_DISABLE PPC_REG_VAL(31, 0x0) |
Definition at line 151 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_BE_ENABLE PPC_REG_VAL(31, 0x1) |
Definition at line 152 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_BE_MASK PPC_REG_VAL(31, 0x1) |
Definition at line 150 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_128MB PPC_REG_VAL(19, 0x5) |
Definition at line 132 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_16MB PPC_REG_VAL(19, 0x2) |
Definition at line 129 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_1GB PPC_REG_VAL(19, 0x8) |
Definition at line 135 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_256MB PPC_REG_VAL(19, 0x6) |
Definition at line 133 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_2GB PPC_REG_VAL(19, 0x9) |
Definition at line 136 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_32MB PPC_REG_VAL(19, 0x3) |
Definition at line 130 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_4GB PPC_REG_VAL(19, 0xA) |
Definition at line 137 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_4MB PPC_REG_VAL(19, 0x0) |
Definition at line 127 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_512MB PPC_REG_VAL(19, 0x7) |
Definition at line 134 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_64MB PPC_REG_VAL(19, 0x4) |
Definition at line 131 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_8GB PPC_REG_VAL(19, 0xB) |
Definition at line 138 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_8MB PPC_REG_VAL(19, 0x1) |
Definition at line 128 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_DECODE | ( | mbxcf | ) | PPC_REG_DECODE(19, mbxcf) |
Definition at line 126 of file ppc4xx_edac.h.
| #define SDRAM_MBCF_SZ_MASK PPC_REG_VAL(19, 0xF) |
Definition at line 125 of file ppc4xx_edac.h.
| #define SDRAM_MBXCF | ( | n | ) | (SDRAM_MBXCF_BASE + (4 * (n))) |
Definition at line 40 of file ppc4xx_edac.h.
| #define SDRAM_MBXCF_BASE 0x40 /* Bank n configuration base */ |
Definition at line 39 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1 0x20 /* Controller options 1 */ |
Definition at line 38 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_DDR1_TYPE PPC_REG_VAL(11, 0x0) /* DDR1 type */ |
Definition at line 118 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_DDR2_TYPE PPC_REG_VAL(11, 0x1) /* DDR2 type */ |
Definition at line 119 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_DDR_TYPE_MASK PPC_REG_VAL(11, 0x1) /* DDR type mask */ |
Definition at line 117 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_MCHK_CHK PPC_REG_VAL(3, 0x1) /* ECC gen and chk */ |
Definition at line 109 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_MCHK_CHK_REP PPC_REG_VAL(3, 0x3) /* ECC gen/chk/rpt */ |
Definition at line 110 of file ppc4xx_edac.h.
Definition at line 111 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_MCHK_GEN PPC_REG_VAL(3, 0x2) /* ECC gen */ |
Definition at line 108 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_MCHK_MASK PPC_REG_VAL(3, 0x3) /* ECC mask */ |
Definition at line 106 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_MCHK_NON PPC_REG_VAL(3, 0x0) /* No ECC gen */ |
Definition at line 107 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_RDEN PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM enbl */ |
Definition at line 113 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_RDEN_MASK PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM mask */ |
Definition at line 112 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_WDTH_16 PPC_REG_VAL(7, 0x1) /* 16 bits */ |
Definition at line 116 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_WDTH_32 PPC_REG_VAL(7, 0x0) /* 32 bits */ |
Definition at line 115 of file ppc4xx_edac.h.
| #define SDRAM_MCOPT1_WDTH_MASK PPC_REG_VAL(7, 0x1) /* Width mask */ |
Definition at line 114 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_AHB 8 |
Definition at line 60 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_COUNT |
Definition at line 62 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_DCU 4 |
Definition at line 56 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_DMA 3 |
Definition at line 55 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_FIRST 0 |
Definition at line 51 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_ICU SDRAM_PLB_M0ID_FIRST |
Definition at line 52 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_LAST SDRAM_PLB_M0ID_AHB |
Definition at line 61 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_MAL 6 |
Definition at line 58 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_OPB 5 |
Definition at line 57 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_PCIE0 1 |
Definition at line 53 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_PCIE1 2 |
Definition at line 54 of file ppc4xx_edac.h.
| #define SDRAM_PLB_M0ID_SEC 7 |
Definition at line 59 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ 0x06 /* Write master (read/clear) */ |
Definition at line 36 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_AHB PPC_REG_VAL(SDRAM_PLB_M0ID_AHB, 1) |
Definition at line 101 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_DCU PPC_REG_VAL(SDRAM_PLB_M0ID_DCU, 1) |
Definition at line 97 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_DMA PPC_REG_VAL(SDRAM_PLB_M0ID_DMA, 1) |
Definition at line 96 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_ENCODE | ( | id | ) |
Definition at line 91 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_ICU PPC_REG_VAL(SDRAM_PLB_M0ID_ICU, 1) |
Definition at line 93 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_MAL PPC_REG_VAL(SDRAM_PLB_M0ID_MAL, 1) |
Definition at line 99 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_MASK PPC_REG_VAL(8, 0x1FF) |
Definition at line 90 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_OPB PPC_REG_VAL(SDRAM_PLB_M0ID_OPB, 1) |
Definition at line 98 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_PCIE0 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE0, 1) |
Definition at line 94 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_PCIE1 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE1, 1) |
Definition at line 95 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQ_SEC PPC_REG_VAL(SDRAM_PLB_M0ID_SEC, 1) |
Definition at line 100 of file ppc4xx_edac.h.
| #define SDRAM_WMIRQT 0x07 /* Write master (test/set) */ |
Definition at line 37 of file ppc4xx_edac.h.
1.8.2