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qla3xxx.h
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1 /*
2  * QLogic QLA3xxx NIC HBA Driver
3  * Copyright (c) 2003-2006 QLogic Corporation
4  *
5  * See LICENSE.qla3xxx for copyright and licensing details.
6  */
7 #ifndef _QLA3XXX_H_
8 #define _QLA3XXX_H_
9 
10 /*
11  * IOCB Definitions...
12  */
13 #pragma pack(1)
14 
15 #define OPCODE_OB_MAC_IOCB_FN0 0x01
16 #define OPCODE_OB_MAC_IOCB_FN2 0x21
17 
18 #define OPCODE_IB_MAC_IOCB 0xF9
19 #define OPCODE_IB_3032_MAC_IOCB 0x09
20 #define OPCODE_IB_IP_IOCB 0xFA
21 #define OPCODE_IB_3032_IP_IOCB 0x0A
22 
23 #define OPCODE_FUNC_ID_MASK 0x30
24 #define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */
25 
26 #define FN0_MA_BITS_MASK 0x00
27 #define FN1_MA_BITS_MASK 0x80
28 
32 #define OB_MAC_IOCB_REQ_MA 0xe0
33 #define OB_MAC_IOCB_REQ_F 0x10
34 #define OB_MAC_IOCB_REQ_X 0x08
35 #define OB_MAC_IOCB_REQ_D 0x02
36 #define OB_MAC_IOCB_REQ_I 0x01
38 #define OB_3032MAC_IOCB_REQ_IC 0x04
39 #define OB_3032MAC_IOCB_REQ_TC 0x02
40 #define OB_3032MAC_IOCB_REQ_UC 0x01
42 
43  u32 transaction_id; /* opaque for hardware */
60 };
61 /*
62  * The following constants define control bits for buffer
63  * length fields for all IOCB's.
64  */
65 #define OB_MAC_IOCB_REQ_E 0x80000000 /* Last valid buffer in list. */
66 #define OB_MAC_IOCB_REQ_C 0x40000000 /* points to an OAL. (continuation) */
67 #define OB_MAC_IOCB_REQ_L 0x20000000 /* Auburn local address pointer. */
68 #define OB_MAC_IOCB_REQ_R 0x10000000 /* 32-bit address pointer. */
69 
73 #define OB_MAC_IOCB_RSP_P 0x08
74 #define OB_MAC_IOCB_RSP_L 0x04
75 #define OB_MAC_IOCB_RSP_S 0x02
76 #define OB_MAC_IOCB_RSP_I 0x01
77 
79  u32 transaction_id; /* opaque for hardware */
82 };
83 
86 #define IB_MAC_IOCB_RSP_V 0x80
88 #define IB_MAC_IOCB_RSP_S 0x80
89 #define IB_MAC_IOCB_RSP_H1 0x40
90 #define IB_MAC_IOCB_RSP_H0 0x20
91 #define IB_MAC_IOCB_RSP_B 0x10
92 #define IB_MAC_IOCB_RSP_M 0x08
93 #define IB_MAC_IOCB_RSP_MA 0x07
94 
99 
100 };
101 
105 #define OB_IP_IOCB_REQ_O 0x100
106 #define OB_IP_IOCB_REQ_H 0x008
107 #define OB_IP_IOCB_REQ_U 0x004
108 #define OB_IP_IOCB_REQ_D 0x002
109 #define OB_IP_IOCB_REQ_I 0x001
110 
112 
129 };
130 
131 /* defines for BufferLength fields above */
132 #define OB_IP_IOCB_REQ_E 0x80000000
133 #define OB_IP_IOCB_REQ_C 0x40000000
134 #define OB_IP_IOCB_REQ_L 0x20000000
135 #define OB_IP_IOCB_REQ_R 0x10000000
136 
140 #define OB_MAC_IOCB_RSP_H 0x10
141 #define OB_MAC_IOCB_RSP_E 0x08
142 #define OB_MAC_IOCB_RSP_L 0x04
143 #define OB_MAC_IOCB_RSP_S 0x02
144 #define OB_MAC_IOCB_RSP_I 0x01
145 
150 };
151 
154 #define IB_IP_IOCB_RSP_3032_V 0x80
155 #define IB_IP_IOCB_RSP_3032_O 0x40
156 #define IB_IP_IOCB_RSP_3032_I 0x20
157 #define IB_IP_IOCB_RSP_3032_R 0x10
159 #define IB_IP_IOCB_RSP_S 0x80
160 #define IB_IP_IOCB_RSP_H1 0x40
161 #define IB_IP_IOCB_RSP_H0 0x20
162 #define IB_IP_IOCB_RSP_B 0x10
163 #define IB_IP_IOCB_RSP_M 0x08
164 #define IB_IP_IOCB_RSP_MA 0x07
165 
168 #define IB_IP_IOCB_RSP_3032_ICE 0x01
169 #define IB_IP_IOCB_RSP_3032_CE 0x02
170 #define IB_IP_IOCB_RSP_3032_NUC 0x04
171 #define IB_IP_IOCB_RSP_3032_UDP 0x08
172 #define IB_IP_IOCB_RSP_3032_TCP 0x10
173 #define IB_IP_IOCB_RSP_3032_IPE 0x20
175 #define IB_IP_IOCB_RSP_R 0x01
178 };
179 
180 struct net_rsp_iocb {
185 };
186 #pragma pack()
187 
188 /*
189  * Register Definitions...
190  */
191 #define PORT0_PHY_ADDRESS 0x1e00
192 #define PORT1_PHY_ADDRESS 0x1f00
193 
194 #define ETHERNET_CRC_SIZE 4
195 
196 #define MII_SCAN_REGISTER 0x00000001
197 
198 #define PHY_ID_0_REG 2
199 #define PHY_ID_1_REG 3
200 
201 #define PHY_OUI_1_MASK 0xfc00
202 #define PHY_MODEL_MASK 0x03f0
203 
204 /* Address for the Agere Phy */
205 #define MII_AGERE_ADDR_1 0x00001000
206 #define MII_AGERE_ADDR_2 0x00001100
207 
208 /* 32-bit ispControlStatus */
209 enum {
215  ISP_CONTROL_RI = 0x0008,
216  ISP_CONTROL_CI = 0x0010,
217  ISP_CONTROL_PI = 0x0020,
218  ISP_CONTROL_IN = 0x0040,
219  ISP_CONTROL_BE = 0x0080,
227  ISP_CONTROL_FSR = 0x2000,
228  ISP_CONTROL_FE = 0x4000,
229  ISP_CONTROL_SR = 0x8000,
230 };
231 
232 /* 32-bit ispInterruptMaskReg */
233 enum {
238 };
239 
240 /* 32-bit serialPortInterfaceReg */
241 enum {
246  ISP_NVRAM_MASK = (0x000F << 16),
256 };
257 
258 /* semaphoreReg */
259 enum {
272 };
273 
274  /*
275  * QL3XXX memory-mapped registers
276  * QL3XXX has 4 "pages" of registers, each page occupying
277  * 256 bytes. Each page has a "common" area at the start and then
278  * page-specific registers after that.
279  */
281  u32 MB0; /* Offset 0x00 */
282  u32 MB1; /* Offset 0x04 */
283  u32 MB2; /* Offset 0x08 */
284  u32 MB3; /* Offset 0x0c */
285  u32 MB4; /* Offset 0x10 */
286  u32 MB5; /* Offset 0x14 */
287  u32 MB6; /* Offset 0x18 */
288  u32 MB7; /* Offset 0x1c */
297 
302 };
303 
304 enum {
328 };
329 
330 /* InternalChipConfig */
331 enum {
345 };
346 
347 /* portControl */
348 enum {
349  PORT_CONTROL_DS = 0x0001,
350  PORT_CONTROL_HH = 0x0002,
351  PORT_CONTROL_EI = 0x0004,
352  PORT_CONTROL_ET = 0x0008,
353  PORT_CONTROL_EF = 0x0010,
361  PORT_CONTROL_FI = 0x1000,
363  PORT_CONTROL_OI = 0x4000,
364  PORT_CONTROL_CC = 0x8000,
365 };
366 
367 /* portStatus */
368 enum {
369  PORT_STATUS_SM0 = 0x0001,
370  PORT_STATUS_SM1 = 0x0002,
371  PORT_STATUS_X = 0x0008,
372  PORT_STATUS_DL = 0x0080,
373  PORT_STATUS_IC = 0x0200,
374  PORT_STATUS_MRC = 0x0400,
375  PORT_STATUS_NL = 0x0800,
380  PORT_STATUS_64 = 0x8000,
381  PORT_STATUS_UP0 = 0x10000,
382  PORT_STATUS_AC0 = 0x20000,
383  PORT_STATUS_AE0 = 0x40000,
384  PORT_STATUS_UP1 = 0x100000,
385  PORT_STATUS_AC1 = 0x200000,
386  PORT_STATUS_AE1 = 0x400000,
391 };
392 
393 /* macMIIMgmtControlReg */
394 enum {
405 };
406 
407 /* macMIIMgmtControlReg */
408 enum {
423 };
424 
425 /* macMIIStatusReg */
426 enum {
430 };
431 
432 enum {
440 };
441 
442 enum {
447 };
448 
449 enum {
462 };
463 enum {
474 };
475 
476 enum {
485 };
486 
487 enum {
541 };
542 
543 enum {
569 };
570 
571 /*
572  * port control and status page - page 0
573  */
574 
577 
621 };
622 
623 /*
624  * port host memory config page - page 1
625  */
628 
630 
631  /* Network Request Queue */
638 
639  /* Network Completion Queue */
646 
647  /* RX Large Buffer Queue */
653 
654  /* RX Small Buffer Queue */
660 
661 };
662 
663 /*
664  * port local RAM page - page 2
665  */
684 };
685 
686 /*
687  * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
688  */
689 
690 #define LS_64BITS(x) (u32)(0xffffffff & ((u64)x))
691 #define MS_64BITS(x) (u32)(0xffffffff & (((u64)x)>>16>>16) )
692 
693 /*
694  * I/O register
695  */
696 
697 enum {
702 
710 
714 
716  PETBI_NEG_PAUSE = 0x0080,
720 
723 
726 
728  PHY_GIG_ENABLE_MAN = 0x1000, /* Enable Master/Slave Manual Config*/
729  PHY_GIG_SET_MASTER = 0x0800, /* Set Master (slave if clear)*/
733 
741  PHY_NEG_ADV_10F = 0x0040,
742  PHY_NEG_ADV_10H = 0x0020,
743 
745  PETBI_TBI_RESET = 0x8000,
749 
757  PHY_NEG_PAUSE = 0x0400,
761 };
762 enum {
763 /* AM29LV Flash definitions */
765 /* Commands */
773 /* Command Extensions */
778 /* Special Bits */
783 /* AM29LV Flash definitions */
789 /* Address Bits */
793 /* Data Bits */
796 };
797 enum {
798 /* Auburn Bits */
810 };
814 };
815 
816 /*
817  * MAC Config data structure
818  */
824 #define PORT_CONFIG_DEFAULT 0xf700
825 #define PORT_CONFIG_AUTO_NEG_ENABLED 0x8000
826 #define PORT_CONFIG_SYM_PAUSE_ENABLED 0x4000
827 #define PORT_CONFIG_FULL_DUPLEX_ENABLED 0x2000
828 #define PORT_CONFIG_HALF_DUPLEX_ENABLED 0x1000
829 #define PORT_CONFIG_1000MB_SPEED 0x0400
830 #define PORT_CONFIG_100MB_SPEED 0x0200
831 #define PORT_CONFIG_10MB_SPEED 0x0100
832 #define PORT_CONFIG_LINK_SPEED_MASK 0x0F00
834 
835 };
836 
837 /*
838  * BIOS data structure
839  */
842 
845 
848 
851 };
852 
853 /*
854  * Function Specific Data structure
855  */
860 
863 };
864 
865 /*
866  * EEPROM format
867  */
868 struct eeprom_data {
869  u8 asicId[4];
870  u16 version_and_numPorts; /* together to avoid endianness crap */
872 
873 #define EEPROM_BOARDID_STR_SIZE 16
874 #define EEPROM_SERIAL_NUM_SIZE 16
875 
902 #define IPSEC_CONFIG_PRESENT 0x0001
907  u8 oemSpace[432];
918 };
919 
920 /*
921  * General definitions...
922  */
923 
924 /*
925  * Below are a number compiler switches for controlling driver behavior.
926  * Some are not supported under certain conditions and are notated as such.
927  */
928 
929 #define QL3XXX_VENDOR_ID 0x1077
930 #define QL3022_DEVICE_ID 0x3022
931 #define QL3032_DEVICE_ID 0x3032
932 
933 /* MTU & Frame Size stuff */
934 #define NORMAL_MTU_SIZE ETH_DATA_LEN
935 #define JUMBO_MTU_SIZE 9000
936 #define VLAN_ID_LEN 2
937 
938 /* Request Queue Related Definitions */
939 #define NUM_REQ_Q_ENTRIES 256 /* so that 64 * 64 = 4096 (1 page) */
940 
941 /* Response Queue Related Definitions */
942 #define NUM_RSP_Q_ENTRIES 256 /* so that 256 * 16 = 4096 (1 page) */
943 
944 /* Transmit and Receive Buffers */
945 #define NUM_LBUFQ_ENTRIES 128
946 #define JUMBO_NUM_LBUFQ_ENTRIES 32
947 #define NUM_SBUFQ_ENTRIES 64
948 #define QL_SMALL_BUFFER_SIZE 32
949 #define QL_ADDR_ELE_PER_BUFQ_ENTRY \
950 (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
951  /* Each send has at least control block. This is how many we keep. */
952 #define NUM_SMALL_BUFFERS NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
953 
954 #define QL_HEADER_SPACE 32 /* make header space at top of skb. */
955 /*
956  * Large & Small Buffers for Receives
957  */
959 
961 #define IAL_LAST_ENTRY 0x00000001
962 #define IAL_CONT_ENTRY 0x00000002
963 #define IAL_FLAG_MASK 0x00000003
979 
980 };
981 
985 };
986 
987 #define QL_NO_RESET 0
988 #define QL_DO_RESET 1
989 
996 };
997 
1000  struct sk_buff *skb;
1001  DEFINE_DMA_UNMAP_ADDR(mapaddr);
1002  DEFINE_DMA_UNMAP_LEN(maplen);
1005  int index;
1006 };
1007 
1008 /*
1009  * Original IOCB has 3 sg entries:
1010  * first points to skb-data area
1011  * second points to first frag
1012  * third points to next oal.
1013  * OAL has 5 entries:
1014  * 1 thru 4 point to frags
1015  * fifth points to next oal.
1016  */
1017 #define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
1018 
1019 struct oal_entry {
1023 #define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */
1024 #define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */
1025 };
1026 
1027 struct oal {
1029 };
1030 
1031 struct map_list {
1032  DEFINE_DMA_UNMAP_ADDR(mapaddr);
1033  DEFINE_DMA_UNMAP_LEN(maplen);
1034 };
1035 
1037  struct sk_buff *skb;
1040  struct oal *oal;
1042 };
1043 
1044 /* definitions for type field */
1045 #define QL_BUF_TYPE_MACIOCB 0x01
1046 #define QL_BUF_TYPE_IPIOCB 0x02
1047 #define QL_BUF_TYPE_TCPIOCB 0x03
1048 
1049 /* qdev->flags definitions. */
1050 enum { QL_RESET_DONE = 1, /* Reset finished. */
1051  QL_RESET_ACTIVE = 2, /* Waiting for reset to finish. */
1052  QL_RESET_START = 3, /* Please reset the chip. */
1053  QL_RESET_PER_SCSI = 4, /* SCSI driver requests reset. */
1054  QL_TX_TIMEOUT = 5, /* Timeout in progress. */
1055  QL_LINK_MASTER = 6, /* This driver controls the link. */
1056  QL_ADAPTER_UP = 7, /* Adapter has been brought up. */
1057  QL_THREAD_UP = 8, /* This flag is available. */
1058  QL_LINK_UP = 9, /* Link Status. */
1064 };
1065 
1066 /*
1067  * ql3_adapter - The main Adapter structure definition.
1068  * This structure has all fields relevant to the hardware.
1069  */
1070 
1071 struct ql3_adapter {
1073  unsigned long flags;
1074 
1075  /* PCI Configuration information for this device */
1076  struct pci_dev *pdev;
1077  struct net_device *ndev; /* Parent NET device */
1078 
1080 
1081  /* Hardware information */
1087  int index;
1088  struct timer_list adapter_timer; /* timer used for various functions */
1089 
1092 
1093  /* PCI Bus Relative Register Addresses */
1094  u8 __iomem *mmap_virt_base; /* stores return value from ioremap() */
1096  u32 current_page; /* tracks current register page */
1097 
1101 
1102  /* Page for Shadow Registers */
1105 
1106  /* Net Request Queue */
1118 
1119  /* Net Response Queue */
1130 
1131  /* Large Buffer Queue */
1143 
1144  /* Large (Receive) Buffers */
1152 
1153  /* Small Buffer Queue */
1162 
1163  /* Small (Receive) Buffers */
1170 
1173 
1174  /* 4022 specific */
1175  u32 mac_index; /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
1176  u32 PHYAddr; /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
1177  u32 mac_ob_opcode; /* Opcode to use on mac transmission */
1178  u32 mb_bit_mask; /* MA Bits mask to use on transmission */
1187 };
1188 
1189 #endif /* _QLA3XXX_H_ */