|
| enum | {
ISP_CONTROL_NP_MASK = 0x0003,
ISP_CONTROL_NP_PCSR = 0x0000,
ISP_CONTROL_NP_HMCR = 0x0001,
ISP_CONTROL_NP_LRAMCR = 0x0002,
ISP_CONTROL_NP_PSR = 0x0003,
ISP_CONTROL_RI = 0x0008,
ISP_CONTROL_CI = 0x0010,
ISP_CONTROL_PI = 0x0020,
ISP_CONTROL_IN = 0x0040,
ISP_CONTROL_BE = 0x0080,
ISP_CONTROL_FN_MASK = 0x0700,
ISP_CONTROL_FN0_NET = 0x0400,
ISP_CONTROL_FN0_SCSI = 0x0500,
ISP_CONTROL_FN1_NET = 0x0600,
ISP_CONTROL_FN1_SCSI = 0x0700,
ISP_CONTROL_LINK_DN_0 = 0x0800,
ISP_CONTROL_LINK_DN_1 = 0x1000,
ISP_CONTROL_FSR = 0x2000,
ISP_CONTROL_FE = 0x4000,
ISP_CONTROL_SR = 0x8000
} |
| |
| enum | { ISP_IMR_ENABLE_INT = 0x0004,
ISP_IMR_DISABLE_RESET_INT = 0x0008,
ISP_IMR_DISABLE_CMPL_INT = 0x0010,
ISP_IMR_DISABLE_PROC_INT = 0x0020
} |
| |
| enum | {
ISP_SERIAL_PORT_IF_CLK = 0x0001,
ISP_SERIAL_PORT_IF_CS = 0x0002,
ISP_SERIAL_PORT_IF_D0 = 0x0004,
ISP_SERIAL_PORT_IF_DI = 0x0008,
ISP_NVRAM_MASK = (0x000F << 16),
ISP_SERIAL_PORT_IF_WE = 0x0010,
ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
ISP_SERIAL_PORT_IF_SCI = 0x0400,
ISP_SERIAL_PORT_IF_SC0 = 0x0800,
ISP_SERIAL_PORT_IF_SCE = 0x1000,
ISP_SERIAL_PORT_IF_SDI = 0x2000,
ISP_SERIAL_PORT_IF_SDO = 0x4000,
ISP_SERIAL_PORT_IF_SDE = 0x8000,
ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00
} |
| |
| enum | {
QL_RESOURCE_MASK_BASE_CODE = 0x7,
QL_RESOURCE_BITS_BASE_CODE = 0x4,
QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16))
} |
| |
| enum | {
EXT_HW_CONFIG_SP_MASK = 0x0006,
EXT_HW_CONFIG_SP_NONE = 0x0000,
EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
EXT_HW_CONFIG_SP_ECC = 0x0004,
EXT_HW_CONFIG_SP_ECCx = 0x0006,
EXT_HW_CONFIG_SIZE_MASK = 0x0060,
EXT_HW_CONFIG_SIZE_128M = 0x0000,
EXT_HW_CONFIG_SIZE_256M = 0x0020,
EXT_HW_CONFIG_SIZE_512M = 0x0040,
EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
EXT_HW_CONFIG_PD = 0x0080,
EXT_HW_CONFIG_FW = 0x0200,
EXT_HW_CONFIG_US = 0x0400,
EXT_HW_CONFIG_DCS_MASK = 0x1800,
EXT_HW_CONFIG_DCS_9MA = 0x0000,
EXT_HW_CONFIG_DCS_15MA = 0x0800,
EXT_HW_CONFIG_DCS_18MA = 0x1000,
EXT_HW_CONFIG_DCS_24MA = 0x1800,
EXT_HW_CONFIG_DDS_MASK = 0x6000,
EXT_HW_CONFIG_DDS_9MA = 0x0000,
EXT_HW_CONFIG_DDS_15MA = 0x2000,
EXT_HW_CONFIG_DDS_18MA = 0x4000,
EXT_HW_CONFIG_DDS_24MA = 0x6000
} |
| |
| enum | {
INTERNAL_CHIP_DM = 0x0001,
INTERNAL_CHIP_SD = 0x0002,
INTERNAL_CHIP_RAP_MASK = 0x000C,
INTERNAL_CHIP_RAP_RR = 0x0000,
INTERNAL_CHIP_RAP_NRM = 0x0004,
INTERNAL_CHIP_RAP_ERM = 0x0008,
INTERNAL_CHIP_RAP_ERMx = 0x000C,
INTERNAL_CHIP_WE = 0x0010,
INTERNAL_CHIP_EF = 0x0020,
INTERNAL_CHIP_FR = 0x0040,
INTERNAL_CHIP_FW = 0x0080,
INTERNAL_CHIP_FI = 0x0100,
INTERNAL_CHIP_FT = 0x0200
} |
| |
| enum | {
PORT_CONTROL_DS = 0x0001,
PORT_CONTROL_HH = 0x0002,
PORT_CONTROL_EI = 0x0004,
PORT_CONTROL_ET = 0x0008,
PORT_CONTROL_EF = 0x0010,
PORT_CONTROL_DRM = 0x0020,
PORT_CONTROL_RLB = 0x0040,
PORT_CONTROL_RCB = 0x0080,
PORT_CONTROL_MAC = 0x0100,
PORT_CONTROL_IPV = 0x0200,
PORT_CONTROL_IFP = 0x0400,
PORT_CONTROL_ITP = 0x0800,
PORT_CONTROL_FI = 0x1000,
PORT_CONTROL_DFP = 0x2000,
PORT_CONTROL_OI = 0x4000,
PORT_CONTROL_CC = 0x8000
} |
| |
| enum | {
PORT_STATUS_SM0 = 0x0001,
PORT_STATUS_SM1 = 0x0002,
PORT_STATUS_X = 0x0008,
PORT_STATUS_DL = 0x0080,
PORT_STATUS_IC = 0x0200,
PORT_STATUS_MRC = 0x0400,
PORT_STATUS_NL = 0x0800,
PORT_STATUS_REV_ID_MASK = 0x7000,
PORT_STATUS_REV_ID_1 = 0x1000,
PORT_STATUS_REV_ID_2 = 0x2000,
PORT_STATUS_REV_ID_3 = 0x3000,
PORT_STATUS_64 = 0x8000,
PORT_STATUS_UP0 = 0x10000,
PORT_STATUS_AC0 = 0x20000,
PORT_STATUS_AE0 = 0x40000,
PORT_STATUS_UP1 = 0x100000,
PORT_STATUS_AC1 = 0x200000,
PORT_STATUS_AE1 = 0x400000,
PORT_STATUS_F0_ENABLED = 0x1000000,
PORT_STATUS_F1_ENABLED = 0x2000000,
PORT_STATUS_F2_ENABLED = 0x4000000,
PORT_STATUS_F3_ENABLED = 0x8000000
} |
| |
| enum | {
MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080
} |
| |
| enum | {
MAC_MII_CONTROL_RC = 0x0001,
MAC_MII_CONTROL_SC = 0x0002,
MAC_MII_CONTROL_AS = 0x0004,
MAC_MII_CONTROL_NP = 0x0008,
MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
MAC_MII_CONTROL_RM = 0x8000
} |
| |
| enum | { MAC_MII_STATUS_BSY = 0x0001,
MAC_MII_STATUS_SC = 0x0002,
MAC_MII_STATUS_NV = 0x0004
} |
| |
| enum | {
MAC_CONFIG_REG_PE = 0x0001,
MAC_CONFIG_REG_TF = 0x0002,
MAC_CONFIG_REG_RF = 0x0004,
MAC_CONFIG_REG_FD = 0x0008,
MAC_CONFIG_REG_GM = 0x0010,
MAC_CONFIG_REG_LB = 0x0020,
MAC_CONFIG_REG_SR = 0x8000
} |
| |
| enum | { MAC_HALF_DUPLEX_REG_ED = 0x10000,
MAC_HALF_DUPLEX_REG_NB = 0x20000,
MAC_HALF_DUPLEX_REG_BNB = 0x40000,
MAC_HALF_DUPLEX_REG_ALT = 0x80000
} |
| |
| enum | {
IP_ADDR_INDEX_REG_MASK = 0x000f,
IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
IP_ADDR_INDEX_REG_6 = 0x0008,
IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
IP_ADDR_INDEX_REG_E = 0x0040
} |
| |
| enum | {
QL3032_PORT_CONTROL_DS = 0x0001,
QL3032_PORT_CONTROL_HH = 0x0002,
QL3032_PORT_CONTROL_EIv6 = 0x0004,
QL3032_PORT_CONTROL_EIv4 = 0x0008,
QL3032_PORT_CONTROL_ET = 0x0010,
QL3032_PORT_CONTROL_EF = 0x0020,
QL3032_PORT_CONTROL_DRM = 0x0040,
QL3032_PORT_CONTROL_RLB = 0x0080,
QL3032_PORT_CONTROL_RCB = 0x0100,
QL3032_PORT_CONTROL_KIE = 0x0200
} |
| |
| enum | {
PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
PROBE_MUX_ADDR_REG_UP = 0x4000,
PROBE_MUX_ADDR_REG_RE = 0x8000
} |
| |
| enum | {
STATISTICS_INDEX_REG_MASK = 0x01ff,
STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f
} |
| |
| enum | {
PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
PORT_FATAL_ERROR_STATUS_OCE = 0x01000000
} |
| |
| enum | {
CONTROL_REG = 0,
STATUS_REG = 1,
PHY_STAT_LINK_UP = 0x0004,
PHY_CTRL_LOOPBACK = 0x4000,
PETBI_CONTROL_REG = 0x00,
PETBI_CTRL_ALL_PARAMS = 0x7140,
PETBI_CTRL_SOFT_RESET = 0x8000,
PETBI_CTRL_AUTO_NEG = 0x1000,
PETBI_CTRL_RESTART_NEG = 0x0200,
PETBI_CTRL_FULL_DUPLEX = 0x0100,
PETBI_CTRL_SPEED_1000 = 0x0040,
PETBI_STATUS_REG = 0x01,
PETBI_STAT_NEG_DONE = 0x0020,
PETBI_STAT_LINK_UP = 0x0004,
PETBI_NEG_ADVER = 0x04,
PETBI_NEG_PAUSE = 0x0080,
PETBI_NEG_PAUSE_MASK = 0x0180,
PETBI_NEG_DUPLEX = 0x0020,
PETBI_NEG_DUPLEX_MASK = 0x0060,
PETBI_NEG_PARTNER = 0x05,
PETBI_NEG_ERROR_MASK = 0x3000,
PETBI_EXPANSION_REG = 0x06,
PETBI_EXP_PAGE_RX = 0x0002,
PHY_GIG_CONTROL = 9,
PHY_GIG_ENABLE_MAN = 0x1000,
PHY_GIG_SET_MASTER = 0x0800,
PHY_GIG_ALL_PARAMS = 0x0300,
PHY_GIG_ADV_1000F = 0x0200,
PHY_GIG_ADV_1000H = 0x0100,
PHY_NEG_ADVER = 4,
PHY_NEG_ALL_PARAMS = 0x0fe0,
PHY_NEG_ASY_PAUSE = 0x0800,
PHY_NEG_SYM_PAUSE = 0x0400,
PHY_NEG_ADV_SPEED = 0x01e0,
PHY_NEG_ADV_100F = 0x0100,
PHY_NEG_ADV_100H = 0x0080,
PHY_NEG_ADV_10F = 0x0040,
PHY_NEG_ADV_10H = 0x0020,
PETBI_TBI_CTRL = 0x11,
PETBI_TBI_RESET = 0x8000,
PETBI_TBI_AUTO_SENSE = 0x0100,
PETBI_TBI_SERDES_MODE = 0x0010,
PETBI_TBI_SERDES_WRAP = 0x0002,
AUX_CONTROL_STATUS = 0x1c,
PHY_AUX_NEG_DONE = 0x8000,
PHY_NEG_PARTNER = 5,
PHY_AUX_DUPLEX_STAT = 0x0020,
PHY_AUX_SPEED_STAT = 0x0018,
PHY_AUX_NO_HW_STRAP = 0x0004,
PHY_AUX_RESET_STICK = 0x0002,
PHY_NEG_PAUSE = 0x0400,
PHY_CTRL_SOFT_RESET = 0x8000,
PHY_CTRL_AUTO_NEG = 0x1000,
PHY_CTRL_RESTART_NEG = 0x0200
} |
| |
| enum | {
FM93C56A_START = 0x1,
FM93C56A_READ = 0x2,
FM93C56A_WEN = 0x0,
FM93C56A_WRITE = 0x1,
FM93C56A_WRITE_ALL = 0x0,
FM93C56A_WDS = 0x0,
FM93C56A_ERASE = 0x3,
FM93C56A_ERASE_ALL = 0x0,
FM93C56A_WEN_EXT = 0x3,
FM93C56A_WRITE_ALL_EXT = 0x1,
FM93C56A_WDS_EXT = 0x0,
FM93C56A_ERASE_ALL_EXT = 0x2,
FM93C56A_READ_DUMMY_BITS = 1,
FM93C56A_READY = 0,
FM93C56A_BUSY = 1,
FM93C56A_CMD_BITS = 2,
FM93C56A_SIZE_8 = 0x100,
FM93C56A_SIZE_16 = 0x80,
FM93C66A_SIZE_8 = 0x200,
FM93C66A_SIZE_16 = 0x100,
FM93C86A_SIZE_16 = 0x400,
FM93C56A_NO_ADDR_BITS_16 = 8,
FM93C56A_NO_ADDR_BITS_8 = 9,
FM93C86A_NO_ADDR_BITS_16 = 10,
FM93C56A_DATA_BITS_16 = 16,
FM93C56A_DATA_BITS_8 = 8
} |
| |
| enum | {
AUBURN_EEPROM_DI = 0x8,
AUBURN_EEPROM_DI_0 = 0x0,
AUBURN_EEPROM_DI_1 = 0x8,
AUBURN_EEPROM_DO = 0x4,
AUBURN_EEPROM_DO_0 = 0x0,
AUBURN_EEPROM_DO_1 = 0x4,
AUBURN_EEPROM_CS = 0x2,
AUBURN_EEPROM_CS_0 = 0x0,
AUBURN_EEPROM_CS_1 = 0x2,
AUBURN_EEPROM_CLK_RISE = 0x1,
AUBURN_EEPROM_CLK_FALL = 0x0
} |
| |
| enum | { EEPROM_SIZE = FM93C86A_SIZE_16,
EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16
} |
| |
| enum | link_state_t {
LS_UNKNOWN = 0,
LS_DOWN,
LS_DEGRADE,
LS_RECOVER,
LS_UP
} |
| |
| enum | {
QL_RESET_DONE = 1,
QL_RESET_ACTIVE = 2,
QL_RESET_START = 3,
QL_RESET_PER_SCSI = 4,
QL_TX_TIMEOUT = 5,
QL_LINK_MASTER = 6,
QL_ADAPTER_UP = 7,
QL_THREAD_UP = 8,
QL_LINK_UP = 9,
QL_ALLOC_REQ_RSP_Q_DONE = 10,
QL_ALLOC_BUFQS_DONE = 11,
QL_ALLOC_SMALL_BUF_DONE = 12,
QL_LINK_OPTICAL = 13,
QL_MSI_ENABLED = 14
} |
| |
1.8.2