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Data Structures | Macros | Enumerations
qla3xxx.h File Reference

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Data Structures

struct  ob_mac_iocb_req
 
struct  ob_mac_iocb_rsp
 
struct  ib_mac_iocb_rsp
 
struct  ob_ip_iocb_req
 
struct  ob_ip_iocb_rsp
 
struct  ib_ip_iocb_rsp
 
struct  net_rsp_iocb
 
struct  ql3xxx_common_registers
 
struct  ql3xxx_port_registers
 
struct  ql3xxx_host_memory_registers
 
struct  ql3xxx_local_ram_registers
 
struct  eeprom_port_cfg
 
struct  eeprom_bios_cfg
 
struct  eeprom_function_cfg
 
struct  eeprom_data
 
struct  lrg_buf_q_entry
 
struct  bufq_addr_element
 
struct  ql_rcv_buf_cb
 
struct  oal_entry
 
struct  oal
 
struct  map_list
 
struct  ql_tx_buf_cb
 
struct  ql3_adapter
 

Macros

#define OPCODE_OB_MAC_IOCB_FN0   0x01
 
#define OPCODE_OB_MAC_IOCB_FN2   0x21
 
#define OPCODE_IB_MAC_IOCB   0xF9
 
#define OPCODE_IB_3032_MAC_IOCB   0x09
 
#define OPCODE_IB_IP_IOCB   0xFA
 
#define OPCODE_IB_3032_IP_IOCB   0x0A
 
#define OPCODE_FUNC_ID_MASK   0x30
 
#define OUTBOUND_MAC_IOCB   0x01 /* plus function bits */
 
#define FN0_MA_BITS_MASK   0x00
 
#define FN1_MA_BITS_MASK   0x80
 
#define OB_MAC_IOCB_REQ_MA   0xe0
 
#define OB_MAC_IOCB_REQ_F   0x10
 
#define OB_MAC_IOCB_REQ_X   0x08
 
#define OB_MAC_IOCB_REQ_D   0x02
 
#define OB_MAC_IOCB_REQ_I   0x01
 
#define OB_3032MAC_IOCB_REQ_IC   0x04
 
#define OB_3032MAC_IOCB_REQ_TC   0x02
 
#define OB_3032MAC_IOCB_REQ_UC   0x01
 
#define OB_MAC_IOCB_REQ_E   0x80000000 /* Last valid buffer in list. */
 
#define OB_MAC_IOCB_REQ_C   0x40000000 /* points to an OAL. (continuation) */
 
#define OB_MAC_IOCB_REQ_L   0x20000000 /* Auburn local address pointer. */
 
#define OB_MAC_IOCB_REQ_R   0x10000000 /* 32-bit address pointer. */
 
#define OB_MAC_IOCB_RSP_P   0x08
 
#define OB_MAC_IOCB_RSP_L   0x04
 
#define OB_MAC_IOCB_RSP_S   0x02
 
#define OB_MAC_IOCB_RSP_I   0x01
 
#define IB_MAC_IOCB_RSP_V   0x80
 
#define IB_MAC_IOCB_RSP_S   0x80
 
#define IB_MAC_IOCB_RSP_H1   0x40
 
#define IB_MAC_IOCB_RSP_H0   0x20
 
#define IB_MAC_IOCB_RSP_B   0x10
 
#define IB_MAC_IOCB_RSP_M   0x08
 
#define IB_MAC_IOCB_RSP_MA   0x07
 
#define OB_IP_IOCB_REQ_O   0x100
 
#define OB_IP_IOCB_REQ_H   0x008
 
#define OB_IP_IOCB_REQ_U   0x004
 
#define OB_IP_IOCB_REQ_D   0x002
 
#define OB_IP_IOCB_REQ_I   0x001
 
#define OB_IP_IOCB_REQ_E   0x80000000
 
#define OB_IP_IOCB_REQ_C   0x40000000
 
#define OB_IP_IOCB_REQ_L   0x20000000
 
#define OB_IP_IOCB_REQ_R   0x10000000
 
#define OB_MAC_IOCB_RSP_H   0x10
 
#define OB_MAC_IOCB_RSP_E   0x08
 
#define OB_MAC_IOCB_RSP_L   0x04
 
#define OB_MAC_IOCB_RSP_S   0x02
 
#define OB_MAC_IOCB_RSP_I   0x01
 
#define IB_IP_IOCB_RSP_3032_V   0x80
 
#define IB_IP_IOCB_RSP_3032_O   0x40
 
#define IB_IP_IOCB_RSP_3032_I   0x20
 
#define IB_IP_IOCB_RSP_3032_R   0x10
 
#define IB_IP_IOCB_RSP_S   0x80
 
#define IB_IP_IOCB_RSP_H1   0x40
 
#define IB_IP_IOCB_RSP_H0   0x20
 
#define IB_IP_IOCB_RSP_B   0x10
 
#define IB_IP_IOCB_RSP_M   0x08
 
#define IB_IP_IOCB_RSP_MA   0x07
 
#define IB_IP_IOCB_RSP_3032_ICE   0x01
 
#define IB_IP_IOCB_RSP_3032_CE   0x02
 
#define IB_IP_IOCB_RSP_3032_NUC   0x04
 
#define IB_IP_IOCB_RSP_3032_UDP   0x08
 
#define IB_IP_IOCB_RSP_3032_TCP   0x10
 
#define IB_IP_IOCB_RSP_3032_IPE   0x20
 
#define IB_IP_IOCB_RSP_R   0x01
 
#define PORT0_PHY_ADDRESS   0x1e00
 
#define PORT1_PHY_ADDRESS   0x1f00
 
#define ETHERNET_CRC_SIZE   4
 
#define MII_SCAN_REGISTER   0x00000001
 
#define PHY_ID_0_REG   2
 
#define PHY_ID_1_REG   3
 
#define PHY_OUI_1_MASK   0xfc00
 
#define PHY_MODEL_MASK   0x03f0
 
#define MII_AGERE_ADDR_1   0x00001000
 
#define MII_AGERE_ADDR_2   0x00001100
 
#define LS_64BITS(x)   (u32)(0xffffffff & ((u64)x))
 
#define MS_64BITS(x)   (u32)(0xffffffff & (((u64)x)>>16>>16) )
 
#define PORT_CONFIG_DEFAULT   0xf700
 
#define PORT_CONFIG_AUTO_NEG_ENABLED   0x8000
 
#define PORT_CONFIG_SYM_PAUSE_ENABLED   0x4000
 
#define PORT_CONFIG_FULL_DUPLEX_ENABLED   0x2000
 
#define PORT_CONFIG_HALF_DUPLEX_ENABLED   0x1000
 
#define PORT_CONFIG_1000MB_SPEED   0x0400
 
#define PORT_CONFIG_100MB_SPEED   0x0200
 
#define PORT_CONFIG_10MB_SPEED   0x0100
 
#define PORT_CONFIG_LINK_SPEED_MASK   0x0F00
 
#define EEPROM_BOARDID_STR_SIZE   16
 
#define EEPROM_SERIAL_NUM_SIZE   16
 
#define IPSEC_CONFIG_PRESENT   0x0001
 
#define QL3XXX_VENDOR_ID   0x1077
 
#define QL3022_DEVICE_ID   0x3022
 
#define QL3032_DEVICE_ID   0x3032
 
#define NORMAL_MTU_SIZE   ETH_DATA_LEN
 
#define JUMBO_MTU_SIZE   9000
 
#define VLAN_ID_LEN   2
 
#define NUM_REQ_Q_ENTRIES   256 /* so that 64 * 64 = 4096 (1 page) */
 
#define NUM_RSP_Q_ENTRIES   256 /* so that 256 * 16 = 4096 (1 page) */
 
#define NUM_LBUFQ_ENTRIES   128
 
#define JUMBO_NUM_LBUFQ_ENTRIES   32
 
#define NUM_SBUFQ_ENTRIES   64
 
#define QL_SMALL_BUFFER_SIZE   32
 
#define QL_ADDR_ELE_PER_BUFQ_ENTRY   (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
 
#define NUM_SMALL_BUFFERS   NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
 
#define QL_HEADER_SPACE   32 /* make header space at top of skb. */
 
#define IAL_LAST_ENTRY   0x00000001
 
#define IAL_CONT_ENTRY   0x00000002
 
#define IAL_FLAG_MASK   0x00000003
 
#define QL_NO_RESET   0
 
#define QL_DO_RESET   1
 
#define MAX_OAL_CNT   ((MAX_SKB_FRAGS-1)/4 + 1)
 
#define OAL_LAST_ENTRY   0x80000000 /* Last valid buffer in list. */
 
#define OAL_CONT_ENTRY   0x40000000 /* points to an OAL. (continuation) */
 
#define QL_BUF_TYPE_MACIOCB   0x01
 
#define QL_BUF_TYPE_IPIOCB   0x02
 
#define QL_BUF_TYPE_TCPIOCB   0x03
 

Enumerations

enum  {
  ISP_CONTROL_NP_MASK = 0x0003, ISP_CONTROL_NP_PCSR = 0x0000, ISP_CONTROL_NP_HMCR = 0x0001, ISP_CONTROL_NP_LRAMCR = 0x0002,
  ISP_CONTROL_NP_PSR = 0x0003, ISP_CONTROL_RI = 0x0008, ISP_CONTROL_CI = 0x0010, ISP_CONTROL_PI = 0x0020,
  ISP_CONTROL_IN = 0x0040, ISP_CONTROL_BE = 0x0080, ISP_CONTROL_FN_MASK = 0x0700, ISP_CONTROL_FN0_NET = 0x0400,
  ISP_CONTROL_FN0_SCSI = 0x0500, ISP_CONTROL_FN1_NET = 0x0600, ISP_CONTROL_FN1_SCSI = 0x0700, ISP_CONTROL_LINK_DN_0 = 0x0800,
  ISP_CONTROL_LINK_DN_1 = 0x1000, ISP_CONTROL_FSR = 0x2000, ISP_CONTROL_FE = 0x4000, ISP_CONTROL_SR = 0x8000
}
 
enum  { ISP_IMR_ENABLE_INT = 0x0004, ISP_IMR_DISABLE_RESET_INT = 0x0008, ISP_IMR_DISABLE_CMPL_INT = 0x0010, ISP_IMR_DISABLE_PROC_INT = 0x0020 }
 
enum  {
  ISP_SERIAL_PORT_IF_CLK = 0x0001, ISP_SERIAL_PORT_IF_CS = 0x0002, ISP_SERIAL_PORT_IF_D0 = 0x0004, ISP_SERIAL_PORT_IF_DI = 0x0008,
  ISP_NVRAM_MASK = (0x000F << 16), ISP_SERIAL_PORT_IF_WE = 0x0010, ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F, ISP_SERIAL_PORT_IF_SCI = 0x0400,
  ISP_SERIAL_PORT_IF_SC0 = 0x0800, ISP_SERIAL_PORT_IF_SCE = 0x1000, ISP_SERIAL_PORT_IF_SDI = 0x2000, ISP_SERIAL_PORT_IF_SDO = 0x4000,
  ISP_SERIAL_PORT_IF_SDE = 0x8000, ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00
}
 
enum  {
  QL_RESOURCE_MASK_BASE_CODE = 0x7, QL_RESOURCE_BITS_BASE_CODE = 0x4, QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1), QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
  QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7), QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10), QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13), QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
  QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)), QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)), QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)), QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16))
}
 
enum  {
  EXT_HW_CONFIG_SP_MASK = 0x0006, EXT_HW_CONFIG_SP_NONE = 0x0000, EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002, EXT_HW_CONFIG_SP_ECC = 0x0004,
  EXT_HW_CONFIG_SP_ECCx = 0x0006, EXT_HW_CONFIG_SIZE_MASK = 0x0060, EXT_HW_CONFIG_SIZE_128M = 0x0000, EXT_HW_CONFIG_SIZE_256M = 0x0020,
  EXT_HW_CONFIG_SIZE_512M = 0x0040, EXT_HW_CONFIG_SIZE_INVALID = 0x0060, EXT_HW_CONFIG_PD = 0x0080, EXT_HW_CONFIG_FW = 0x0200,
  EXT_HW_CONFIG_US = 0x0400, EXT_HW_CONFIG_DCS_MASK = 0x1800, EXT_HW_CONFIG_DCS_9MA = 0x0000, EXT_HW_CONFIG_DCS_15MA = 0x0800,
  EXT_HW_CONFIG_DCS_18MA = 0x1000, EXT_HW_CONFIG_DCS_24MA = 0x1800, EXT_HW_CONFIG_DDS_MASK = 0x6000, EXT_HW_CONFIG_DDS_9MA = 0x0000,
  EXT_HW_CONFIG_DDS_15MA = 0x2000, EXT_HW_CONFIG_DDS_18MA = 0x4000, EXT_HW_CONFIG_DDS_24MA = 0x6000
}
 
enum  {
  INTERNAL_CHIP_DM = 0x0001, INTERNAL_CHIP_SD = 0x0002, INTERNAL_CHIP_RAP_MASK = 0x000C, INTERNAL_CHIP_RAP_RR = 0x0000,
  INTERNAL_CHIP_RAP_NRM = 0x0004, INTERNAL_CHIP_RAP_ERM = 0x0008, INTERNAL_CHIP_RAP_ERMx = 0x000C, INTERNAL_CHIP_WE = 0x0010,
  INTERNAL_CHIP_EF = 0x0020, INTERNAL_CHIP_FR = 0x0040, INTERNAL_CHIP_FW = 0x0080, INTERNAL_CHIP_FI = 0x0100,
  INTERNAL_CHIP_FT = 0x0200
}
 
enum  {
  PORT_CONTROL_DS = 0x0001, PORT_CONTROL_HH = 0x0002, PORT_CONTROL_EI = 0x0004, PORT_CONTROL_ET = 0x0008,
  PORT_CONTROL_EF = 0x0010, PORT_CONTROL_DRM = 0x0020, PORT_CONTROL_RLB = 0x0040, PORT_CONTROL_RCB = 0x0080,
  PORT_CONTROL_MAC = 0x0100, PORT_CONTROL_IPV = 0x0200, PORT_CONTROL_IFP = 0x0400, PORT_CONTROL_ITP = 0x0800,
  PORT_CONTROL_FI = 0x1000, PORT_CONTROL_DFP = 0x2000, PORT_CONTROL_OI = 0x4000, PORT_CONTROL_CC = 0x8000
}
 
enum  {
  PORT_STATUS_SM0 = 0x0001, PORT_STATUS_SM1 = 0x0002, PORT_STATUS_X = 0x0008, PORT_STATUS_DL = 0x0080,
  PORT_STATUS_IC = 0x0200, PORT_STATUS_MRC = 0x0400, PORT_STATUS_NL = 0x0800, PORT_STATUS_REV_ID_MASK = 0x7000,
  PORT_STATUS_REV_ID_1 = 0x1000, PORT_STATUS_REV_ID_2 = 0x2000, PORT_STATUS_REV_ID_3 = 0x3000, PORT_STATUS_64 = 0x8000,
  PORT_STATUS_UP0 = 0x10000, PORT_STATUS_AC0 = 0x20000, PORT_STATUS_AE0 = 0x40000, PORT_STATUS_UP1 = 0x100000,
  PORT_STATUS_AC1 = 0x200000, PORT_STATUS_AE1 = 0x400000, PORT_STATUS_F0_ENABLED = 0x1000000, PORT_STATUS_F1_ENABLED = 0x2000000,
  PORT_STATUS_F2_ENABLED = 0x4000000, PORT_STATUS_F3_ENABLED = 0x8000000
}
 
enum  {
  MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003, MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000, MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001, MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
  MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003, MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008, MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010, MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
  MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040, MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080
}
 
enum  {
  MAC_MII_CONTROL_RC = 0x0001, MAC_MII_CONTROL_SC = 0x0002, MAC_MII_CONTROL_AS = 0x0004, MAC_MII_CONTROL_NP = 0x0008,
  MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070, MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000, MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010, MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
  MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030, MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040, MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050, MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
  MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070, MAC_MII_CONTROL_RM = 0x8000
}
 
enum  { MAC_MII_STATUS_BSY = 0x0001, MAC_MII_STATUS_SC = 0x0002, MAC_MII_STATUS_NV = 0x0004 }
 
enum  {
  MAC_CONFIG_REG_PE = 0x0001, MAC_CONFIG_REG_TF = 0x0002, MAC_CONFIG_REG_RF = 0x0004, MAC_CONFIG_REG_FD = 0x0008,
  MAC_CONFIG_REG_GM = 0x0010, MAC_CONFIG_REG_LB = 0x0020, MAC_CONFIG_REG_SR = 0x8000
}
 
enum  { MAC_HALF_DUPLEX_REG_ED = 0x10000, MAC_HALF_DUPLEX_REG_NB = 0x20000, MAC_HALF_DUPLEX_REG_BNB = 0x40000, MAC_HALF_DUPLEX_REG_ALT = 0x80000 }
 
enum  {
  IP_ADDR_INDEX_REG_MASK = 0x000f, IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000, IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001, IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
  IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003, IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004, IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005, IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
  IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007, IP_ADDR_INDEX_REG_6 = 0x0008, IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030, IP_ADDR_INDEX_REG_E = 0x0040
}
 
enum  {
  QL3032_PORT_CONTROL_DS = 0x0001, QL3032_PORT_CONTROL_HH = 0x0002, QL3032_PORT_CONTROL_EIv6 = 0x0004, QL3032_PORT_CONTROL_EIv4 = 0x0008,
  QL3032_PORT_CONTROL_ET = 0x0010, QL3032_PORT_CONTROL_EF = 0x0020, QL3032_PORT_CONTROL_DRM = 0x0040, QL3032_PORT_CONTROL_RLB = 0x0080,
  QL3032_PORT_CONTROL_RCB = 0x0100, QL3032_PORT_CONTROL_KIE = 0x0200
}
 
enum  {
  PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f, PROBE_MUX_ADDR_REG_SYSCLK = 0x0000, PROBE_MUX_ADDR_REG_PCICLK = 0x0040, PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
  PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0, PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00, PROBE_MUX_ADDR_REG_UP = 0x4000, PROBE_MUX_ADDR_REG_RE = 0x8000
}
 
enum  {
  STATISTICS_INDEX_REG_MASK = 0x01ff, STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000, STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001, STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
  STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003, STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004, STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005, STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
  STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007, STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008, STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009, STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
  STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b, STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c, STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d, STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
  STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f, STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010, STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011, STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
  STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013, STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014, STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015, STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
  STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017, STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018, STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019, STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
  STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b, STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c, STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d, STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
  STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f, STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020, STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021, STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
  STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023, STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024, STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025, STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
  STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027, STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028, STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029, STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
  STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031, STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032, STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033, STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
  STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035, STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036, STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037, STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
  STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f
}
 
enum  {
  PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001, PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002, PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004, PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
  PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010, PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020, PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040, PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
  PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100, PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200, PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400, PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
  PORT_FATAL_ERROR_STATUS_BLE = 0x00001000, PORT_FATAL_ERROR_STATUS_SPE = 0x00002000, PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000, PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
  PORT_FATAL_ERROR_STATUS_ICE = 0x00010000, PORT_FATAL_ERROR_STATUS_ILE = 0x00020000, PORT_FATAL_ERROR_STATUS_OPE = 0x00040000, PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
  PORT_FATAL_ERROR_STATUS_MA = 0x00100000, PORT_FATAL_ERROR_STATUS_SCE = 0x00200000, PORT_FATAL_ERROR_STATUS_RPE = 0x00400000, PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
  PORT_FATAL_ERROR_STATUS_OCE = 0x01000000
}
 
enum  {
  CONTROL_REG = 0, STATUS_REG = 1, PHY_STAT_LINK_UP = 0x0004, PHY_CTRL_LOOPBACK = 0x4000,
  PETBI_CONTROL_REG = 0x00, PETBI_CTRL_ALL_PARAMS = 0x7140, PETBI_CTRL_SOFT_RESET = 0x8000, PETBI_CTRL_AUTO_NEG = 0x1000,
  PETBI_CTRL_RESTART_NEG = 0x0200, PETBI_CTRL_FULL_DUPLEX = 0x0100, PETBI_CTRL_SPEED_1000 = 0x0040, PETBI_STATUS_REG = 0x01,
  PETBI_STAT_NEG_DONE = 0x0020, PETBI_STAT_LINK_UP = 0x0004, PETBI_NEG_ADVER = 0x04, PETBI_NEG_PAUSE = 0x0080,
  PETBI_NEG_PAUSE_MASK = 0x0180, PETBI_NEG_DUPLEX = 0x0020, PETBI_NEG_DUPLEX_MASK = 0x0060, PETBI_NEG_PARTNER = 0x05,
  PETBI_NEG_ERROR_MASK = 0x3000, PETBI_EXPANSION_REG = 0x06, PETBI_EXP_PAGE_RX = 0x0002, PHY_GIG_CONTROL = 9,
  PHY_GIG_ENABLE_MAN = 0x1000, PHY_GIG_SET_MASTER = 0x0800, PHY_GIG_ALL_PARAMS = 0x0300, PHY_GIG_ADV_1000F = 0x0200,
  PHY_GIG_ADV_1000H = 0x0100, PHY_NEG_ADVER = 4, PHY_NEG_ALL_PARAMS = 0x0fe0, PHY_NEG_ASY_PAUSE = 0x0800,
  PHY_NEG_SYM_PAUSE = 0x0400, PHY_NEG_ADV_SPEED = 0x01e0, PHY_NEG_ADV_100F = 0x0100, PHY_NEG_ADV_100H = 0x0080,
  PHY_NEG_ADV_10F = 0x0040, PHY_NEG_ADV_10H = 0x0020, PETBI_TBI_CTRL = 0x11, PETBI_TBI_RESET = 0x8000,
  PETBI_TBI_AUTO_SENSE = 0x0100, PETBI_TBI_SERDES_MODE = 0x0010, PETBI_TBI_SERDES_WRAP = 0x0002, AUX_CONTROL_STATUS = 0x1c,
  PHY_AUX_NEG_DONE = 0x8000, PHY_NEG_PARTNER = 5, PHY_AUX_DUPLEX_STAT = 0x0020, PHY_AUX_SPEED_STAT = 0x0018,
  PHY_AUX_NO_HW_STRAP = 0x0004, PHY_AUX_RESET_STICK = 0x0002, PHY_NEG_PAUSE = 0x0400, PHY_CTRL_SOFT_RESET = 0x8000,
  PHY_CTRL_AUTO_NEG = 0x1000, PHY_CTRL_RESTART_NEG = 0x0200
}
 
enum  {
  FM93C56A_START = 0x1, FM93C56A_READ = 0x2, FM93C56A_WEN = 0x0, FM93C56A_WRITE = 0x1,
  FM93C56A_WRITE_ALL = 0x0, FM93C56A_WDS = 0x0, FM93C56A_ERASE = 0x3, FM93C56A_ERASE_ALL = 0x0,
  FM93C56A_WEN_EXT = 0x3, FM93C56A_WRITE_ALL_EXT = 0x1, FM93C56A_WDS_EXT = 0x0, FM93C56A_ERASE_ALL_EXT = 0x2,
  FM93C56A_READ_DUMMY_BITS = 1, FM93C56A_READY = 0, FM93C56A_BUSY = 1, FM93C56A_CMD_BITS = 2,
  FM93C56A_SIZE_8 = 0x100, FM93C56A_SIZE_16 = 0x80, FM93C66A_SIZE_8 = 0x200, FM93C66A_SIZE_16 = 0x100,
  FM93C86A_SIZE_16 = 0x400, FM93C56A_NO_ADDR_BITS_16 = 8, FM93C56A_NO_ADDR_BITS_8 = 9, FM93C86A_NO_ADDR_BITS_16 = 10,
  FM93C56A_DATA_BITS_16 = 16, FM93C56A_DATA_BITS_8 = 8
}
 
enum  {
  AUBURN_EEPROM_DI = 0x8, AUBURN_EEPROM_DI_0 = 0x0, AUBURN_EEPROM_DI_1 = 0x8, AUBURN_EEPROM_DO = 0x4,
  AUBURN_EEPROM_DO_0 = 0x0, AUBURN_EEPROM_DO_1 = 0x4, AUBURN_EEPROM_CS = 0x2, AUBURN_EEPROM_CS_0 = 0x0,
  AUBURN_EEPROM_CS_1 = 0x2, AUBURN_EEPROM_CLK_RISE = 0x1, AUBURN_EEPROM_CLK_FALL = 0x0
}
 
enum  { EEPROM_SIZE = FM93C86A_SIZE_16, EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16, EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16 }
 
enum  link_state_t {
  LS_UNKNOWN = 0, LS_DOWN, LS_DEGRADE, LS_RECOVER,
  LS_UP
}
 
enum  {
  QL_RESET_DONE = 1, QL_RESET_ACTIVE = 2, QL_RESET_START = 3, QL_RESET_PER_SCSI = 4,
  QL_TX_TIMEOUT = 5, QL_LINK_MASTER = 6, QL_ADAPTER_UP = 7, QL_THREAD_UP = 8,
  QL_LINK_UP = 9, QL_ALLOC_REQ_RSP_Q_DONE = 10, QL_ALLOC_BUFQS_DONE = 11, QL_ALLOC_SMALL_BUF_DONE = 12,
  QL_LINK_OPTICAL = 13, QL_MSI_ENABLED = 14
}
 

Macro Definition Documentation

#define EEPROM_BOARDID_STR_SIZE   16

Definition at line 873 of file qla3xxx.h.

#define EEPROM_SERIAL_NUM_SIZE   16

Definition at line 874 of file qla3xxx.h.

#define ETHERNET_CRC_SIZE   4

Definition at line 194 of file qla3xxx.h.

#define FN0_MA_BITS_MASK   0x00

Definition at line 26 of file qla3xxx.h.

#define FN1_MA_BITS_MASK   0x80

Definition at line 27 of file qla3xxx.h.

#define IAL_CONT_ENTRY   0x00000002

Definition at line 962 of file qla3xxx.h.

#define IAL_FLAG_MASK   0x00000003

Definition at line 963 of file qla3xxx.h.

#define IAL_LAST_ENTRY   0x00000001

Definition at line 961 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_CE   0x02

Definition at line 169 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_I   0x20

Definition at line 156 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_ICE   0x01

Definition at line 168 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_IPE   0x20

Definition at line 173 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_NUC   0x04

Definition at line 170 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_O   0x40

Definition at line 155 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_R   0x10

Definition at line 157 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_TCP   0x10

Definition at line 172 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_UDP   0x08

Definition at line 171 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_3032_V   0x80

Definition at line 154 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_B   0x10

Definition at line 162 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_H0   0x20

Definition at line 161 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_H1   0x40

Definition at line 160 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_M   0x08

Definition at line 163 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_MA   0x07

Definition at line 164 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_R   0x01

Definition at line 175 of file qla3xxx.h.

#define IB_IP_IOCB_RSP_S   0x80

Definition at line 159 of file qla3xxx.h.

#define IB_MAC_IOCB_RSP_B   0x10

Definition at line 91 of file qla3xxx.h.

#define IB_MAC_IOCB_RSP_H0   0x20

Definition at line 90 of file qla3xxx.h.

#define IB_MAC_IOCB_RSP_H1   0x40

Definition at line 89 of file qla3xxx.h.

#define IB_MAC_IOCB_RSP_M   0x08

Definition at line 92 of file qla3xxx.h.

#define IB_MAC_IOCB_RSP_MA   0x07

Definition at line 93 of file qla3xxx.h.

#define IB_MAC_IOCB_RSP_S   0x80

Definition at line 88 of file qla3xxx.h.

#define IB_MAC_IOCB_RSP_V   0x80

Definition at line 86 of file qla3xxx.h.

#define IPSEC_CONFIG_PRESENT   0x0001

Definition at line 902 of file qla3xxx.h.

#define JUMBO_MTU_SIZE   9000

Definition at line 935 of file qla3xxx.h.

#define JUMBO_NUM_LBUFQ_ENTRIES   32

Definition at line 946 of file qla3xxx.h.

#define LS_64BITS (   x)    (u32)(0xffffffff & ((u64)x))

Definition at line 690 of file qla3xxx.h.

#define MAX_OAL_CNT   ((MAX_SKB_FRAGS-1)/4 + 1)

Definition at line 1017 of file qla3xxx.h.

#define MII_AGERE_ADDR_1   0x00001000

Definition at line 205 of file qla3xxx.h.

#define MII_AGERE_ADDR_2   0x00001100

Definition at line 206 of file qla3xxx.h.

#define MII_SCAN_REGISTER   0x00000001

Definition at line 196 of file qla3xxx.h.

#define MS_64BITS (   x)    (u32)(0xffffffff & (((u64)x)>>16>>16) )

Definition at line 691 of file qla3xxx.h.

#define NORMAL_MTU_SIZE   ETH_DATA_LEN

Definition at line 934 of file qla3xxx.h.

#define NUM_LBUFQ_ENTRIES   128

Definition at line 945 of file qla3xxx.h.

#define NUM_REQ_Q_ENTRIES   256 /* so that 64 * 64 = 4096 (1 page) */

Definition at line 939 of file qla3xxx.h.

#define NUM_RSP_Q_ENTRIES   256 /* so that 256 * 16 = 4096 (1 page) */

Definition at line 942 of file qla3xxx.h.

#define NUM_SBUFQ_ENTRIES   64

Definition at line 947 of file qla3xxx.h.

#define NUM_SMALL_BUFFERS   NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY

Definition at line 952 of file qla3xxx.h.

#define OAL_CONT_ENTRY   0x40000000 /* points to an OAL. (continuation) */

Definition at line 1024 of file qla3xxx.h.

#define OAL_LAST_ENTRY   0x80000000 /* Last valid buffer in list. */

Definition at line 1023 of file qla3xxx.h.

#define OB_3032MAC_IOCB_REQ_IC   0x04

Definition at line 38 of file qla3xxx.h.

#define OB_3032MAC_IOCB_REQ_TC   0x02

Definition at line 39 of file qla3xxx.h.

#define OB_3032MAC_IOCB_REQ_UC   0x01

Definition at line 40 of file qla3xxx.h.

#define OB_IP_IOCB_REQ_C   0x40000000

Definition at line 133 of file qla3xxx.h.

#define OB_IP_IOCB_REQ_D   0x002

Definition at line 108 of file qla3xxx.h.

#define OB_IP_IOCB_REQ_E   0x80000000

Definition at line 132 of file qla3xxx.h.

#define OB_IP_IOCB_REQ_H   0x008

Definition at line 106 of file qla3xxx.h.

#define OB_IP_IOCB_REQ_I   0x001

Definition at line 109 of file qla3xxx.h.

#define OB_IP_IOCB_REQ_L   0x20000000

Definition at line 134 of file qla3xxx.h.

#define OB_IP_IOCB_REQ_O   0x100

Definition at line 105 of file qla3xxx.h.

#define OB_IP_IOCB_REQ_R   0x10000000

Definition at line 135 of file qla3xxx.h.

#define OB_IP_IOCB_REQ_U   0x004

Definition at line 107 of file qla3xxx.h.

#define OB_MAC_IOCB_REQ_C   0x40000000 /* points to an OAL. (continuation) */

Definition at line 66 of file qla3xxx.h.

#define OB_MAC_IOCB_REQ_D   0x02

Definition at line 35 of file qla3xxx.h.

#define OB_MAC_IOCB_REQ_E   0x80000000 /* Last valid buffer in list. */

Definition at line 65 of file qla3xxx.h.

#define OB_MAC_IOCB_REQ_F   0x10

Definition at line 33 of file qla3xxx.h.

#define OB_MAC_IOCB_REQ_I   0x01

Definition at line 36 of file qla3xxx.h.

#define OB_MAC_IOCB_REQ_L   0x20000000 /* Auburn local address pointer. */

Definition at line 67 of file qla3xxx.h.

#define OB_MAC_IOCB_REQ_MA   0xe0

Definition at line 32 of file qla3xxx.h.

#define OB_MAC_IOCB_REQ_R   0x10000000 /* 32-bit address pointer. */

Definition at line 68 of file qla3xxx.h.

#define OB_MAC_IOCB_REQ_X   0x08

Definition at line 34 of file qla3xxx.h.

#define OB_MAC_IOCB_RSP_E   0x08

Definition at line 141 of file qla3xxx.h.

#define OB_MAC_IOCB_RSP_H   0x10

Definition at line 140 of file qla3xxx.h.

#define OB_MAC_IOCB_RSP_I   0x01

Definition at line 144 of file qla3xxx.h.

#define OB_MAC_IOCB_RSP_I   0x01

Definition at line 144 of file qla3xxx.h.

#define OB_MAC_IOCB_RSP_L   0x04

Definition at line 142 of file qla3xxx.h.

#define OB_MAC_IOCB_RSP_L   0x04

Definition at line 142 of file qla3xxx.h.

#define OB_MAC_IOCB_RSP_P   0x08

Definition at line 73 of file qla3xxx.h.

#define OB_MAC_IOCB_RSP_S   0x02

Definition at line 143 of file qla3xxx.h.

#define OB_MAC_IOCB_RSP_S   0x02

Definition at line 143 of file qla3xxx.h.

#define OPCODE_FUNC_ID_MASK   0x30

Definition at line 23 of file qla3xxx.h.

#define OPCODE_IB_3032_IP_IOCB   0x0A

Definition at line 21 of file qla3xxx.h.

#define OPCODE_IB_3032_MAC_IOCB   0x09

Definition at line 19 of file qla3xxx.h.

#define OPCODE_IB_IP_IOCB   0xFA

Definition at line 20 of file qla3xxx.h.

#define OPCODE_IB_MAC_IOCB   0xF9

Definition at line 18 of file qla3xxx.h.

#define OPCODE_OB_MAC_IOCB_FN0   0x01

Definition at line 15 of file qla3xxx.h.

#define OPCODE_OB_MAC_IOCB_FN2   0x21

Definition at line 16 of file qla3xxx.h.

#define OUTBOUND_MAC_IOCB   0x01 /* plus function bits */

Definition at line 24 of file qla3xxx.h.

#define PHY_ID_0_REG   2

Definition at line 198 of file qla3xxx.h.

#define PHY_ID_1_REG   3

Definition at line 199 of file qla3xxx.h.

#define PHY_MODEL_MASK   0x03f0

Definition at line 202 of file qla3xxx.h.

#define PHY_OUI_1_MASK   0xfc00

Definition at line 201 of file qla3xxx.h.

#define PORT0_PHY_ADDRESS   0x1e00

Definition at line 191 of file qla3xxx.h.

#define PORT1_PHY_ADDRESS   0x1f00

Definition at line 192 of file qla3xxx.h.

#define PORT_CONFIG_1000MB_SPEED   0x0400

Definition at line 829 of file qla3xxx.h.

#define PORT_CONFIG_100MB_SPEED   0x0200

Definition at line 830 of file qla3xxx.h.

#define PORT_CONFIG_10MB_SPEED   0x0100

Definition at line 831 of file qla3xxx.h.

#define PORT_CONFIG_AUTO_NEG_ENABLED   0x8000

Definition at line 825 of file qla3xxx.h.

#define PORT_CONFIG_DEFAULT   0xf700

Definition at line 824 of file qla3xxx.h.

#define PORT_CONFIG_FULL_DUPLEX_ENABLED   0x2000

Definition at line 827 of file qla3xxx.h.

#define PORT_CONFIG_HALF_DUPLEX_ENABLED   0x1000

Definition at line 828 of file qla3xxx.h.

#define PORT_CONFIG_LINK_SPEED_MASK   0x0F00

Definition at line 832 of file qla3xxx.h.

#define PORT_CONFIG_SYM_PAUSE_ENABLED   0x4000

Definition at line 826 of file qla3xxx.h.

#define QL3022_DEVICE_ID   0x3022

Definition at line 930 of file qla3xxx.h.

#define QL3032_DEVICE_ID   0x3032

Definition at line 931 of file qla3xxx.h.

#define QL3XXX_VENDOR_ID   0x1077

Definition at line 929 of file qla3xxx.h.

#define QL_ADDR_ELE_PER_BUFQ_ENTRY   (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))

Definition at line 949 of file qla3xxx.h.

#define QL_BUF_TYPE_IPIOCB   0x02

Definition at line 1046 of file qla3xxx.h.

#define QL_BUF_TYPE_MACIOCB   0x01

Definition at line 1045 of file qla3xxx.h.

#define QL_BUF_TYPE_TCPIOCB   0x03

Definition at line 1047 of file qla3xxx.h.

#define QL_DO_RESET   1

Definition at line 988 of file qla3xxx.h.

#define QL_HEADER_SPACE   32 /* make header space at top of skb. */

Definition at line 954 of file qla3xxx.h.

#define QL_NO_RESET   0

Definition at line 987 of file qla3xxx.h.

#define QL_SMALL_BUFFER_SIZE   32

Definition at line 948 of file qla3xxx.h.

#define VLAN_ID_LEN   2

Definition at line 936 of file qla3xxx.h.

Enumeration Type Documentation

anonymous enum
Enumerator:
ISP_CONTROL_NP_MASK 
ISP_CONTROL_NP_PCSR 
ISP_CONTROL_NP_HMCR 
ISP_CONTROL_NP_LRAMCR 
ISP_CONTROL_NP_PSR 
ISP_CONTROL_RI 
ISP_CONTROL_CI 
ISP_CONTROL_PI 
ISP_CONTROL_IN 
ISP_CONTROL_BE 
ISP_CONTROL_FN_MASK 
ISP_CONTROL_FN0_NET 
ISP_CONTROL_FN0_SCSI 
ISP_CONTROL_FN1_NET 
ISP_CONTROL_FN1_SCSI 
ISP_CONTROL_LINK_DN_0 
ISP_CONTROL_LINK_DN_1 
ISP_CONTROL_FSR 
ISP_CONTROL_FE 
ISP_CONTROL_SR 

Definition at line 209 of file qla3xxx.h.

anonymous enum
Enumerator:
ISP_IMR_ENABLE_INT 
ISP_IMR_DISABLE_RESET_INT 
ISP_IMR_DISABLE_CMPL_INT 
ISP_IMR_DISABLE_PROC_INT 

Definition at line 233 of file qla3xxx.h.

anonymous enum
Enumerator:
ISP_SERIAL_PORT_IF_CLK 
ISP_SERIAL_PORT_IF_CS 
ISP_SERIAL_PORT_IF_D0 
ISP_SERIAL_PORT_IF_DI 
ISP_NVRAM_MASK 
ISP_SERIAL_PORT_IF_WE 
ISP_SERIAL_PORT_IF_NVR_MASK 
ISP_SERIAL_PORT_IF_SCI 
ISP_SERIAL_PORT_IF_SC0 
ISP_SERIAL_PORT_IF_SCE 
ISP_SERIAL_PORT_IF_SDI 
ISP_SERIAL_PORT_IF_SDO 
ISP_SERIAL_PORT_IF_SDE 
ISP_SERIAL_PORT_IF_I2C_MASK 

Definition at line 241 of file qla3xxx.h.

anonymous enum
Enumerator:
QL_RESOURCE_MASK_BASE_CODE 
QL_RESOURCE_BITS_BASE_CODE 
QL_DRVR_SEM_BITS 
QL_DDR_RAM_SEM_BITS 
QL_PHY_GIO_SEM_BITS 
QL_NVRAM_SEM_BITS 
QL_FLASH_SEM_BITS 
QL_DRVR_SEM_MASK 
QL_DDR_RAM_SEM_MASK 
QL_PHY_GIO_SEM_MASK 
QL_NVRAM_SEM_MASK 
QL_FLASH_SEM_MASK 

Definition at line 259 of file qla3xxx.h.

anonymous enum
Enumerator:
EXT_HW_CONFIG_SP_MASK 
EXT_HW_CONFIG_SP_NONE 
EXT_HW_CONFIG_SP_BYTE_PARITY 
EXT_HW_CONFIG_SP_ECC 
EXT_HW_CONFIG_SP_ECCx 
EXT_HW_CONFIG_SIZE_MASK 
EXT_HW_CONFIG_SIZE_128M 
EXT_HW_CONFIG_SIZE_256M 
EXT_HW_CONFIG_SIZE_512M 
EXT_HW_CONFIG_SIZE_INVALID 
EXT_HW_CONFIG_PD 
EXT_HW_CONFIG_FW 
EXT_HW_CONFIG_US 
EXT_HW_CONFIG_DCS_MASK 
EXT_HW_CONFIG_DCS_9MA 
EXT_HW_CONFIG_DCS_15MA 
EXT_HW_CONFIG_DCS_18MA 
EXT_HW_CONFIG_DCS_24MA 
EXT_HW_CONFIG_DDS_MASK 
EXT_HW_CONFIG_DDS_9MA 
EXT_HW_CONFIG_DDS_15MA 
EXT_HW_CONFIG_DDS_18MA 
EXT_HW_CONFIG_DDS_24MA 

Definition at line 304 of file qla3xxx.h.

anonymous enum
Enumerator:
INTERNAL_CHIP_DM 
INTERNAL_CHIP_SD 
INTERNAL_CHIP_RAP_MASK 
INTERNAL_CHIP_RAP_RR 
INTERNAL_CHIP_RAP_NRM 
INTERNAL_CHIP_RAP_ERM 
INTERNAL_CHIP_RAP_ERMx 
INTERNAL_CHIP_WE 
INTERNAL_CHIP_EF 
INTERNAL_CHIP_FR 
INTERNAL_CHIP_FW 
INTERNAL_CHIP_FI 
INTERNAL_CHIP_FT 

Definition at line 331 of file qla3xxx.h.

anonymous enum
Enumerator:
PORT_CONTROL_DS 
PORT_CONTROL_HH 
PORT_CONTROL_EI 
PORT_CONTROL_ET 
PORT_CONTROL_EF 
PORT_CONTROL_DRM 
PORT_CONTROL_RLB 
PORT_CONTROL_RCB 
PORT_CONTROL_MAC 
PORT_CONTROL_IPV 
PORT_CONTROL_IFP 
PORT_CONTROL_ITP 
PORT_CONTROL_FI 
PORT_CONTROL_DFP 
PORT_CONTROL_OI 
PORT_CONTROL_CC 

Definition at line 348 of file qla3xxx.h.

anonymous enum
Enumerator:
PORT_STATUS_SM0 
PORT_STATUS_SM1 
PORT_STATUS_X 
PORT_STATUS_DL 
PORT_STATUS_IC 
PORT_STATUS_MRC 
PORT_STATUS_NL 
PORT_STATUS_REV_ID_MASK 
PORT_STATUS_REV_ID_1 
PORT_STATUS_REV_ID_2 
PORT_STATUS_REV_ID_3 
PORT_STATUS_64 
PORT_STATUS_UP0 
PORT_STATUS_AC0 
PORT_STATUS_AE0 
PORT_STATUS_UP1 
PORT_STATUS_AC1 
PORT_STATUS_AE1 
PORT_STATUS_F0_ENABLED 
PORT_STATUS_F1_ENABLED 
PORT_STATUS_F2_ENABLED 
PORT_STATUS_F3_ENABLED 

Definition at line 368 of file qla3xxx.h.

anonymous enum
Enumerator:
MAC_ADDR_INDIRECT_PTR_REG_RP_MASK 
MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR 
MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR 
MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR 
MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR 
MAC_ADDR_INDIRECT_PTR_REG_PR 
MAC_ADDR_INDIRECT_PTR_REG_SS 
MAC_ADDR_INDIRECT_PTR_REG_SE 
MAC_ADDR_INDIRECT_PTR_REG_SP 
MAC_ADDR_INDIRECT_PTR_REG_PE 

Definition at line 394 of file qla3xxx.h.

anonymous enum
Enumerator:
MAC_MII_CONTROL_RC 
MAC_MII_CONTROL_SC 
MAC_MII_CONTROL_AS 
MAC_MII_CONTROL_NP 
MAC_MII_CONTROL_CLK_SEL_MASK 
MAC_MII_CONTROL_CLK_SEL_DIV2 
MAC_MII_CONTROL_CLK_SEL_DIV4 
MAC_MII_CONTROL_CLK_SEL_DIV6 
MAC_MII_CONTROL_CLK_SEL_DIV8 
MAC_MII_CONTROL_CLK_SEL_DIV10 
MAC_MII_CONTROL_CLK_SEL_DIV14 
MAC_MII_CONTROL_CLK_SEL_DIV20 
MAC_MII_CONTROL_CLK_SEL_DIV28 
MAC_MII_CONTROL_RM 

Definition at line 408 of file qla3xxx.h.

anonymous enum
Enumerator:
MAC_MII_STATUS_BSY 
MAC_MII_STATUS_SC 
MAC_MII_STATUS_NV 

Definition at line 426 of file qla3xxx.h.

anonymous enum
Enumerator:
MAC_CONFIG_REG_PE 
MAC_CONFIG_REG_TF 
MAC_CONFIG_REG_RF 
MAC_CONFIG_REG_FD 
MAC_CONFIG_REG_GM 
MAC_CONFIG_REG_LB 
MAC_CONFIG_REG_SR 

Definition at line 432 of file qla3xxx.h.

anonymous enum
Enumerator:
MAC_HALF_DUPLEX_REG_ED 
MAC_HALF_DUPLEX_REG_NB 
MAC_HALF_DUPLEX_REG_BNB 
MAC_HALF_DUPLEX_REG_ALT 

Definition at line 442 of file qla3xxx.h.

anonymous enum
Enumerator:
IP_ADDR_INDEX_REG_MASK 
IP_ADDR_INDEX_REG_FUNC_0_PRI 
IP_ADDR_INDEX_REG_FUNC_0_SEC 
IP_ADDR_INDEX_REG_FUNC_1_PRI 
IP_ADDR_INDEX_REG_FUNC_1_SEC 
IP_ADDR_INDEX_REG_FUNC_2_PRI 
IP_ADDR_INDEX_REG_FUNC_2_SEC 
IP_ADDR_INDEX_REG_FUNC_3_PRI 
IP_ADDR_INDEX_REG_FUNC_3_SEC 
IP_ADDR_INDEX_REG_6 
IP_ADDR_INDEX_REG_OFFSET_MASK 
IP_ADDR_INDEX_REG_E 

Definition at line 449 of file qla3xxx.h.

anonymous enum
Enumerator:
QL3032_PORT_CONTROL_DS 
QL3032_PORT_CONTROL_HH 
QL3032_PORT_CONTROL_EIv6 
QL3032_PORT_CONTROL_EIv4 
QL3032_PORT_CONTROL_ET 
QL3032_PORT_CONTROL_EF 
QL3032_PORT_CONTROL_DRM 
QL3032_PORT_CONTROL_RLB 
QL3032_PORT_CONTROL_RCB 
QL3032_PORT_CONTROL_KIE 

Definition at line 463 of file qla3xxx.h.

anonymous enum
Enumerator:
PROBE_MUX_ADDR_REG_MUX_SEL_MASK 
PROBE_MUX_ADDR_REG_SYSCLK 
PROBE_MUX_ADDR_REG_PCICLK 
PROBE_MUX_ADDR_REG_NRXCLK 
PROBE_MUX_ADDR_REG_CPUCLK 
PROBE_MUX_ADDR_REG_MODULE_SEL_MASK 
PROBE_MUX_ADDR_REG_UP 
PROBE_MUX_ADDR_REG_RE 

Definition at line 476 of file qla3xxx.h.

anonymous enum
Enumerator:
STATISTICS_INDEX_REG_MASK 
STATISTICS_INDEX_REG_MAC0_TX_FRAME 
STATISTICS_INDEX_REG_MAC0_TX_BYTES 
STATISTICS_INDEX_REG_MAC0_TX_STAT1 
STATISTICS_INDEX_REG_MAC0_TX_STAT2 
STATISTICS_INDEX_REG_MAC0_TX_STAT3 
STATISTICS_INDEX_REG_MAC0_TX_STAT4 
STATISTICS_INDEX_REG_MAC0_TX_STAT5 
STATISTICS_INDEX_REG_MAC0_RX_FRAME 
STATISTICS_INDEX_REG_MAC0_RX_BYTES 
STATISTICS_INDEX_REG_MAC0_RX_STAT1 
STATISTICS_INDEX_REG_MAC0_RX_STAT2 
STATISTICS_INDEX_REG_MAC0_RX_STAT3 
STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC 
STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC 
STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN 
STATISTICS_INDEX_REG_MAC0_RX_STAT4 
STATISTICS_INDEX_REG_MAC1_TX_FRAME 
STATISTICS_INDEX_REG_MAC1_TX_BYTES 
STATISTICS_INDEX_REG_MAC1_TX_STAT1 
STATISTICS_INDEX_REG_MAC1_TX_STAT2 
STATISTICS_INDEX_REG_MAC1_TX_STAT3 
STATISTICS_INDEX_REG_MAC1_TX_STAT4 
STATISTICS_INDEX_REG_MAC1_TX_STAT5 
STATISTICS_INDEX_REG_MAC1_RX_FRAME 
STATISTICS_INDEX_REG_MAC1_RX_BYTES 
STATISTICS_INDEX_REG_MAC1_RX_STAT1 
STATISTICS_INDEX_REG_MAC1_RX_STAT2 
STATISTICS_INDEX_REG_MAC1_RX_STAT3 
STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC 
STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC 
STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN 
STATISTICS_INDEX_REG_MAC1_RX_STAT4 
STATISTICS_INDEX_REG_IP_TX_PKTS 
STATISTICS_INDEX_REG_IP_TX_BYTES 
STATISTICS_INDEX_REG_IP_TX_FRAG 
STATISTICS_INDEX_REG_IP_RX_PKTS 
STATISTICS_INDEX_REG_IP_RX_BYTES 
STATISTICS_INDEX_REG_IP_RX_FRAG 
STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY 
STATISTICS_INDEX_REG_IP_V6_RX_PKTS 
STATISTICS_INDEX_REG_IP_RX_PKTERR 
STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR 
STATISTICS_INDEX_REG_TCP_TX_SEG 
STATISTICS_INDEX_REG_TCP_TX_BYTES 
STATISTICS_INDEX_REG_TCP_RX_SEG 
STATISTICS_INDEX_REG_TCP_RX_BYTES 
STATISTICS_INDEX_REG_TCP_TIMER_EXP 
STATISTICS_INDEX_REG_TCP_RX_ACK 
STATISTICS_INDEX_REG_TCP_TX_ACK 
STATISTICS_INDEX_REG_TCP_RX_ERR 
STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE 
STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR 

Definition at line 487 of file qla3xxx.h.

anonymous enum
Enumerator:
PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 
PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 
PORT_FATAL_ERROR_STATUS_OFB_WE 
PORT_FATAL_ERROR_STATUS_IFB_RE 
PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 
PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 
PORT_FATAL_ERROR_STATUS_ODE_RE 
PORT_FATAL_ERROR_STATUS_ODE_WE 
PORT_FATAL_ERROR_STATUS_IDE_RE 
PORT_FATAL_ERROR_STATUS_IDE_WE 
PORT_FATAL_ERROR_STATUS_SDE_RE 
PORT_FATAL_ERROR_STATUS_SDE_WE 
PORT_FATAL_ERROR_STATUS_BLE 
PORT_FATAL_ERROR_STATUS_SPE 
PORT_FATAL_ERROR_STATUS_EP0 
PORT_FATAL_ERROR_STATUS_EP1 
PORT_FATAL_ERROR_STATUS_ICE 
PORT_FATAL_ERROR_STATUS_ILE 
PORT_FATAL_ERROR_STATUS_OPE 
PORT_FATAL_ERROR_STATUS_TA 
PORT_FATAL_ERROR_STATUS_MA 
PORT_FATAL_ERROR_STATUS_SCE 
PORT_FATAL_ERROR_STATUS_RPE 
PORT_FATAL_ERROR_STATUS_MPE 
PORT_FATAL_ERROR_STATUS_OCE 

Definition at line 543 of file qla3xxx.h.

anonymous enum
Enumerator:
CONTROL_REG 
STATUS_REG 
PHY_STAT_LINK_UP 
PHY_CTRL_LOOPBACK 
PETBI_CONTROL_REG 
PETBI_CTRL_ALL_PARAMS 
PETBI_CTRL_SOFT_RESET 
PETBI_CTRL_AUTO_NEG 
PETBI_CTRL_RESTART_NEG 
PETBI_CTRL_FULL_DUPLEX 
PETBI_CTRL_SPEED_1000 
PETBI_STATUS_REG 
PETBI_STAT_NEG_DONE 
PETBI_STAT_LINK_UP 
PETBI_NEG_ADVER 
PETBI_NEG_PAUSE 
PETBI_NEG_PAUSE_MASK 
PETBI_NEG_DUPLEX 
PETBI_NEG_DUPLEX_MASK 
PETBI_NEG_PARTNER 
PETBI_NEG_ERROR_MASK 
PETBI_EXPANSION_REG 
PETBI_EXP_PAGE_RX 
PHY_GIG_CONTROL 
PHY_GIG_ENABLE_MAN 
PHY_GIG_SET_MASTER 
PHY_GIG_ALL_PARAMS 
PHY_GIG_ADV_1000F 
PHY_GIG_ADV_1000H 
PHY_NEG_ADVER 
PHY_NEG_ALL_PARAMS 
PHY_NEG_ASY_PAUSE 
PHY_NEG_SYM_PAUSE 
PHY_NEG_ADV_SPEED 
PHY_NEG_ADV_100F 
PHY_NEG_ADV_100H 
PHY_NEG_ADV_10F 
PHY_NEG_ADV_10H 
PETBI_TBI_CTRL 
PETBI_TBI_RESET 
PETBI_TBI_AUTO_SENSE 
PETBI_TBI_SERDES_MODE 
PETBI_TBI_SERDES_WRAP 
AUX_CONTROL_STATUS 
PHY_AUX_NEG_DONE 
PHY_NEG_PARTNER 
PHY_AUX_DUPLEX_STAT 
PHY_AUX_SPEED_STAT 
PHY_AUX_NO_HW_STRAP 
PHY_AUX_RESET_STICK 
PHY_NEG_PAUSE 
PHY_CTRL_SOFT_RESET 
PHY_CTRL_AUTO_NEG 
PHY_CTRL_RESTART_NEG 

Definition at line 697 of file qla3xxx.h.

anonymous enum
Enumerator:
FM93C56A_START 
FM93C56A_READ 
FM93C56A_WEN 
FM93C56A_WRITE 
FM93C56A_WRITE_ALL 
FM93C56A_WDS 
FM93C56A_ERASE 
FM93C56A_ERASE_ALL 
FM93C56A_WEN_EXT 
FM93C56A_WRITE_ALL_EXT 
FM93C56A_WDS_EXT 
FM93C56A_ERASE_ALL_EXT 
FM93C56A_READ_DUMMY_BITS 
FM93C56A_READY 
FM93C56A_BUSY 
FM93C56A_CMD_BITS 
FM93C56A_SIZE_8 
FM93C56A_SIZE_16 
FM93C66A_SIZE_8 
FM93C66A_SIZE_16 
FM93C86A_SIZE_16 
FM93C56A_NO_ADDR_BITS_16 
FM93C56A_NO_ADDR_BITS_8 
FM93C86A_NO_ADDR_BITS_16 
FM93C56A_DATA_BITS_16 
FM93C56A_DATA_BITS_8 

Definition at line 762 of file qla3xxx.h.

anonymous enum
Enumerator:
AUBURN_EEPROM_DI 
AUBURN_EEPROM_DI_0 
AUBURN_EEPROM_DI_1 
AUBURN_EEPROM_DO 
AUBURN_EEPROM_DO_0 
AUBURN_EEPROM_DO_1 
AUBURN_EEPROM_CS 
AUBURN_EEPROM_CS_0 
AUBURN_EEPROM_CS_1 
AUBURN_EEPROM_CLK_RISE 
AUBURN_EEPROM_CLK_FALL 

Definition at line 797 of file qla3xxx.h.

anonymous enum
Enumerator:
EEPROM_SIZE 
EEPROM_NO_ADDR_BITS 
EEPROM_NO_DATA_BITS 

Definition at line 811 of file qla3xxx.h.

anonymous enum
Enumerator:
QL_RESET_DONE 
QL_RESET_ACTIVE 
QL_RESET_START 
QL_RESET_PER_SCSI 
QL_TX_TIMEOUT 
QL_LINK_MASTER 
QL_ADAPTER_UP 
QL_THREAD_UP 
QL_LINK_UP 
QL_ALLOC_REQ_RSP_Q_DONE 
QL_ALLOC_BUFQS_DONE 
QL_ALLOC_SMALL_BUF_DONE 
QL_LINK_OPTICAL 
QL_MSI_ENABLED 

Definition at line 1050 of file qla3xxx.h.

Enumerator:
LS_UNKNOWN 
LS_DOWN 
LS_DEGRADE 
LS_RECOVER 
LS_UP 

Definition at line 990 of file qla3xxx.h.