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qla_nx.h
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1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c) 2003-2012 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 #ifndef __QLA_NX_H
8 #define __QLA_NX_H
9 
10 /*
11  * Following are the states of the Phantom. Phantom will set them and
12  * Host will read to check if the fields are correct.
13 */
14 #define PHAN_INITIALIZE_FAILED 0xffff
15 #define PHAN_INITIALIZE_COMPLETE 0xff01
16 
17 /* Host writes the following to notify that it has done the init-handshake */
18 #define PHAN_INITIALIZE_ACK 0xf00f
19 #define PHAN_PEG_RCV_INITIALIZED 0xff01
20 
21 /*CRB_RELATED*/
22 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
23 #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))
24 
25 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
26 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
27 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
28 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
29 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
30 #define QLA82XX_DMA_SHIFT_VALUE 0x55555555
31 
32 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
33 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
34 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
35 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
36 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
37 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
38 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
39 
40 /* Hub 0 */
41 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
42 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
43 
44 /* Hub 1 */
45 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
46 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
47 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
48 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
49 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
50 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
51 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
52 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
53 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
54 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
55 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
56 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
57 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
58 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
59 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
60 
61 /* Hub 2 */
62 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
63 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
64 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
65 
66 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
67 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
68 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
69 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
70 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
71 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
72 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
73 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
74 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
75 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
76 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
77 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
78 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
79 
80 /* Hub 3 */
81 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
82 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
83 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
84 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
85 
86 /* Hub 4 */
87 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
88 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
89 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
90 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
91 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
92 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
93 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
94 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
95 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
96 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
97 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
98 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
99 
100 /* Hub 5 */
101 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
102 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
103 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
104 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
105 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
106 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
107 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
108 
109 /* Hub 6 */
110 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
111 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
112 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
113 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
114 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
115 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
116 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
117 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
118 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
119 
120 /* This field defines PCI/X adr [25:20] of agents on the CRB */
121 /* */
122 #define QLA82XX_HW_PX_MAP_CRB_PH 0
123 #define QLA82XX_HW_PX_MAP_CRB_PS 1
124 #define QLA82XX_HW_PX_MAP_CRB_MN 2
125 #define QLA82XX_HW_PX_MAP_CRB_MS 3
126 #define QLA82XX_HW_PX_MAP_CRB_SRE 5
127 #define QLA82XX_HW_PX_MAP_CRB_NIU 6
128 #define QLA82XX_HW_PX_MAP_CRB_QMN 7
129 #define QLA82XX_HW_PX_MAP_CRB_SQN0 8
130 #define QLA82XX_HW_PX_MAP_CRB_SQN1 9
131 #define QLA82XX_HW_PX_MAP_CRB_SQN2 10
132 #define QLA82XX_HW_PX_MAP_CRB_SQN3 11
133 #define QLA82XX_HW_PX_MAP_CRB_QMS 12
134 #define QLA82XX_HW_PX_MAP_CRB_SQS0 13
135 #define QLA82XX_HW_PX_MAP_CRB_SQS1 14
136 #define QLA82XX_HW_PX_MAP_CRB_SQS2 15
137 #define QLA82XX_HW_PX_MAP_CRB_SQS3 16
138 #define QLA82XX_HW_PX_MAP_CRB_PGN0 17
139 #define QLA82XX_HW_PX_MAP_CRB_PGN1 18
140 #define QLA82XX_HW_PX_MAP_CRB_PGN2 19
141 #define QLA82XX_HW_PX_MAP_CRB_PGN3 20
142 #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2
143 #define QLA82XX_HW_PX_MAP_CRB_PGND 21
144 #define QLA82XX_HW_PX_MAP_CRB_PGNI 22
145 #define QLA82XX_HW_PX_MAP_CRB_PGS0 23
146 #define QLA82XX_HW_PX_MAP_CRB_PGS1 24
147 #define QLA82XX_HW_PX_MAP_CRB_PGS2 25
148 #define QLA82XX_HW_PX_MAP_CRB_PGS3 26
149 #define QLA82XX_HW_PX_MAP_CRB_PGSD 27
150 #define QLA82XX_HW_PX_MAP_CRB_PGSI 28
151 #define QLA82XX_HW_PX_MAP_CRB_SN 29
152 #define QLA82XX_HW_PX_MAP_CRB_EG 31
153 #define QLA82XX_HW_PX_MAP_CRB_PH2 32
154 #define QLA82XX_HW_PX_MAP_CRB_PS2 33
155 #define QLA82XX_HW_PX_MAP_CRB_CAM 34
156 #define QLA82XX_HW_PX_MAP_CRB_CAS0 35
157 #define QLA82XX_HW_PX_MAP_CRB_CAS1 36
158 #define QLA82XX_HW_PX_MAP_CRB_CAS2 37
159 #define QLA82XX_HW_PX_MAP_CRB_C2C0 38
160 #define QLA82XX_HW_PX_MAP_CRB_C2C1 39
161 #define QLA82XX_HW_PX_MAP_CRB_TIMR 40
162 #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42
163 #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43
164 #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44
165 #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45
166 #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46
167 #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47
168 #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48
169 #define QLA82XX_HW_PX_MAP_CRB_XDMA 49
170 #define QLA82XX_HW_PX_MAP_CRB_I2Q 50
171 #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51
172 #define QLA82XX_HW_PX_MAP_CRB_CAS3 52
173 #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53
174 #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54
175 #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55
176 #define QLA82XX_HW_PX_MAP_CRB_OCM0 56
177 #define QLA82XX_HW_PX_MAP_CRB_OCM1 57
178 #define QLA82XX_HW_PX_MAP_CRB_SMB 58
179 #define QLA82XX_HW_PX_MAP_CRB_I2C0 59
180 #define QLA82XX_HW_PX_MAP_CRB_I2C1 60
181 #define QLA82XX_HW_PX_MAP_CRB_LPC 61
182 #define QLA82XX_HW_PX_MAP_CRB_PGNC 62
183 #define QLA82XX_HW_PX_MAP_CRB_PGR0 63
184 #define QLA82XX_HW_PX_MAP_CRB_PGR1 4
185 #define QLA82XX_HW_PX_MAP_CRB_PGR2 30
186 #define QLA82XX_HW_PX_MAP_CRB_PGR3 41
187 
188 /* This field defines CRB adr [31:20] of the agents */
189 /* */
190 
191 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
192  QLA82XX_HW_MN_CRB_AGT_ADR)
193 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
194  QLA82XX_HW_PH_CRB_AGT_ADR)
195 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
196  QLA82XX_HW_MS_CRB_AGT_ADR)
197 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
198  QLA82XX_HW_PS_CRB_AGT_ADR)
199 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
200  QLA82XX_HW_SS_CRB_AGT_ADR)
201 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
202  QLA82XX_HW_RPMX3_CRB_AGT_ADR)
203 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
204  QLA82XX_HW_QMS_CRB_AGT_ADR)
205 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
206  QLA82XX_HW_SQGS0_CRB_AGT_ADR)
207 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
208  QLA82XX_HW_SQGS1_CRB_AGT_ADR)
209 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
210  QLA82XX_HW_SQGS2_CRB_AGT_ADR)
211 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
212  QLA82XX_HW_SQGS3_CRB_AGT_ADR)
213 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
214  QLA82XX_HW_C2C0_CRB_AGT_ADR)
215 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
216  QLA82XX_HW_C2C1_CRB_AGT_ADR)
217 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
218  QLA82XX_HW_RPMX2_CRB_AGT_ADR)
219 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
220  QLA82XX_HW_RPMX4_CRB_AGT_ADR)
221 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
222  QLA82XX_HW_RPMX7_CRB_AGT_ADR)
223 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
224  QLA82XX_HW_RPMX9_CRB_AGT_ADR)
225 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
226  QLA82XX_HW_SMB_CRB_AGT_ADR)
227 #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
228  QLA82XX_HW_NIU_CRB_AGT_ADR)
229 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
230  QLA82XX_HW_I2C0_CRB_AGT_ADR)
231 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
232  QLA82XX_HW_I2C1_CRB_AGT_ADR)
233 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
234  QLA82XX_HW_SRE_CRB_AGT_ADR)
235 #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
236  QLA82XX_HW_EG_CRB_AGT_ADR)
237 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
238  QLA82XX_HW_RPMX0_CRB_AGT_ADR)
239 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
240  QLA82XX_HW_QM_CRB_AGT_ADR)
241 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
242  QLA82XX_HW_SQG0_CRB_AGT_ADR)
243 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
244  QLA82XX_HW_SQG1_CRB_AGT_ADR)
245 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
246  QLA82XX_HW_SQG2_CRB_AGT_ADR)
247 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
248  QLA82XX_HW_SQG3_CRB_AGT_ADR)
249 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
250  QLA82XX_HW_RPMX1_CRB_AGT_ADR)
251 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
252  QLA82XX_HW_RPMX5_CRB_AGT_ADR)
253 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
254  QLA82XX_HW_RPMX6_CRB_AGT_ADR)
255 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
256  QLA82XX_HW_RPMX8_CRB_AGT_ADR)
257 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
258  QLA82XX_HW_CAS0_CRB_AGT_ADR)
259 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
260  QLA82XX_HW_CAS1_CRB_AGT_ADR)
261 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
262  QLA82XX_HW_CAS2_CRB_AGT_ADR)
263 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
264  QLA82XX_HW_CAS3_CRB_AGT_ADR)
265 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
266  QLA82XX_HW_PEGNI_CRB_AGT_ADR)
267 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
268  QLA82XX_HW_PEGND_CRB_AGT_ADR)
269 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
270  QLA82XX_HW_PEGN0_CRB_AGT_ADR)
271 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
272  QLA82XX_HW_PEGN1_CRB_AGT_ADR)
273 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
274  QLA82XX_HW_PEGN2_CRB_AGT_ADR)
275 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
276  QLA82XX_HW_PEGN3_CRB_AGT_ADR)
277 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
278  QLA82XX_HW_PEGN4_CRB_AGT_ADR)
279 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
280  QLA82XX_HW_PEGNC_CRB_AGT_ADR)
281 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
282  QLA82XX_HW_PEGR0_CRB_AGT_ADR)
283 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
284  QLA82XX_HW_PEGR1_CRB_AGT_ADR)
285 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
286  QLA82XX_HW_PEGR2_CRB_AGT_ADR)
287 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
288  QLA82XX_HW_PEGR3_CRB_AGT_ADR)
289 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
290  QLA82XX_HW_PEGSI_CRB_AGT_ADR)
291 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
292  QLA82XX_HW_PEGSD_CRB_AGT_ADR)
293 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
294  QLA82XX_HW_PEGS0_CRB_AGT_ADR)
295 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
296  QLA82XX_HW_PEGS1_CRB_AGT_ADR)
297 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
298  QLA82XX_HW_PEGS2_CRB_AGT_ADR)
299 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
300  QLA82XX_HW_PEGS3_CRB_AGT_ADR)
301 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
302  QLA82XX_HW_PEGSC_CRB_AGT_ADR)
303 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
304  QLA82XX_HW_NCM_CRB_AGT_ADR)
305 #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
306  QLA82XX_HW_TMR_CRB_AGT_ADR)
307 #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
308  QLA82XX_HW_XDMA_CRB_AGT_ADR)
309 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
310  QLA82XX_HW_SN_CRB_AGT_ADR)
311 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
312  QLA82XX_HW_I2Q_CRB_AGT_ADR)
313 #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
314  QLA82XX_HW_ROMUSB_CRB_AGT_ADR)
315 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
316  QLA82XX_HW_OCM0_CRB_AGT_ADR)
317 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
318  QLA82XX_HW_OCM1_CRB_AGT_ADR)
319 #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
320  QLA82XX_HW_LPC_CRB_AGT_ADR)
321 
322 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
323 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
324 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
325 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
326 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
327 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
328 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
329 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
330 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
331 
332 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
333 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
334 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
335 
336 /* Lock IDs for ROM lock */
337 #define ROM_LOCK_DRIVER 0x0d417340
338 
339 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
340 #define QLA82XX_PCI_CRB_WINDOW(A) \
341  (QLA82XX_PCI_CRBSPACE + (A)*QLA82XX_PCI_CRB_WINDOWSIZE)
342 #define QLA82XX_CRB_C2C_0 \
343  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)
344 #define QLA82XX_CRB_C2C_1 \
345  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)
346 #define QLA82XX_CRB_C2C_2 \
347  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)
348 #define QLA82XX_CRB_CAM \
349  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)
350 #define QLA82XX_CRB_CASPER \
351  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)
352 #define QLA82XX_CRB_CASPER_0 \
353  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)
354 #define QLA82XX_CRB_CASPER_1 \
355  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)
356 #define QLA82XX_CRB_CASPER_2 \
357  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)
358 #define QLA82XX_CRB_DDR_MD \
359  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)
360 #define QLA82XX_CRB_DDR_NET \
361  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)
362 #define QLA82XX_CRB_EPG \
363  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)
364 #define QLA82XX_CRB_I2Q \
365  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)
366 #define QLA82XX_CRB_NIU \
367  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)
368 
369 #define QLA82XX_CRB_PCIX_HOST \
370  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)
371 #define QLA82XX_CRB_PCIX_HOST2 \
372  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)
373 #define QLA82XX_CRB_PCIX_MD \
374  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)
375 #define QLA82XX_CRB_PCIE \
376  QLA82XX_CRB_PCIX_MD
377 
378 /* window 1 pcie slot */
379 #define QLA82XX_CRB_PCIE2 \
380  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)
381 #define QLA82XX_CRB_PEG_MD_0 \
382  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)
383 #define QLA82XX_CRB_PEG_MD_1 \
384  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)
385 #define QLA82XX_CRB_PEG_MD_2 \
386  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)
387 #define QLA82XX_CRB_PEG_MD_3 \
388  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
389 #define QLA82XX_CRB_PEG_MD_3 \
390  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
391 #define QLA82XX_CRB_PEG_MD_D \
392  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)
393 #define QLA82XX_CRB_PEG_MD_I \
394  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)
395 #define QLA82XX_CRB_PEG_NET_0 \
396  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)
397 #define QLA82XX_CRB_PEG_NET_1 \
398  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)
399 #define QLA82XX_CRB_PEG_NET_2 \
400  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)
401 #define QLA82XX_CRB_PEG_NET_3 \
402  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)
403 #define QLA82XX_CRB_PEG_NET_4 \
404  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)
405 #define QLA82XX_CRB_PEG_NET_D \
406  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)
407 #define QLA82XX_CRB_PEG_NET_I \
408  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)
409 #define QLA82XX_CRB_PQM_MD \
410  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)
411 #define QLA82XX_CRB_PQM_NET \
412  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)
413 #define QLA82XX_CRB_QDR_MD \
414  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)
415 #define QLA82XX_CRB_QDR_NET \
416  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)
417 #define QLA82XX_CRB_ROMUSB \
418  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)
419 #define QLA82XX_CRB_RPMX_0 \
420  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)
421 #define QLA82XX_CRB_RPMX_1 \
422  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)
423 #define QLA82XX_CRB_RPMX_2 \
424  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)
425 #define QLA82XX_CRB_RPMX_3 \
426  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)
427 #define QLA82XX_CRB_RPMX_4 \
428  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)
429 #define QLA82XX_CRB_RPMX_5 \
430  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)
431 #define QLA82XX_CRB_RPMX_6 \
432  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)
433 #define QLA82XX_CRB_RPMX_7 \
434  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)
435 #define QLA82XX_CRB_SQM_MD_0 \
436  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)
437 #define QLA82XX_CRB_SQM_MD_1 \
438  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)
439 #define QLA82XX_CRB_SQM_MD_2 \
440  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)
441 #define QLA82XX_CRB_SQM_MD_3 \
442  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)
443 #define QLA82XX_CRB_SQM_NET_0 \
444  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)
445 #define QLA82XX_CRB_SQM_NET_1 \
446  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)
447 #define QLA82XX_CRB_SQM_NET_2 \
448  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)
449 #define QLA82XX_CRB_SQM_NET_3 \
450  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)
451 #define QLA82XX_CRB_SRE \
452  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)
453 #define QLA82XX_CRB_TIMER \
454  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)
455 #define QLA82XX_CRB_XDMA \
456  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)
457 #define QLA82XX_CRB_I2C0 \
458  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)
459 #define QLA82XX_CRB_I2C1 \
460  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)
461 #define QLA82XX_CRB_OCM0 \
462  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)
463 #define QLA82XX_CRB_SMB \
464  QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)
465 #define QLA82XX_CRB_MAX \
466  QLA82XX_PCI_CRB_WINDOW(64)
467 
468 /*
469  * ====================== BASE ADDRESSES ON-CHIP ======================
470  * Base addresses of major components on-chip.
471  * ====================== BASE ADDRESSES ON-CHIP ======================
472  */
473 #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL)
474 #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
475 
476 /* Imbus address bit used to indicate a host address. This bit is
477  * eliminated by the pcie bar and bar select before presentation
478  * over pcie. */
479 /* host memory via IMBUS */
480 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
481 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
482 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
483 #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL)
484 #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL)
485 #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL)
486 #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL)
487 #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL)
488 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
489 
490 #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
491 #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
492 #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
493 #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
494 #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
495 #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
496 #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
497 
498 /*
499  * Register offsets for MN
500  */
501 #define MIU_CONTROL (0x000)
502 #define MIU_TAG (0x004)
503 #define MIU_TEST_AGT_CTRL (0x090)
504 #define MIU_TEST_AGT_ADDR_LO (0x094)
505 #define MIU_TEST_AGT_ADDR_HI (0x098)
506 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
507 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
508 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
509 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
510 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
511 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
512 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
513 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
514 
515 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
516 #define MIU_TA_CTL_START 1
517 #define MIU_TA_CTL_ENABLE 2
518 #define MIU_TA_CTL_WRITE 4
519 #define MIU_TA_CTL_BUSY 8
520 
521 /*CAM RAM */
522 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
523 # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))
524 
525 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
526 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
527 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
528 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
529 
530 #define QLA82XX_CAMRAM_DB1 (QLA82XX_CAM_RAM(0x1b8))
531 #define QLA82XX_CAMRAM_DB2 (QLA82XX_CAM_RAM(0x1bc))
532 
533 #define HALT_STATUS_UNRECOVERABLE 0x80000000
534 #define HALT_STATUS_RECOVERABLE 0x40000000
535 
536 /* Driver Coexistence Defines */
537 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
538 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
539 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
540 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
541 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
542 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
543 
544 /* Every driver should use these Device State */
545 #define QLA8XXX_DEV_COLD 1
546 #define QLA8XXX_DEV_INITIALIZING 2
547 #define QLA8XXX_DEV_READY 3
548 #define QLA8XXX_DEV_NEED_RESET 4
549 #define QLA8XXX_DEV_NEED_QUIESCENT 5
550 #define QLA8XXX_DEV_FAILED 6
551 #define QLA8XXX_DEV_QUIESCENT 7
552 #define MAX_STATES 8 /* Increment if new state added */
553 #define QLA8XXX_BAD_VALUE 0xbad0bad0
554 
555 #define QLA82XX_IDC_VERSION 1
556 #define QLA82XX_ROM_DEV_INIT_TIMEOUT 30
557 #define QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT 10
558 
559 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
560 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
561 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
562 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
563 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
564 #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))
565 
566 #define PCIE_SETUP_FUNCTION (0x12040)
567 #define PCIE_SETUP_FUNCTION2 (0x12048)
568 
569 #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))
570 #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))
571 
572 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
573 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
574 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
575 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
576 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
577 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
578 
579 /* Different drive state */
580 #define QLA82XX_DRVST_NOT_RDY 0
581 #define QLA82XX_DRVST_RST_RDY 1
582 #define QLA82XX_DRVST_QSNT_RDY 2
583 
584 /* Different drive active state */
585 #define QLA82XX_DRV_NOT_ACTIVE 0
586 #define QLA82XX_DRV_ACTIVE 1
587 
588 /*
589  * The PCI VendorID and DeviceID for our board.
590  */
591 #define PCI_DEVICE_ID_QLOGIC_ISP8021 0x8021
592 
593 #define QLA82XX_MSIX_TBL_SPACE 8192
594 #define QLA82XX_PCI_REG_MSIX_TBL 0x44
595 #define QLA82XX_PCI_MSIX_CONTROL 0x40
596 
598  unsigned valid;
599  unsigned start_128M;
600  unsigned end_128M;
601  unsigned start_2M;
602 };
603 
604 struct crb_128M_2M_block_map {
606 };
607 
608 struct crb_addr_pair {
609  long addr;
610  long data;
611 };
612 
613 #define ADDR_ERROR ((unsigned long) 0xffffffff)
614 #define MAX_CTL_CHECK 1000
615 
616 /***************************************************************************
617  * PCI related defines.
618  **************************************************************************/
619 
620 /*
621  * Interrupt related defines.
622  */
623 #define PCIX_TARGET_STATUS (0x10118)
624 #define PCIX_TARGET_STATUS_F1 (0x10160)
625 #define PCIX_TARGET_STATUS_F2 (0x10164)
626 #define PCIX_TARGET_STATUS_F3 (0x10168)
627 #define PCIX_TARGET_STATUS_F4 (0x10360)
628 #define PCIX_TARGET_STATUS_F5 (0x10364)
629 #define PCIX_TARGET_STATUS_F6 (0x10368)
630 #define PCIX_TARGET_STATUS_F7 (0x1036c)
631 
632 #define PCIX_TARGET_MASK (0x10128)
633 #define PCIX_TARGET_MASK_F1 (0x10170)
634 #define PCIX_TARGET_MASK_F2 (0x10174)
635 #define PCIX_TARGET_MASK_F3 (0x10178)
636 #define PCIX_TARGET_MASK_F4 (0x10370)
637 #define PCIX_TARGET_MASK_F5 (0x10374)
638 #define PCIX_TARGET_MASK_F6 (0x10378)
639 #define PCIX_TARGET_MASK_F7 (0x1037c)
640 
641 /*
642  * Message Signaled Interrupts
643  */
644 #define PCIX_MSI_F0 (0x13000)
645 #define PCIX_MSI_F1 (0x13004)
646 #define PCIX_MSI_F2 (0x13008)
647 #define PCIX_MSI_F3 (0x1300c)
648 #define PCIX_MSI_F4 (0x13010)
649 #define PCIX_MSI_F5 (0x13014)
650 #define PCIX_MSI_F6 (0x13018)
651 #define PCIX_MSI_F7 (0x1301c)
652 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
653 #define PCIX_INT_VECTOR (0x10100)
654 #define PCIX_INT_MASK (0x10104)
655 
656 /*
657  * Interrupt state machine and other bits.
658  */
659 #define PCIE_MISCCFG_RC (0x1206c)
660 
661 #define ISR_INT_TARGET_STATUS \
662  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))
663 #define ISR_INT_TARGET_STATUS_F1 \
664  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
665 #define ISR_INT_TARGET_STATUS_F2 \
666  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
667 #define ISR_INT_TARGET_STATUS_F3 \
668  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
669 #define ISR_INT_TARGET_STATUS_F4 \
670  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
671 #define ISR_INT_TARGET_STATUS_F5 \
672  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
673 #define ISR_INT_TARGET_STATUS_F6 \
674  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
675 #define ISR_INT_TARGET_STATUS_F7 \
676  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
677 
678 #define ISR_INT_TARGET_MASK \
679  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))
680 #define ISR_INT_TARGET_MASK_F1 \
681  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
682 #define ISR_INT_TARGET_MASK_F2 \
683  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
684 #define ISR_INT_TARGET_MASK_F3 \
685  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
686 #define ISR_INT_TARGET_MASK_F4 \
687  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
688 #define ISR_INT_TARGET_MASK_F5 \
689  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
690 #define ISR_INT_TARGET_MASK_F6 \
691  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
692 #define ISR_INT_TARGET_MASK_F7 \
693  (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
694 
695 #define ISR_INT_VECTOR \
696  (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))
697 #define ISR_INT_MASK \
698  (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))
699 #define ISR_INT_STATE_REG \
700  (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))
701 
702 #define ISR_MSI_INT_TRIGGER(FUNC) \
703  (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
704 
705 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
706 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
707 
708 /*
709  * PCI Interrupt Vector Values.
710  */
711 #define PCIX_INT_VECTOR_BIT_F0 0x0080
712 #define PCIX_INT_VECTOR_BIT_F1 0x0100
713 #define PCIX_INT_VECTOR_BIT_F2 0x0200
714 #define PCIX_INT_VECTOR_BIT_F3 0x0400
715 #define PCIX_INT_VECTOR_BIT_F4 0x0800
716 #define PCIX_INT_VECTOR_BIT_F5 0x1000
717 #define PCIX_INT_VECTOR_BIT_F6 0x2000
718 #define PCIX_INT_VECTOR_BIT_F7 0x4000
719 
725 };
726 
727 #define QLA82XX_LEGACY_INTR_CONFIG \
728 { \
729  { \
730  .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
731  .tgt_status_reg = ISR_INT_TARGET_STATUS, \
732  .tgt_mask_reg = ISR_INT_TARGET_MASK, \
733  .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
734  \
735  { \
736  .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
737  .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
738  .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
739  .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
740  \
741  { \
742  .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
743  .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
744  .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
745  .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
746  \
747  { \
748  .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
749  .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
750  .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
751  .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
752  \
753  { \
754  .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
755  .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
756  .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
757  .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
758  \
759  { \
760  .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
761  .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
762  .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
763  .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
764  \
765  { \
766  .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
767  .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
768  .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
769  .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
770  \
771  { \
772  .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
773  .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
774  .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
775  .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
776 }
777 
778 #define BRDCFG_START 0x4000
779 #define BOOTLD_START 0x10000
780 #define IMAGE_START 0x100000
781 #define FLASH_ADDR_START 0x43000
782 
783 /* Magic number to let user know flash is programmed */
784 #define QLA82XX_BDINFO_MAGIC 0x12345678
785 #define QLA82XX_FW_MAGIC_OFFSET (BRDCFG_START + 0x128)
786 #define FW_SIZE_OFFSET (0x3e840c)
787 #define QLA82XX_FW_MIN_SIZE 0x3fffff
788 
789 /* UNIFIED ROMIMAGE START */
790 #define QLA82XX_URI_FW_MIN_SIZE 0xc8000
791 #define QLA82XX_URI_DIR_SECT_PRODUCT_TBL 0x0
792 #define QLA82XX_URI_DIR_SECT_BOOTLD 0x6
793 #define QLA82XX_URI_DIR_SECT_FW 0x7
794 
795 /* Offsets */
796 #define QLA82XX_URI_CHIP_REV_OFF 10
797 #define QLA82XX_URI_FLAGS_OFF 11
798 #define QLA82XX_URI_BIOS_VERSION_OFF 12
799 #define QLA82XX_URI_BOOTLD_IDX_OFF 27
800 #define QLA82XX_URI_FIRMWARE_IDX_OFF 29
801 
807 };
808 
813 };
814 
815 /* UNIFIED ROMIMAGE END */
816 
817 #define QLA82XX_UNIFIED_ROMIMAGE 3
818 #define QLA82XX_FLASH_ROMIMAGE 4
819 #define QLA82XX_UNKNOWN_ROMIMAGE 0xff
820 
821 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
822 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
823 
824 #ifndef readq
825 static inline u64 readq(void __iomem *addr)
826 {
827  return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
828 }
829 #endif
830 
831 #ifndef writeq
832 static inline void writeq(u64 val, void __iomem *addr)
833 {
834  writel(((u32) (val)), (addr));
835  writel(((u32) (val >> 32)), (addr + 4));
836 }
837 #endif
838 
839 /* Request and response queue size */
840 #define REQUEST_ENTRY_CNT_82XX 128 /* Number of request entries. */
841 #define RESPONSE_ENTRY_CNT_82XX 128 /* Number of response entries.*/
842 
843 /*
844  * ISP 8021 I/O Register Set structure definitions.
845  */
847  uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */
848  uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */
849  uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */
850 
851  uint16_t mailbox_in[32]; /* Mail box In registers */
853  uint32_t hint; /* Host interrupt register */
854 #define HINT_MBX_INT_PENDING BIT_0
856  uint16_t mailbox_out[32]; /* Mail box Out registers */
858 
859  uint32_t host_status; /* host status */
860 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
861 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
862  uint32_t host_int; /* Interrupt status. */
863 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
864 };
865 
866 struct fcp_cmnd {
867  struct scsi_lun lun;
872  uint8_t cdb[260]; /* 256 for CDB len and 4 for FCP_DL */
873 };
874 
875 struct dsd_dma {
876  struct list_head list;
878  void *dsd_addr;
879 };
880 
881 #define QLA_DSDS_PER_IOCB 37
882 #define QLA_DSD_SIZE 12
883 struct ct6_dsd {
889 };
890 
891 #define MBC_TOGGLE_INTERRUPT 0x10
892 #define MBC_SET_LED_CONFIG 0x125 /* FCoE specific LED control */
893 #define MBC_GET_LED_CONFIG 0x126 /* FCoE specific LED control */
894 
895 /* Flash offset */
896 #define FLT_REG_BOOTLOAD_82XX 0x72
897 #define FLT_REG_BOOT_CODE_82XX 0x78
898 #define FLT_REG_FW_82XX 0x74
899 #define FLT_REG_GOLD_FW_82XX 0x75
900 #define FLT_REG_VPD_82XX 0x81
901 
902 #define FA_VPD_SIZE_82XX 0x400
903 
904 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400
905 
906 /******************************************************************************
907 *
908 * Definitions specific to M25P flash
909 *
910 *******************************************************************************
911 * Instructions
912 */
913 #define M25P_INSTR_WREN 0x06
914 #define M25P_INSTR_WRDI 0x04
915 #define M25P_INSTR_RDID 0x9f
916 #define M25P_INSTR_RDSR 0x05
917 #define M25P_INSTR_WRSR 0x01
918 #define M25P_INSTR_READ 0x03
919 #define M25P_INSTR_FAST_READ 0x0b
920 #define M25P_INSTR_PP 0x02
921 #define M25P_INSTR_SE 0xd8
922 #define M25P_INSTR_BE 0xc7
923 #define M25P_INSTR_DP 0xb9
924 #define M25P_INSTR_RES 0xab
925 
926 /* Minidump related */
927 
928 /*
929  * Version of the template
930  * 4 Bytes
931  * X.Major.Minor.RELEASE
932  */
933 #define QLA82XX_MINIDUMP_VERSION 0x10101
934 
935 /*
936  * Entry Type Defines
937  */
938 #define QLA82XX_RDNOP 0
939 #define QLA82XX_RDCRB 1
940 #define QLA82XX_RDMUX 2
941 #define QLA82XX_QUEUE 3
942 #define QLA82XX_BOARD 4
943 #define QLA82XX_RDSRE 5
944 #define QLA82XX_RDOCM 6
945 #define QLA82XX_CACHE 10
946 #define QLA82XX_L1DAT 11
947 #define QLA82XX_L1INS 12
948 #define QLA82XX_L2DTG 21
949 #define QLA82XX_L2ITG 22
950 #define QLA82XX_L2DAT 23
951 #define QLA82XX_L2INS 24
952 #define QLA82XX_RDROM 71
953 #define QLA82XX_RDMEM 72
954 #define QLA82XX_CNTRL 98
955 #define QLA82XX_TLHDR 99
956 #define QLA82XX_RDEND 255
957 
958 /*
959  * Opcodes for Control Entries.
960  * These Flags are bit fields.
961  */
962 #define QLA82XX_DBG_OPCODE_WR 0x01
963 #define QLA82XX_DBG_OPCODE_RW 0x02
964 #define QLA82XX_DBG_OPCODE_AND 0x04
965 #define QLA82XX_DBG_OPCODE_OR 0x08
966 #define QLA82XX_DBG_OPCODE_POLL 0x10
967 #define QLA82XX_DBG_OPCODE_RDSTATE 0x20
968 #define QLA82XX_DBG_OPCODE_WRSTATE 0x40
969 #define QLA82XX_DBG_OPCODE_MDSTATE 0x80
970 
971 /*
972  * Template Header and Entry Header definitions start here.
973  */
974 
975 /*
976  * Template Header
977  * Parts of the template header can be modified by the driver.
978  * These include the saved_state_array, capture_debug_level, driver_timestamp
979  */
980 
981 #define QLA82XX_DBG_STATE_ARRAY_LEN 16
982 #define QLA82XX_DBG_CAP_SIZE_ARRAY_LEN 8
983 #define QLA82XX_DBG_RSVD_ARRAY_LEN 8
984 
985 /*
986  * Driver Flags
987  */
988 #define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
989 #define QLA82XX_DEFAULT_CAP_MASK 0xFF /* default capture mask */
990 
996 
1001 
1004 
1007 
1008  /* markers_array used to capture some special locations on board */
1010  uint32_t num_of_free_entries; /* For internal use */
1011  uint32_t free_entry_offset; /* For internal use */
1012  uint32_t total_table_size; /* For internal use */
1013  uint32_t bkup_table_offset; /* For internal use */
1014 } __packed;
1015 
1016 /*
1017  * Entry Header: Common to All Entry Types
1018  */
1019 
1020 /*
1021  * Driver Code is for driver to write some info about the entry.
1022  * Currently not used.
1023  */
1024 typedef struct qla82xx_md_entry_hdr {
1028  struct {
1033  } d_ctrl;
1035 
1036 /*
1037  * Read CRB entry header
1038  */
1040  qla82xx_md_entry_hdr_t h;
1042  struct {
1046  } crb_strd;
1047 
1050 
1051  struct {
1056  } crb_ctrl;
1057 
1061 } __packed;
1062 
1063 /*
1064  * Cache entry header
1065  */
1067  qla82xx_md_entry_hdr_t h;
1068 
1070  struct {
1073  } addr_ctrl;
1074 
1077 
1079  struct {
1083  } cache_ctrl;
1084 
1086  struct {
1090  } read_ctrl;
1091 } __packed;
1092 
1093 /*
1094  * Read OCM
1095  */
1097  qla82xx_md_entry_hdr_t h;
1098 
1103 
1109 } __packed;
1110 
1111 /*
1112  * Read Memory
1113  */
1115  qla82xx_md_entry_hdr_t h;
1119 } __packed;
1120 
1121 /*
1122  * Read ROM
1123  */
1125  qla82xx_md_entry_hdr_t h;
1129 } __packed;
1130 
1132  qla82xx_md_entry_hdr_t h;
1133 
1138 
1143 } __packed;
1144 
1146  qla82xx_md_entry_hdr_t h;
1147 
1149  struct {
1152  } q_strd;
1153 
1158 
1160  struct {
1164  } rd_strd;
1165 } __packed;
1166 
1167 #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129
1168 #define RQST_TMPLT_SIZE 0x0
1169 #define RQST_TMPLT 0x1
1170 #define MD_DIRECT_ROM_WINDOW 0x42110030
1171 #define MD_DIRECT_ROM_READ_BASE 0x42150000
1172 #define MD_MIU_TEST_AGT_CTRL 0x41000090
1173 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1174 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1175 
1176 static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8, 0x410000AC,
1177  0x410000B8, 0x410000BC };
1178 
1179 #define CRB_NIU_XG_PAUSE_CTL_P0 0x1
1180 #define CRB_NIU_XG_PAUSE_CTL_P1 0x8
1181 
1182 #define qla82xx_get_temp_val(x) ((x) >> 16)
1183 #define qla82xx_get_temp_state(x) ((x) & 0xffff)
1184 #define qla82xx_encode_temp(val, state) (((val) << 16) | (state))
1185 
1186 /*
1187  * Temperature control.
1188  */
1189 enum {
1190  QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */
1191  QLA82XX_TEMP_WARN, /* Sound alert, temperature getting high */
1192  QLA82XX_TEMP_PANIC /* Fatal error, hardware has shut down. */
1193 };
1194 #endif