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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | Entry_header |
| struct | dataseg |
| struct | Command_Entry |
| struct | Ext_Command_Entry |
| struct | Continuation_Entry |
| struct | Marker_Entry |
| struct | Status_Entry |
| struct | host_param |
| struct | dev_param |
| struct | pti_queue_entry |
| struct | qlogicpti |
Macros | |
| #define | SBUS_CFG1 0x006UL |
| #define | SBUS_CTRL 0x008UL |
| #define | SBUS_STAT 0x00aUL |
| #define | SBUS_SEMAPHORE 0x00cUL |
| #define | CMD_DMA_CTRL 0x022UL |
| #define | DATA_DMA_CTRL 0x042UL |
| #define | MBOX0 0x080UL |
| #define | MBOX1 0x082UL |
| #define | MBOX2 0x084UL |
| #define | MBOX3 0x086UL |
| #define | MBOX4 0x088UL |
| #define | MBOX5 0x08aUL |
| #define | CPU_CMD 0x214UL |
| #define | CPU_ORIDE 0x224UL |
| #define | CPU_PCTRL 0x272UL |
| #define | CPU_PDIFF 0x276UL |
| #define | RISC_PSR 0x420UL |
| #define | RISC_MTREG 0x42EUL |
| #define | HCCTRL 0x440UL |
| #define | MAX_TARGETS 16 |
| #define | MAX_LUNS 8 |
| #define | QLOGICPTI_REQ_QUEUE_LEN 255 /* must be power of two - 1 */ |
| #define | QLOGICPTI_MAX_SG(ql) (4 + (((ql) > 0) ? 7*((ql) - 1) : 0)) |
| #define | MBOX_COMMAND_COMPLETE 0x4000 |
| #define | INVALID_COMMAND 0x4001 |
| #define | HOST_INTERFACE_ERROR 0x4002 |
| #define | TEST_FAILED 0x4003 |
| #define | COMMAND_ERROR 0x4005 |
| #define | COMMAND_PARAM_ERROR 0x4006 |
| #define | ASYNC_SCSI_BUS_RESET 0x8001 |
| #define | SYSTEM_ERROR 0x8002 |
| #define | REQUEST_TRANSFER_ERROR 0x8003 |
| #define | RESPONSE_TRANSFER_ERROR 0x8004 |
| #define | REQUEST_QUEUE_WAKEUP 0x8005 |
| #define | EXECUTION_TIMEOUT_RESET 0x8006 |
| #define | ENTRY_COMMAND 1 |
| #define | ENTRY_CONTINUATION 2 |
| #define | ENTRY_STATUS 3 |
| #define | ENTRY_MARKER 4 |
| #define | ENTRY_EXTENDED_COMMAND 5 |
| #define | EFLAG_CONTINUATION 1 |
| #define | EFLAG_BUSY 2 |
| #define | EFLAG_BAD_HEADER 4 |
| #define | EFLAG_BAD_PAYLOAD 8 |
| #define | CFLAG_NODISC 0x01 |
| #define | CFLAG_HEAD_TAG 0x02 |
| #define | CFLAG_ORDERED_TAG 0x04 |
| #define | CFLAG_SIMPLE_TAG 0x08 |
| #define | CFLAG_TAR_RTN 0x10 |
| #define | CFLAG_READ 0x20 |
| #define | CFLAG_WRITE 0x40 |
| #define | SYNC_DEVICE 0 |
| #define | SYNC_TARGET 1 |
| #define | SYNC_ALL 2 |
| #define | CS_COMPLETE 0x0000 |
| #define | CS_INCOMPLETE 0x0001 |
| #define | CS_DMA_ERROR 0x0002 |
| #define | CS_TRANSPORT_ERROR 0x0003 |
| #define | CS_RESET_OCCURRED 0x0004 |
| #define | CS_ABORTED 0x0005 |
| #define | CS_TIMEOUT 0x0006 |
| #define | CS_DATA_OVERRUN 0x0007 |
| #define | CS_COMMAND_OVERRUN 0x0008 |
| #define | CS_STATUS_OVERRUN 0x0009 |
| #define | CS_BAD_MESSAGE 0x000a |
| #define | CS_NO_MESSAGE_OUT 0x000b |
| #define | CS_EXT_ID_FAILED 0x000c |
| #define | CS_IDE_MSG_FAILED 0x000d |
| #define | CS_ABORT_MSG_FAILED 0x000e |
| #define | CS_REJECT_MSG_FAILED 0x000f |
| #define | CS_NOP_MSG_FAILED 0x0010 |
| #define | CS_PARITY_ERROR_MSG_FAILED 0x0011 |
| #define | CS_DEVICE_RESET_MSG_FAILED 0x0012 |
| #define | CS_ID_MSG_FAILED 0x0013 |
| #define | CS_UNEXP_BUS_FREE 0x0014 |
| #define | CS_DATA_UNDERRUN 0x0015 |
| #define | CS_BUS_RESET 0x001c |
| #define | SF_GOT_BUS 0x0100 |
| #define | SF_GOT_TARGET 0x0200 |
| #define | SF_SENT_CDB 0x0400 |
| #define | SF_TRANSFERRED_DATA 0x0800 |
| #define | SF_GOT_STATUS 0x1000 |
| #define | SF_GOT_SENSE 0x2000 |
| #define | STF_DISCONNECT 0x0001 |
| #define | STF_SYNCHRONOUS 0x0002 |
| #define | STF_PARITY_ERROR 0x0004 |
| #define | STF_BUS_RESET 0x0008 |
| #define | STF_DEVICE_RESET 0x0010 |
| #define | STF_ABORTED 0x0020 |
| #define | STF_TIMEOUT 0x0040 |
| #define | STF_NEGOTIATION 0x0080 |
| #define | MBOX_NO_OP 0x0000 |
| #define | MBOX_LOAD_RAM 0x0001 |
| #define | MBOX_EXEC_FIRMWARE 0x0002 |
| #define | MBOX_DUMP_RAM 0x0003 |
| #define | MBOX_WRITE_RAM_WORD 0x0004 |
| #define | MBOX_READ_RAM_WORD 0x0005 |
| #define | MBOX_MAILBOX_REG_TEST 0x0006 |
| #define | MBOX_VERIFY_CHECKSUM 0x0007 |
| #define | MBOX_ABOUT_FIRMWARE 0x0008 |
| #define | MBOX_CHECK_FIRMWARE 0x000e |
| #define | MBOX_INIT_REQ_QUEUE 0x0010 |
| #define | MBOX_INIT_RES_QUEUE 0x0011 |
| #define | MBOX_EXECUTE_IOCB 0x0012 |
| #define | MBOX_WAKE_UP 0x0013 |
| #define | MBOX_STOP_FIRMWARE 0x0014 |
| #define | MBOX_ABORT 0x0015 |
| #define | MBOX_ABORT_DEVICE 0x0016 |
| #define | MBOX_ABORT_TARGET 0x0017 |
| #define | MBOX_BUS_RESET 0x0018 |
| #define | MBOX_STOP_QUEUE 0x0019 |
| #define | MBOX_START_QUEUE 0x001a |
| #define | MBOX_SINGLE_STEP_QUEUE 0x001b |
| #define | MBOX_ABORT_QUEUE 0x001c |
| #define | MBOX_GET_DEV_QUEUE_STATUS 0x001d |
| #define | MBOX_GET_FIRMWARE_STATUS 0x001f |
| #define | MBOX_GET_INIT_SCSI_ID 0x0020 |
| #define | MBOX_GET_SELECT_TIMEOUT 0x0021 |
| #define | MBOX_GET_RETRY_COUNT 0x0022 |
| #define | MBOX_GET_TAG_AGE_LIMIT 0x0023 |
| #define | MBOX_GET_CLOCK_RATE 0x0024 |
| #define | MBOX_GET_ACT_NEG_STATE 0x0025 |
| #define | MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 |
| #define | MBOX_GET_SBUS_PARAMS 0x0027 |
| #define | MBOX_GET_TARGET_PARAMS 0x0028 |
| #define | MBOX_GET_DEV_QUEUE_PARAMS 0x0029 |
| #define | MBOX_SET_INIT_SCSI_ID 0x0030 |
| #define | MBOX_SET_SELECT_TIMEOUT 0x0031 |
| #define | MBOX_SET_RETRY_COUNT 0x0032 |
| #define | MBOX_SET_TAG_AGE_LIMIT 0x0033 |
| #define | MBOX_SET_CLOCK_RATE 0x0034 |
| #define | MBOX_SET_ACTIVE_NEG_STATE 0x0035 |
| #define | MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 |
| #define | MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 |
| #define | MBOX_SET_TARGET_PARAMS 0x0038 |
| #define | MBOX_SET_DEV_QUEUE_PARAMS 0x0039 |
| #define | RES_QUEUE_LEN 255 /* Must be power of two - 1 */ |
| #define | QUEUE_ENTRY_LEN 64 |
| #define | NEXT_REQ_PTR(wheee) (((wheee) + 1) & QLOGICPTI_REQ_QUEUE_LEN) |
| #define | NEXT_RES_PTR(wheee) (((wheee) + 1) & RES_QUEUE_LEN) |
| #define | PREV_REQ_PTR(wheee) (((wheee) - 1) & QLOGICPTI_REQ_QUEUE_LEN) |
| #define | PREV_RES_PTR(wheee) (((wheee) - 1) & RES_QUEUE_LEN) |
| #define | SREG_TPOWER 0x80 /* State of termpwr */ |
| #define | SREG_FUSE 0x40 /* State of on board fuse */ |
| #define | SREG_PDISAB 0x20 /* Disable state for power on */ |
| #define | SREG_DSENSE 0x10 /* Sense for differential */ |
| #define | SREG_IMASK 0x0c /* Interrupt level */ |
| #define | SREG_SPMASK 0x03 /* Mask for switch pack */ |
| #define | SBUS_CFG1_EPAR 0x0100 /* Enable parity checking */ |
| #define | SBUS_CFG1_FMASK 0x00f0 /* Forth code cycle mask */ |
| #define | SBUS_CFG1_BENAB 0x0004 /* Burst dvma enable */ |
| #define | SBUS_CFG1_B64 0x0003 /* Enable 64byte bursts */ |
| #define | SBUS_CFG1_B32 0x0002 /* Enable 32byte bursts */ |
| #define | SBUS_CFG1_B16 0x0001 /* Enable 16byte bursts */ |
| #define | SBUS_CFG1_B8 0x0008 /* Enable 8byte bursts */ |
| #define | SBUS_CTRL_EDIRQ 0x0020 /* Enable Data DVMA Interrupts */ |
| #define | SBUS_CTRL_ECIRQ 0x0010 /* Enable Command DVMA Interrupts */ |
| #define | SBUS_CTRL_ESIRQ 0x0008 /* Enable SCSI Processor Interrupts */ |
| #define | SBUS_CTRL_ERIRQ 0x0004 /* Enable RISC Processor Interrupts */ |
| #define | SBUS_CTRL_GENAB 0x0002 /* Global Interrupt Enable */ |
| #define | SBUS_CTRL_RESET 0x0001 /* Soft Reset */ |
| #define | SBUS_STAT_DINT 0x0020 /* Data DVMA IRQ pending */ |
| #define | SBUS_STAT_CINT 0x0010 /* Command DVMA IRQ pending */ |
| #define | SBUS_STAT_SINT 0x0008 /* SCSI Processor IRQ pending */ |
| #define | SBUS_STAT_RINT 0x0004 /* RISC Processor IRQ pending */ |
| #define | SBUS_STAT_GINT 0x0002 /* Global IRQ pending */ |
| #define | SBUS_SEMAPHORE_STAT 0x0002 /* Semaphore status bit */ |
| #define | SBUS_SEMAPHORE_LCK 0x0001 /* Semaphore lock bit */ |
| #define | DMA_CTRL_CSUSPEND 0x0010 /* DMA channel suspend */ |
| #define | DMA_CTRL_CCLEAR 0x0008 /* DMA channel clear and reset */ |
| #define | DMA_CTRL_FCLEAR 0x0004 /* DMA fifo clear */ |
| #define | DMA_CTRL_CIRQ 0x0002 /* DMA irq clear */ |
| #define | DMA_CTRL_DMASTART 0x0001 /* DMA transfer start */ |
| #define | CPU_ORIDE_ETRIG 0x8000 /* External trigger enable */ |
| #define | CPU_ORIDE_STEP 0x4000 /* Single step mode enable */ |
| #define | CPU_ORIDE_BKPT 0x2000 /* Breakpoint reg enable */ |
| #define | CPU_ORIDE_PWRITE 0x1000 /* SCSI pin write enable */ |
| #define | CPU_ORIDE_OFORCE 0x0800 /* Force outputs on */ |
| #define | CPU_ORIDE_LBACK 0x0400 /* SCSI loopback enable */ |
| #define | CPU_ORIDE_PTEST 0x0200 /* Parity test enable */ |
| #define | CPU_ORIDE_TENAB 0x0100 /* SCSI pins tristate enable */ |
| #define | CPU_ORIDE_TPINS 0x0080 /* SCSI pins enable */ |
| #define | CPU_ORIDE_FRESET 0x0008 /* FIFO reset */ |
| #define | CPU_ORIDE_CTERM 0x0004 /* Command terminate */ |
| #define | CPU_ORIDE_RREG 0x0002 /* Reset SCSI processor regs */ |
| #define | CPU_ORIDE_RMOD 0x0001 /* Reset SCSI processor module */ |
| #define | CPU_CMD_BRESET 0x300b /* Reset SCSI bus */ |
| #define | CPU_PCTRL_PVALID 0x8000 /* Phase bits are valid */ |
| #define | CPU_PCTRL_PHI 0x0400 /* Parity bit high */ |
| #define | CPU_PCTRL_PLO 0x0200 /* Parity bit low */ |
| #define | CPU_PCTRL_REQ 0x0100 /* REQ bus signal */ |
| #define | CPU_PCTRL_ACK 0x0080 /* ACK bus signal */ |
| #define | CPU_PCTRL_RST 0x0040 /* RST bus signal */ |
| #define | CPU_PCTRL_BSY 0x0020 /* BSY bus signal */ |
| #define | CPU_PCTRL_SEL 0x0010 /* SEL bus signal */ |
| #define | CPU_PCTRL_ATN 0x0008 /* ATN bus signal */ |
| #define | CPU_PCTRL_MSG 0x0004 /* MSG bus signal */ |
| #define | CPU_PCTRL_CD 0x0002 /* CD bus signal */ |
| #define | CPU_PCTRL_IO 0x0001 /* IO bus signal */ |
| #define | CPU_PDIFF_SENSE 0x0200 /* Differential sense */ |
| #define | CPU_PDIFF_MODE 0x0100 /* Differential mode */ |
| #define | CPU_PDIFF_OENAB 0x0080 /* Outputs enable */ |
| #define | CPU_PDIFF_PMASK 0x007c /* Differential control pins */ |
| #define | CPU_PDIFF_TGT 0x0002 /* Target mode enable */ |
| #define | CPU_PDIFF_INIT 0x0001 /* Initiator mode enable */ |
| #define | RISC_PSR_FTRUE 0x8000 /* Force true */ |
| #define | RISC_PSR_LCD 0x4000 /* Loop counter shows done status */ |
| #define | RISC_PSR_RIRQ 0x2000 /* RISC irq status */ |
| #define | RISC_PSR_TOFLOW 0x1000 /* Timer overflow (rollover) */ |
| #define | RISC_PSR_AOFLOW 0x0800 /* Arithmetic overflow */ |
| #define | RISC_PSR_AMSB 0x0400 /* Arithmetic big endian */ |
| #define | RISC_PSR_ACARRY 0x0200 /* Arithmetic carry */ |
| #define | RISC_PSR_AZERO 0x0100 /* Arithmetic zero */ |
| #define | RISC_PSR_ULTRA 0x0020 /* Ultra mode */ |
| #define | RISC_PSR_DIRQ 0x0010 /* DVMA interrupt */ |
| #define | RISC_PSR_SIRQ 0x0008 /* SCSI processor interrupt */ |
| #define | RISC_PSR_HIRQ 0x0004 /* Host interrupt */ |
| #define | RISC_PSR_IPEND 0x0002 /* Interrupt pending */ |
| #define | RISC_PSR_FFALSE 0x0001 /* Force false */ |
| #define | RISC_MTREG_P1DFLT 0x1200 /* Default read/write timing, pg1 */ |
| #define | RISC_MTREG_P0DFLT 0x0012 /* Default read/write timing, pg0 */ |
| #define | RISC_MTREG_P1ULTRA 0x2300 /* Ultra-mode rw timing, pg1 */ |
| #define | RISC_MTREG_P0ULTRA 0x0023 /* Ultra-mode rw timing, pg0 */ |
| #define | HCCTRL_NOP 0x0000 /* CMD: No operation */ |
| #define | HCCTRL_RESET 0x1000 /* CMD: Reset RISC cpu */ |
| #define | HCCTRL_PAUSE 0x2000 /* CMD: Pause RISC cpu */ |
| #define | HCCTRL_REL 0x3000 /* CMD: Release paused RISC cpu */ |
| #define | HCCTRL_STEP 0x4000 /* CMD: Single step RISC cpu */ |
| #define | HCCTRL_SHIRQ 0x5000 /* CMD: Set host irq */ |
| #define | HCCTRL_CHIRQ 0x6000 /* CMD: Clear host irq */ |
| #define | HCCTRL_CRIRQ 0x7000 /* CMD: Clear RISC cpu irq */ |
| #define | HCCTRL_BKPT 0x8000 /* CMD: Breakpoint enables change */ |
| #define | HCCTRL_TMODE 0xf000 /* CMD: Enable test mode */ |
| #define | HCCTRL_HIRQ 0x0080 /* Host IRQ pending */ |
| #define | HCCTRL_RRIP 0x0040 /* RISC cpu reset in happening now */ |
| #define | HCCTRL_RPAUSED 0x0020 /* RISC cpu is paused now */ |
| #define | HCCTRL_EBENAB 0x0010 /* External breakpoint enable */ |
| #define | HCCTRL_B1ENAB 0x0008 /* Breakpoint 1 enable */ |
| #define | HCCTRL_B0ENAB 0x0004 /* Breakpoint 0 enable */ |
| #define | for_each_qlogicpti(qp) for((qp) = qptichain; (qp); (qp) = (qp)->next) |
| #define ASYNC_SCSI_BUS_RESET 0x8001 |
Definition at line 57 of file qlogicpti.h.
| #define CFLAG_HEAD_TAG 0x02 |
Definition at line 118 of file qlogicpti.h.
| #define CFLAG_NODISC 0x01 |
Definition at line 117 of file qlogicpti.h.
| #define CFLAG_ORDERED_TAG 0x04 |
Definition at line 119 of file qlogicpti.h.
| #define CFLAG_READ 0x20 |
Definition at line 122 of file qlogicpti.h.
| #define CFLAG_SIMPLE_TAG 0x08 |
Definition at line 120 of file qlogicpti.h.
| #define CFLAG_TAR_RTN 0x10 |
Definition at line 121 of file qlogicpti.h.
| #define CFLAG_WRITE 0x40 |
Definition at line 123 of file qlogicpti.h.
| #define CMD_DMA_CTRL 0x022UL |
Definition at line 14 of file qlogicpti.h.
| #define COMMAND_ERROR 0x4005 |
Definition at line 53 of file qlogicpti.h.
| #define COMMAND_PARAM_ERROR 0x4006 |
Definition at line 54 of file qlogicpti.h.
| #define CPU_CMD 0x214UL |
Definition at line 22 of file qlogicpti.h.
| #define CPU_CMD_BRESET 0x300b /* Reset SCSI bus */ |
Definition at line 439 of file qlogicpti.h.
| #define CPU_ORIDE 0x224UL |
Definition at line 23 of file qlogicpti.h.
| #define CPU_ORIDE_BKPT 0x2000 /* Breakpoint reg enable */ |
Definition at line 426 of file qlogicpti.h.
| #define CPU_ORIDE_CTERM 0x0004 /* Command terminate */ |
Definition at line 434 of file qlogicpti.h.
| #define CPU_ORIDE_ETRIG 0x8000 /* External trigger enable */ |
Definition at line 424 of file qlogicpti.h.
| #define CPU_ORIDE_FRESET 0x0008 /* FIFO reset */ |
Definition at line 433 of file qlogicpti.h.
| #define CPU_ORIDE_LBACK 0x0400 /* SCSI loopback enable */ |
Definition at line 429 of file qlogicpti.h.
| #define CPU_ORIDE_OFORCE 0x0800 /* Force outputs on */ |
Definition at line 428 of file qlogicpti.h.
| #define CPU_ORIDE_PTEST 0x0200 /* Parity test enable */ |
Definition at line 430 of file qlogicpti.h.
| #define CPU_ORIDE_PWRITE 0x1000 /* SCSI pin write enable */ |
Definition at line 427 of file qlogicpti.h.
| #define CPU_ORIDE_RMOD 0x0001 /* Reset SCSI processor module */ |
Definition at line 436 of file qlogicpti.h.
| #define CPU_ORIDE_RREG 0x0002 /* Reset SCSI processor regs */ |
Definition at line 435 of file qlogicpti.h.
| #define CPU_ORIDE_STEP 0x4000 /* Single step mode enable */ |
Definition at line 425 of file qlogicpti.h.
| #define CPU_ORIDE_TENAB 0x0100 /* SCSI pins tristate enable */ |
Definition at line 431 of file qlogicpti.h.
| #define CPU_ORIDE_TPINS 0x0080 /* SCSI pins enable */ |
Definition at line 432 of file qlogicpti.h.
| #define CPU_PCTRL 0x272UL |
Definition at line 24 of file qlogicpti.h.
| #define CPU_PCTRL_ACK 0x0080 /* ACK bus signal */ |
Definition at line 446 of file qlogicpti.h.
| #define CPU_PCTRL_ATN 0x0008 /* ATN bus signal */ |
Definition at line 450 of file qlogicpti.h.
| #define CPU_PCTRL_BSY 0x0020 /* BSY bus signal */ |
Definition at line 448 of file qlogicpti.h.
| #define CPU_PCTRL_CD 0x0002 /* CD bus signal */ |
Definition at line 452 of file qlogicpti.h.
| #define CPU_PCTRL_IO 0x0001 /* IO bus signal */ |
Definition at line 453 of file qlogicpti.h.
| #define CPU_PCTRL_MSG 0x0004 /* MSG bus signal */ |
Definition at line 451 of file qlogicpti.h.
| #define CPU_PCTRL_PHI 0x0400 /* Parity bit high */ |
Definition at line 443 of file qlogicpti.h.
| #define CPU_PCTRL_PLO 0x0200 /* Parity bit low */ |
Definition at line 444 of file qlogicpti.h.
| #define CPU_PCTRL_PVALID 0x8000 /* Phase bits are valid */ |
Definition at line 442 of file qlogicpti.h.
| #define CPU_PCTRL_REQ 0x0100 /* REQ bus signal */ |
Definition at line 445 of file qlogicpti.h.
| #define CPU_PCTRL_RST 0x0040 /* RST bus signal */ |
Definition at line 447 of file qlogicpti.h.
| #define CPU_PCTRL_SEL 0x0010 /* SEL bus signal */ |
Definition at line 449 of file qlogicpti.h.
| #define CPU_PDIFF 0x276UL |
Definition at line 25 of file qlogicpti.h.
| #define CPU_PDIFF_INIT 0x0001 /* Initiator mode enable */ |
Definition at line 461 of file qlogicpti.h.
| #define CPU_PDIFF_MODE 0x0100 /* Differential mode */ |
Definition at line 457 of file qlogicpti.h.
| #define CPU_PDIFF_OENAB 0x0080 /* Outputs enable */ |
Definition at line 458 of file qlogicpti.h.
| #define CPU_PDIFF_PMASK 0x007c /* Differential control pins */ |
Definition at line 459 of file qlogicpti.h.
| #define CPU_PDIFF_SENSE 0x0200 /* Differential sense */ |
Definition at line 456 of file qlogicpti.h.
| #define CPU_PDIFF_TGT 0x0002 /* Target mode enable */ |
Definition at line 460 of file qlogicpti.h.
| #define CS_ABORT_MSG_FAILED 0x000e |
Definition at line 203 of file qlogicpti.h.
| #define CS_ABORTED 0x0005 |
Definition at line 194 of file qlogicpti.h.
| #define CS_BAD_MESSAGE 0x000a |
Definition at line 199 of file qlogicpti.h.
| #define CS_BUS_RESET 0x001c |
Definition at line 211 of file qlogicpti.h.
| #define CS_COMMAND_OVERRUN 0x0008 |
Definition at line 197 of file qlogicpti.h.
| #define CS_COMPLETE 0x0000 |
Definition at line 189 of file qlogicpti.h.
| #define CS_DATA_OVERRUN 0x0007 |
Definition at line 196 of file qlogicpti.h.
| #define CS_DATA_UNDERRUN 0x0015 |
Definition at line 210 of file qlogicpti.h.
| #define CS_DEVICE_RESET_MSG_FAILED 0x0012 |
Definition at line 207 of file qlogicpti.h.
| #define CS_DMA_ERROR 0x0002 |
Definition at line 191 of file qlogicpti.h.
| #define CS_EXT_ID_FAILED 0x000c |
Definition at line 201 of file qlogicpti.h.
| #define CS_ID_MSG_FAILED 0x0013 |
Definition at line 208 of file qlogicpti.h.
| #define CS_IDE_MSG_FAILED 0x000d |
Definition at line 202 of file qlogicpti.h.
| #define CS_INCOMPLETE 0x0001 |
Definition at line 190 of file qlogicpti.h.
| #define CS_NO_MESSAGE_OUT 0x000b |
Definition at line 200 of file qlogicpti.h.
| #define CS_NOP_MSG_FAILED 0x0010 |
Definition at line 205 of file qlogicpti.h.
| #define CS_PARITY_ERROR_MSG_FAILED 0x0011 |
Definition at line 206 of file qlogicpti.h.
| #define CS_REJECT_MSG_FAILED 0x000f |
Definition at line 204 of file qlogicpti.h.
| #define CS_RESET_OCCURRED 0x0004 |
Definition at line 193 of file qlogicpti.h.
| #define CS_STATUS_OVERRUN 0x0009 |
Definition at line 198 of file qlogicpti.h.
| #define CS_TIMEOUT 0x0006 |
Definition at line 195 of file qlogicpti.h.
| #define CS_TRANSPORT_ERROR 0x0003 |
Definition at line 192 of file qlogicpti.h.
| #define CS_UNEXP_BUS_FREE 0x0014 |
Definition at line 209 of file qlogicpti.h.
| #define DATA_DMA_CTRL 0x042UL |
Definition at line 15 of file qlogicpti.h.
| #define DMA_CTRL_CCLEAR 0x0008 /* DMA channel clear and reset */ |
Definition at line 418 of file qlogicpti.h.
| #define DMA_CTRL_CIRQ 0x0002 /* DMA irq clear */ |
Definition at line 420 of file qlogicpti.h.
| #define DMA_CTRL_CSUSPEND 0x0010 /* DMA channel suspend */ |
Definition at line 417 of file qlogicpti.h.
| #define DMA_CTRL_DMASTART 0x0001 /* DMA transfer start */ |
Definition at line 421 of file qlogicpti.h.
| #define DMA_CTRL_FCLEAR 0x0004 /* DMA fifo clear */ |
Definition at line 419 of file qlogicpti.h.
| #define EFLAG_BAD_HEADER 4 |
Definition at line 89 of file qlogicpti.h.
| #define EFLAG_BAD_PAYLOAD 8 |
Definition at line 90 of file qlogicpti.h.
| #define EFLAG_BUSY 2 |
Definition at line 88 of file qlogicpti.h.
| #define EFLAG_CONTINUATION 1 |
Definition at line 87 of file qlogicpti.h.
| #define ENTRY_COMMAND 1 |
Definition at line 80 of file qlogicpti.h.
| #define ENTRY_CONTINUATION 2 |
Definition at line 81 of file qlogicpti.h.
| #define ENTRY_EXTENDED_COMMAND 5 |
Definition at line 84 of file qlogicpti.h.
| #define ENTRY_MARKER 4 |
Definition at line 83 of file qlogicpti.h.
| #define ENTRY_STATUS 3 |
Definition at line 82 of file qlogicpti.h.
| #define EXECUTION_TIMEOUT_RESET 0x8006 |
Definition at line 62 of file qlogicpti.h.
Definition at line 504 of file qlogicpti.h.
| #define HCCTRL 0x440UL |
Definition at line 28 of file qlogicpti.h.
| #define HCCTRL_B0ENAB 0x0004 /* Breakpoint 0 enable */ |
Definition at line 501 of file qlogicpti.h.
| #define HCCTRL_B1ENAB 0x0008 /* Breakpoint 1 enable */ |
Definition at line 500 of file qlogicpti.h.
| #define HCCTRL_BKPT 0x8000 /* CMD: Breakpoint enables change */ |
Definition at line 494 of file qlogicpti.h.
| #define HCCTRL_CHIRQ 0x6000 /* CMD: Clear host irq */ |
Definition at line 492 of file qlogicpti.h.
| #define HCCTRL_CRIRQ 0x7000 /* CMD: Clear RISC cpu irq */ |
Definition at line 493 of file qlogicpti.h.
| #define HCCTRL_EBENAB 0x0010 /* External breakpoint enable */ |
Definition at line 499 of file qlogicpti.h.
| #define HCCTRL_HIRQ 0x0080 /* Host IRQ pending */ |
Definition at line 496 of file qlogicpti.h.
| #define HCCTRL_NOP 0x0000 /* CMD: No operation */ |
Definition at line 486 of file qlogicpti.h.
| #define HCCTRL_PAUSE 0x2000 /* CMD: Pause RISC cpu */ |
Definition at line 488 of file qlogicpti.h.
| #define HCCTRL_REL 0x3000 /* CMD: Release paused RISC cpu */ |
Definition at line 489 of file qlogicpti.h.
| #define HCCTRL_RESET 0x1000 /* CMD: Reset RISC cpu */ |
Definition at line 487 of file qlogicpti.h.
| #define HCCTRL_RPAUSED 0x0020 /* RISC cpu is paused now */ |
Definition at line 498 of file qlogicpti.h.
| #define HCCTRL_RRIP 0x0040 /* RISC cpu reset in happening now */ |
Definition at line 497 of file qlogicpti.h.
| #define HCCTRL_SHIRQ 0x5000 /* CMD: Set host irq */ |
Definition at line 491 of file qlogicpti.h.
| #define HCCTRL_STEP 0x4000 /* CMD: Single step RISC cpu */ |
Definition at line 490 of file qlogicpti.h.
| #define HCCTRL_TMODE 0xf000 /* CMD: Enable test mode */ |
Definition at line 495 of file qlogicpti.h.
| #define HOST_INTERFACE_ERROR 0x4002 |
Definition at line 51 of file qlogicpti.h.
| #define INVALID_COMMAND 0x4001 |
Definition at line 50 of file qlogicpti.h.
| #define MAX_LUNS 8 |
Definition at line 32 of file qlogicpti.h.
| #define MAX_TARGETS 16 |
Definition at line 31 of file qlogicpti.h.
| #define MBOX0 0x080UL |
Definition at line 16 of file qlogicpti.h.
| #define MBOX1 0x082UL |
Definition at line 17 of file qlogicpti.h.
| #define MBOX2 0x084UL |
Definition at line 18 of file qlogicpti.h.
| #define MBOX3 0x086UL |
Definition at line 19 of file qlogicpti.h.
| #define MBOX4 0x088UL |
Definition at line 20 of file qlogicpti.h.
| #define MBOX5 0x08aUL |
Definition at line 21 of file qlogicpti.h.
| #define MBOX_ABORT 0x0015 |
Definition at line 247 of file qlogicpti.h.
| #define MBOX_ABORT_DEVICE 0x0016 |
Definition at line 248 of file qlogicpti.h.
| #define MBOX_ABORT_QUEUE 0x001c |
Definition at line 254 of file qlogicpti.h.
| #define MBOX_ABORT_TARGET 0x0017 |
Definition at line 249 of file qlogicpti.h.
| #define MBOX_ABOUT_FIRMWARE 0x0008 |
Definition at line 240 of file qlogicpti.h.
| #define MBOX_BUS_RESET 0x0018 |
Definition at line 250 of file qlogicpti.h.
| #define MBOX_CHECK_FIRMWARE 0x000e |
Definition at line 241 of file qlogicpti.h.
| #define MBOX_COMMAND_COMPLETE 0x4000 |
Definition at line 49 of file qlogicpti.h.
| #define MBOX_DUMP_RAM 0x0003 |
Definition at line 235 of file qlogicpti.h.
| #define MBOX_EXEC_FIRMWARE 0x0002 |
Definition at line 234 of file qlogicpti.h.
| #define MBOX_EXECUTE_IOCB 0x0012 |
Definition at line 244 of file qlogicpti.h.
| #define MBOX_GET_ACT_NEG_STATE 0x0025 |
Definition at line 262 of file qlogicpti.h.
| #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 |
Definition at line 263 of file qlogicpti.h.
| #define MBOX_GET_CLOCK_RATE 0x0024 |
Definition at line 261 of file qlogicpti.h.
| #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 |
Definition at line 266 of file qlogicpti.h.
| #define MBOX_GET_DEV_QUEUE_STATUS 0x001d |
Definition at line 255 of file qlogicpti.h.
| #define MBOX_GET_FIRMWARE_STATUS 0x001f |
Definition at line 256 of file qlogicpti.h.
| #define MBOX_GET_INIT_SCSI_ID 0x0020 |
Definition at line 257 of file qlogicpti.h.
| #define MBOX_GET_RETRY_COUNT 0x0022 |
Definition at line 259 of file qlogicpti.h.
| #define MBOX_GET_SBUS_PARAMS 0x0027 |
Definition at line 264 of file qlogicpti.h.
| #define MBOX_GET_SELECT_TIMEOUT 0x0021 |
Definition at line 258 of file qlogicpti.h.
| #define MBOX_GET_TAG_AGE_LIMIT 0x0023 |
Definition at line 260 of file qlogicpti.h.
| #define MBOX_GET_TARGET_PARAMS 0x0028 |
Definition at line 265 of file qlogicpti.h.
| #define MBOX_INIT_REQ_QUEUE 0x0010 |
Definition at line 242 of file qlogicpti.h.
| #define MBOX_INIT_RES_QUEUE 0x0011 |
Definition at line 243 of file qlogicpti.h.
| #define MBOX_LOAD_RAM 0x0001 |
Definition at line 233 of file qlogicpti.h.
| #define MBOX_MAILBOX_REG_TEST 0x0006 |
Definition at line 238 of file qlogicpti.h.
| #define MBOX_NO_OP 0x0000 |
Definition at line 232 of file qlogicpti.h.
| #define MBOX_READ_RAM_WORD 0x0005 |
Definition at line 237 of file qlogicpti.h.
| #define MBOX_SET_ACTIVE_NEG_STATE 0x0035 |
Definition at line 272 of file qlogicpti.h.
| #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 |
Definition at line 273 of file qlogicpti.h.
| #define MBOX_SET_CLOCK_RATE 0x0034 |
Definition at line 271 of file qlogicpti.h.
| #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 |
Definition at line 276 of file qlogicpti.h.
| #define MBOX_SET_INIT_SCSI_ID 0x0030 |
Definition at line 267 of file qlogicpti.h.
| #define MBOX_SET_RETRY_COUNT 0x0032 |
Definition at line 269 of file qlogicpti.h.
| #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 |
Definition at line 274 of file qlogicpti.h.
| #define MBOX_SET_SELECT_TIMEOUT 0x0031 |
Definition at line 268 of file qlogicpti.h.
| #define MBOX_SET_TAG_AGE_LIMIT 0x0033 |
Definition at line 270 of file qlogicpti.h.
| #define MBOX_SET_TARGET_PARAMS 0x0038 |
Definition at line 275 of file qlogicpti.h.
| #define MBOX_SINGLE_STEP_QUEUE 0x001b |
Definition at line 253 of file qlogicpti.h.
| #define MBOX_START_QUEUE 0x001a |
Definition at line 252 of file qlogicpti.h.
| #define MBOX_STOP_FIRMWARE 0x0014 |
Definition at line 246 of file qlogicpti.h.
| #define MBOX_STOP_QUEUE 0x0019 |
Definition at line 251 of file qlogicpti.h.
| #define MBOX_VERIFY_CHECKSUM 0x0007 |
Definition at line 239 of file qlogicpti.h.
| #define MBOX_WAKE_UP 0x0013 |
Definition at line 245 of file qlogicpti.h.
| #define MBOX_WRITE_RAM_WORD 0x0004 |
Definition at line 236 of file qlogicpti.h.
| #define NEXT_REQ_PTR | ( | wheee | ) | (((wheee) + 1) & QLOGICPTI_REQ_QUEUE_LEN) |
Definition at line 324 of file qlogicpti.h.
| #define NEXT_RES_PTR | ( | wheee | ) | (((wheee) + 1) & RES_QUEUE_LEN) |
Definition at line 325 of file qlogicpti.h.
| #define PREV_REQ_PTR | ( | wheee | ) | (((wheee) - 1) & QLOGICPTI_REQ_QUEUE_LEN) |
Definition at line 326 of file qlogicpti.h.
| #define PREV_RES_PTR | ( | wheee | ) | (((wheee) - 1) & RES_QUEUE_LEN) |
Definition at line 327 of file qlogicpti.h.
| #define QLOGICPTI_MAX_SG | ( | ql | ) | (4 + (((ql) > 0) ? 7*((ql) - 1) : 0)) |
Definition at line 46 of file qlogicpti.h.
| #define QLOGICPTI_REQ_QUEUE_LEN 255 /* must be power of two - 1 */ |
Definition at line 45 of file qlogicpti.h.
| #define QUEUE_ENTRY_LEN 64 |
Definition at line 322 of file qlogicpti.h.
| #define REQUEST_QUEUE_WAKEUP 0x8005 |
Definition at line 61 of file qlogicpti.h.
| #define REQUEST_TRANSFER_ERROR 0x8003 |
Definition at line 59 of file qlogicpti.h.
| #define RES_QUEUE_LEN 255 /* Must be power of two - 1 */ |
Definition at line 321 of file qlogicpti.h.
| #define RESPONSE_TRANSFER_ERROR 0x8004 |
Definition at line 60 of file qlogicpti.h.
| #define RISC_MTREG 0x42EUL |
Definition at line 27 of file qlogicpti.h.
| #define RISC_MTREG_P0DFLT 0x0012 /* Default read/write timing, pg0 */ |
Definition at line 481 of file qlogicpti.h.
| #define RISC_MTREG_P0ULTRA 0x0023 /* Ultra-mode rw timing, pg0 */ |
Definition at line 483 of file qlogicpti.h.
| #define RISC_MTREG_P1DFLT 0x1200 /* Default read/write timing, pg1 */ |
Definition at line 480 of file qlogicpti.h.
| #define RISC_MTREG_P1ULTRA 0x2300 /* Ultra-mode rw timing, pg1 */ |
Definition at line 482 of file qlogicpti.h.
| #define RISC_PSR 0x420UL |
Definition at line 26 of file qlogicpti.h.
| #define RISC_PSR_ACARRY 0x0200 /* Arithmetic carry */ |
Definition at line 470 of file qlogicpti.h.
| #define RISC_PSR_AMSB 0x0400 /* Arithmetic big endian */ |
Definition at line 469 of file qlogicpti.h.
| #define RISC_PSR_AOFLOW 0x0800 /* Arithmetic overflow */ |
Definition at line 468 of file qlogicpti.h.
| #define RISC_PSR_AZERO 0x0100 /* Arithmetic zero */ |
Definition at line 471 of file qlogicpti.h.
| #define RISC_PSR_DIRQ 0x0010 /* DVMA interrupt */ |
Definition at line 473 of file qlogicpti.h.
| #define RISC_PSR_FFALSE 0x0001 /* Force false */ |
Definition at line 477 of file qlogicpti.h.
| #define RISC_PSR_FTRUE 0x8000 /* Force true */ |
Definition at line 464 of file qlogicpti.h.
| #define RISC_PSR_HIRQ 0x0004 /* Host interrupt */ |
Definition at line 475 of file qlogicpti.h.
| #define RISC_PSR_IPEND 0x0002 /* Interrupt pending */ |
Definition at line 476 of file qlogicpti.h.
| #define RISC_PSR_LCD 0x4000 /* Loop counter shows done status */ |
Definition at line 465 of file qlogicpti.h.
| #define RISC_PSR_RIRQ 0x2000 /* RISC irq status */ |
Definition at line 466 of file qlogicpti.h.
| #define RISC_PSR_SIRQ 0x0008 /* SCSI processor interrupt */ |
Definition at line 474 of file qlogicpti.h.
| #define RISC_PSR_TOFLOW 0x1000 /* Timer overflow (rollover) */ |
Definition at line 467 of file qlogicpti.h.
| #define RISC_PSR_ULTRA 0x0020 /* Ultra mode */ |
Definition at line 472 of file qlogicpti.h.
| #define SBUS_CFG1 0x006UL |
Definition at line 10 of file qlogicpti.h.
| #define SBUS_CFG1_B16 0x0001 /* Enable 16byte bursts */ |
Definition at line 394 of file qlogicpti.h.
| #define SBUS_CFG1_B32 0x0002 /* Enable 32byte bursts */ |
Definition at line 393 of file qlogicpti.h.
| #define SBUS_CFG1_B64 0x0003 /* Enable 64byte bursts */ |
Definition at line 392 of file qlogicpti.h.
| #define SBUS_CFG1_B8 0x0008 /* Enable 8byte bursts */ |
Definition at line 395 of file qlogicpti.h.
| #define SBUS_CFG1_BENAB 0x0004 /* Burst dvma enable */ |
Definition at line 391 of file qlogicpti.h.
| #define SBUS_CFG1_EPAR 0x0100 /* Enable parity checking */ |
Definition at line 389 of file qlogicpti.h.
| #define SBUS_CFG1_FMASK 0x00f0 /* Forth code cycle mask */ |
Definition at line 390 of file qlogicpti.h.
| #define SBUS_CTRL 0x008UL |
Definition at line 11 of file qlogicpti.h.
| #define SBUS_CTRL_ECIRQ 0x0010 /* Enable Command DVMA Interrupts */ |
Definition at line 399 of file qlogicpti.h.
| #define SBUS_CTRL_EDIRQ 0x0020 /* Enable Data DVMA Interrupts */ |
Definition at line 398 of file qlogicpti.h.
| #define SBUS_CTRL_ERIRQ 0x0004 /* Enable RISC Processor Interrupts */ |
Definition at line 401 of file qlogicpti.h.
| #define SBUS_CTRL_ESIRQ 0x0008 /* Enable SCSI Processor Interrupts */ |
Definition at line 400 of file qlogicpti.h.
| #define SBUS_CTRL_GENAB 0x0002 /* Global Interrupt Enable */ |
Definition at line 402 of file qlogicpti.h.
| #define SBUS_CTRL_RESET 0x0001 /* Soft Reset */ |
Definition at line 403 of file qlogicpti.h.
| #define SBUS_SEMAPHORE 0x00cUL |
Definition at line 13 of file qlogicpti.h.
| #define SBUS_SEMAPHORE_LCK 0x0001 /* Semaphore lock bit */ |
Definition at line 414 of file qlogicpti.h.
| #define SBUS_SEMAPHORE_STAT 0x0002 /* Semaphore status bit */ |
Definition at line 413 of file qlogicpti.h.
| #define SBUS_STAT 0x00aUL |
Definition at line 12 of file qlogicpti.h.
| #define SBUS_STAT_CINT 0x0010 /* Command DVMA IRQ pending */ |
Definition at line 407 of file qlogicpti.h.
| #define SBUS_STAT_DINT 0x0020 /* Data DVMA IRQ pending */ |
Definition at line 406 of file qlogicpti.h.
| #define SBUS_STAT_GINT 0x0002 /* Global IRQ pending */ |
Definition at line 410 of file qlogicpti.h.
| #define SBUS_STAT_RINT 0x0004 /* RISC Processor IRQ pending */ |
Definition at line 409 of file qlogicpti.h.
| #define SBUS_STAT_SINT 0x0008 /* SCSI Processor IRQ pending */ |
Definition at line 408 of file qlogicpti.h.
| #define SF_GOT_BUS 0x0100 |
Definition at line 214 of file qlogicpti.h.
| #define SF_GOT_SENSE 0x2000 |
Definition at line 219 of file qlogicpti.h.
| #define SF_GOT_STATUS 0x1000 |
Definition at line 218 of file qlogicpti.h.
| #define SF_GOT_TARGET 0x0200 |
Definition at line 215 of file qlogicpti.h.
| #define SF_SENT_CDB 0x0400 |
Definition at line 216 of file qlogicpti.h.
| #define SF_TRANSFERRED_DATA 0x0800 |
Definition at line 217 of file qlogicpti.h.
| #define SREG_DSENSE 0x10 /* Sense for differential */ |
Definition at line 377 of file qlogicpti.h.
| #define SREG_FUSE 0x40 /* State of on board fuse */ |
Definition at line 375 of file qlogicpti.h.
| #define SREG_IMASK 0x0c /* Interrupt level */ |
Definition at line 378 of file qlogicpti.h.
| #define SREG_PDISAB 0x20 /* Disable state for power on */ |
Definition at line 376 of file qlogicpti.h.
| #define SREG_SPMASK 0x03 /* Mask for switch pack */ |
Definition at line 379 of file qlogicpti.h.
| #define SREG_TPOWER 0x80 /* State of termpwr */ |
Definition at line 374 of file qlogicpti.h.
| #define STF_ABORTED 0x0020 |
Definition at line 227 of file qlogicpti.h.
| #define STF_BUS_RESET 0x0008 |
Definition at line 225 of file qlogicpti.h.
| #define STF_DEVICE_RESET 0x0010 |
Definition at line 226 of file qlogicpti.h.
| #define STF_DISCONNECT 0x0001 |
Definition at line 222 of file qlogicpti.h.
| #define STF_NEGOTIATION 0x0080 |
Definition at line 229 of file qlogicpti.h.
| #define STF_PARITY_ERROR 0x0004 |
Definition at line 224 of file qlogicpti.h.
| #define STF_SYNCHRONOUS 0x0002 |
Definition at line 223 of file qlogicpti.h.
| #define STF_TIMEOUT 0x0040 |
Definition at line 228 of file qlogicpti.h.
| #define SYNC_ALL 2 |
Definition at line 172 of file qlogicpti.h.
| #define SYNC_DEVICE 0 |
Definition at line 170 of file qlogicpti.h.
| #define SYNC_TARGET 1 |
Definition at line 171 of file qlogicpti.h.
| #define SYSTEM_ERROR 0x8002 |
Definition at line 58 of file qlogicpti.h.
| #define TEST_FAILED 0x4003 |
Definition at line 52 of file qlogicpti.h.
1.8.2