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Macros
r8192E_phyreg.h File Reference

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Macros

#define RF_DATA   0x1d4
 
#define rPMAC_Reset   0x100
 
#define rPMAC_TxStart   0x104
 
#define rPMAC_TxLegacySIG   0x108
 
#define rPMAC_TxHTSIG1   0x10c
 
#define rPMAC_TxHTSIG2   0x110
 
#define rPMAC_PHYDebug   0x114
 
#define rPMAC_TxPacketNum   0x118
 
#define rPMAC_TxIdle   0x11c
 
#define rPMAC_TxMACHeader0   0x120
 
#define rPMAC_TxMACHeader1   0x124
 
#define rPMAC_TxMACHeader2   0x128
 
#define rPMAC_TxMACHeader3   0x12c
 
#define rPMAC_TxMACHeader4   0x130
 
#define rPMAC_TxMACHeader5   0x134
 
#define rPMAC_TxDataType   0x138
 
#define rPMAC_TxRandomSeed   0x13c
 
#define rPMAC_CCKPLCPPreamble   0x140
 
#define rPMAC_CCKPLCPHeader   0x144
 
#define rPMAC_CCKCRC16   0x148
 
#define rPMAC_OFDMRxCRC32OK   0x170
 
#define rPMAC_OFDMRxCRC32Er   0x174
 
#define rPMAC_OFDMRxParityEr   0x178
 
#define rPMAC_OFDMRxCRC8Er   0x17c
 
#define rPMAC_CCKCRxRC16Er   0x180
 
#define rPMAC_CCKCRxRC32Er   0x184
 
#define rPMAC_CCKCRxRC32OK   0x188
 
#define rPMAC_TxStatus   0x18c
 
#define MCS_TXAGC   0x340
 
#define CCK_TXAGC   0x348
 
#define MacBlkCtrl   0x403
 
#define rFPGA0_RFMOD   0x800
 
#define rFPGA0_TxInfo   0x804
 
#define rFPGA0_PSDFunction   0x808
 
#define rFPGA0_TxGainStage   0x80c
 
#define rFPGA0_RFTiming1   0x810
 
#define rFPGA0_RFTiming2   0x814
 
#define rFPGA0_XA_HSSIParameter1   0x820
 
#define rFPGA0_XA_HSSIParameter2   0x824
 
#define rFPGA0_XB_HSSIParameter1   0x828
 
#define rFPGA0_XB_HSSIParameter2   0x82c
 
#define rFPGA0_XC_HSSIParameter1   0x830
 
#define rFPGA0_XC_HSSIParameter2   0x834
 
#define rFPGA0_XD_HSSIParameter1   0x838
 
#define rFPGA0_XD_HSSIParameter2   0x83c
 
#define rFPGA0_XA_LSSIParameter   0x840
 
#define rFPGA0_XB_LSSIParameter   0x844
 
#define rFPGA0_XC_LSSIParameter   0x848
 
#define rFPGA0_XD_LSSIParameter   0x84c
 
#define rFPGA0_RFWakeUpParameter   0x850
 
#define rFPGA0_RFSleepUpParameter   0x854
 
#define rFPGA0_XAB_SwitchControl   0x858
 
#define rFPGA0_XCD_SwitchControl   0x85c
 
#define rFPGA0_XA_RFInterfaceOE   0x860
 
#define rFPGA0_XB_RFInterfaceOE   0x864
 
#define rFPGA0_XC_RFInterfaceOE   0x868
 
#define rFPGA0_XD_RFInterfaceOE   0x86c
 
#define rFPGA0_XAB_RFInterfaceSW   0x870
 
#define rFPGA0_XCD_RFInterfaceSW   0x874
 
#define rFPGA0_XAB_RFParameter   0x878
 
#define rFPGA0_XCD_RFParameter   0x87c
 
#define rFPGA0_AnalogParameter1   0x880
 
#define rFPGA0_AnalogParameter2   0x884
 
#define rFPGA0_AnalogParameter3   0x888
 
#define rFPGA0_AnalogParameter4   0x88c
 
#define rFPGA0_XA_LSSIReadBack   0x8a0
 
#define rFPGA0_XB_LSSIReadBack   0x8a4
 
#define rFPGA0_XC_LSSIReadBack   0x8a8
 
#define rFPGA0_XD_LSSIReadBack   0x8ac
 
#define rFPGA0_PSDReport   0x8b4
 
#define rFPGA0_XAB_RFInterfaceRB   0x8e0
 
#define rFPGA0_XCD_RFInterfaceRB   0x8e4
 
#define rFPGA1_RFMOD   0x900
 
#define rFPGA1_TxBlock   0x904
 
#define rFPGA1_DebugSelect   0x908
 
#define rFPGA1_TxInfo   0x90c
 
#define rCCK0_System   0xa00
 
#define rCCK0_AFESetting   0xa04
 
#define rCCK0_CCA   0xa08
 
#define rCCK0_RxAGC1   0xa0c
 
#define rCCK0_RxAGC2   0xa10
 
#define rCCK0_RxHP   0xa14
 
#define rCCK0_DSPParameter1   0xa18
 
#define rCCK0_DSPParameter2   0xa1c
 
#define rCCK0_TxFilter1   0xa20
 
#define rCCK0_TxFilter2   0xa24
 
#define rCCK0_DebugPort   0xa28
 
#define rCCK0_FalseAlarmReport   0xa2c
 
#define rCCK0_TRSSIReport   0xa50
 
#define rCCK0_RxReport   0xa54
 
#define rCCK0_FACounterLower   0xa5c
 
#define rCCK0_FACounterUpper   0xa58
 
#define rOFDM0_LSTF   0xc00
 
#define rOFDM0_TRxPathEnable   0xc04
 
#define rOFDM0_TRMuxPar   0xc08
 
#define rOFDM0_TRSWIsolation   0xc0c
 
#define rOFDM0_XARxAFE   0xc10
 
#define rOFDM0_XARxIQImbalance   0xc14
 
#define rOFDM0_XBRxAFE   0xc18
 
#define rOFDM0_XBRxIQImbalance   0xc1c
 
#define rOFDM0_XCRxAFE   0xc20
 
#define rOFDM0_XCRxIQImbalance   0xc24
 
#define rOFDM0_XDRxAFE   0xc28
 
#define rOFDM0_XDRxIQImbalance   0xc2c
 
#define rOFDM0_RxDetector1   0xc30
 
#define rOFDM0_RxDetector2   0xc34
 
#define rOFDM0_RxDetector3   0xc38
 
#define rOFDM0_RxDetector4   0xc3c
 
#define rOFDM0_RxDSP   0xc40
 
#define rOFDM0_CFOandDAGC   0xc44
 
#define rOFDM0_CCADropThreshold   0xc48
 
#define rOFDM0_ECCAThreshold   0xc4c
 
#define rOFDM0_XAAGCCore1   0xc50
 
#define rOFDM0_XAAGCCore2   0xc54
 
#define rOFDM0_XBAGCCore1   0xc58
 
#define rOFDM0_XBAGCCore2   0xc5c
 
#define rOFDM0_XCAGCCore1   0xc60
 
#define rOFDM0_XCAGCCore2   0xc64
 
#define rOFDM0_XDAGCCore1   0xc68
 
#define rOFDM0_XDAGCCore2   0xc6c
 
#define rOFDM0_AGCParameter1   0xc70
 
#define rOFDM0_AGCParameter2   0xc74
 
#define rOFDM0_AGCRSSITable   0xc78
 
#define rOFDM0_HTSTFAGC   0xc7c
 
#define rOFDM0_XATxIQImbalance   0xc80
 
#define rOFDM0_XATxAFE   0xc84
 
#define rOFDM0_XBTxIQImbalance   0xc88
 
#define rOFDM0_XBTxAFE   0xc8c
 
#define rOFDM0_XCTxIQImbalance   0xc90
 
#define rOFDM0_XCTxAFE   0xc94
 
#define rOFDM0_XDTxIQImbalance   0xc98
 
#define rOFDM0_XDTxAFE   0xc9c
 
#define rOFDM0_RxHPParameter   0xce0
 
#define rOFDM0_TxPseudoNoiseWgt   0xce4
 
#define rOFDM0_FrameSync   0xcf0
 
#define rOFDM0_DFSReport   0xcf4
 
#define rOFDM0_TxCoeff1   0xca4
 
#define rOFDM0_TxCoeff2   0xca8
 
#define rOFDM0_TxCoeff3   0xcac
 
#define rOFDM0_TxCoeff4   0xcb0
 
#define rOFDM0_TxCoeff5   0xcb4
 
#define rOFDM0_TxCoeff6   0xcb8
 
#define rOFDM1_LSTF   0xd00
 
#define rOFDM1_TRxPathEnable   0xd04
 
#define rOFDM1_CFO   0xd08
 
#define rOFDM1_CSI1   0xd10
 
#define rOFDM1_SBD   0xd14
 
#define rOFDM1_CSI2   0xd18
 
#define rOFDM1_CFOTracking   0xd2c
 
#define rOFDM1_TRxMesaure1   0xd34
 
#define rOFDM1_IntfDet   0xd3c
 
#define rOFDM1_PseudoNoiseStateAB   0xd50
 
#define rOFDM1_PseudoNoiseStateCD   0xd54
 
#define rOFDM1_RxPseudoNoiseWgt   0xd58
 
#define rOFDM_PHYCounter1   0xda0
 
#define rOFDM_PHYCounter2   0xda4
 
#define rOFDM_PHYCounter3   0xda8
 
#define rOFDM_ShortCFOAB   0xdac
 
#define rOFDM_ShortCFOCD   0xdb0
 
#define rOFDM_LongCFOAB   0xdb4
 
#define rOFDM_LongCFOCD   0xdb8
 
#define rOFDM_TailCFOAB   0xdbc
 
#define rOFDM_TailCFOCD   0xdc0
 
#define rOFDM_PWMeasure1   0xdc4
 
#define rOFDM_PWMeasure2   0xdc8
 
#define rOFDM_BWReport   0xdcc
 
#define rOFDM_AGCReport   0xdd0
 
#define rOFDM_RxSNR   0xdd4
 
#define rOFDM_RxEVMCSI   0xdd8
 
#define rOFDM_SIGReport   0xddc
 
#define rTxAGC_Rate18_06   0xe00
 
#define rTxAGC_Rate54_24   0xe04
 
#define rTxAGC_CCK_Mcs32   0xe08
 
#define rTxAGC_Mcs03_Mcs00   0xe10
 
#define rTxAGC_Mcs07_Mcs04   0xe14
 
#define rTxAGC_Mcs11_Mcs08   0xe18
 
#define rTxAGC_Mcs15_Mcs12   0xe1c
 
#define rZebra1_HSSIEnable   0x0
 
#define rZebra1_TRxEnable1   0x1
 
#define rZebra1_TRxEnable2   0x2
 
#define rZebra1_AGC   0x4
 
#define rZebra1_ChargePump   0x5
 
#define rZebra1_Channel   0x7
 
#define rZebra1_TxGain   0x8
 
#define rZebra1_TxLPF   0x9
 
#define rZebra1_RxLPF   0xb
 
#define rZebra1_RxHPFCorner   0xc
 
#define rGlobalCtrl   0
 
#define rRTL8256_TxLPF   19
 
#define rRTL8256_RxLPF   11
 
#define rRTL8258_TxLPF   0x11
 
#define rRTL8258_RxLPF   0x13
 
#define rRTL8258_RSSILPF   0xa
 
#define bBBResetB   0x100
 
#define bGlobalResetB   0x200
 
#define bOFDMTxStart   0x4
 
#define bCCKTxStart   0x8
 
#define bCRC32Debug   0x100
 
#define bPMACLoopback   0x10
 
#define bTxLSIG   0xffffff
 
#define bOFDMTxRate   0xf
 
#define bOFDMTxReserved   0x10
 
#define bOFDMTxLength   0x1ffe0
 
#define bOFDMTxParity   0x20000
 
#define bTxHTSIG1   0xffffff
 
#define bTxHTMCSRate   0x7f
 
#define bTxHTBW   0x80
 
#define bTxHTLength   0xffff00
 
#define bTxHTSIG2   0xffffff
 
#define bTxHTSmoothing   0x1
 
#define bTxHTSounding   0x2
 
#define bTxHTReserved   0x4
 
#define bTxHTAggreation   0x8
 
#define bTxHTSTBC   0x30
 
#define bTxHTAdvanceCoding   0x40
 
#define bTxHTShortGI   0x80
 
#define bTxHTNumberHT_LTF   0x300
 
#define bTxHTCRC8   0x3fc00
 
#define bCounterReset   0x10000
 
#define bNumOfOFDMTx   0xffff
 
#define bNumOfCCKTx   0xffff0000
 
#define bTxIdleInterval   0xffff
 
#define bOFDMService   0xffff0000
 
#define bTxMACHeader   0xffffffff
 
#define bTxDataInit   0xff
 
#define bTxHTMode   0x100
 
#define bTxDataType   0x30000
 
#define bTxRandomSeed   0xffffffff
 
#define bCCKTxPreamble   0x1
 
#define bCCKTxSFD   0xffff0000
 
#define bCCKTxSIG   0xff
 
#define bCCKTxService   0xff00
 
#define bCCKLengthExt   0x8000
 
#define bCCKTxLength   0xffff0000
 
#define bCCKTxCRC16   0xffff
 
#define bCCKTxStatus   0x1
 
#define bOFDMTxStatus   0x2
 
#define bRFMOD   0x1
 
#define bJapanMode   0x2
 
#define bCCKTxSC   0x30
 
#define bCCKEn   0x1000000
 
#define bOFDMEn   0x2000000
 
#define bOFDMRxADCPhase   0x10000
 
#define bOFDMTxDACPhase   0x40000
 
#define bXATxAGC   0x3f
 
#define bXBTxAGC   0xf00
 
#define bXCTxAGC   0xf000
 
#define bXDTxAGC   0xf0000
 
#define bPAStart   0xf0000000
 
#define bTRStart   0x00f00000
 
#define bRFStart   0x0000f000
 
#define bBBStart   0x000000f0
 
#define bBBCCKStart   0x0000000f
 
#define bPAEnd   0xf
 
#define bTREnd   0x0f000000
 
#define bRFEnd   0x000f0000
 
#define bCCAMask   0x000000f0
 
#define bR2RCCAMask   0x00000f00
 
#define bHSSI_R2TDelay   0xf8000000
 
#define bHSSI_T2RDelay   0xf80000
 
#define bContTxHSSI   0x400
 
#define bIGFromCCK   0x200
 
#define bAGCAddress   0x3f
 
#define bRxHPTx   0x7000
 
#define bRxHPT2R   0x38000
 
#define bRxHPCCKIni   0xc0000
 
#define bAGCTxCode   0xc00000
 
#define bAGCRxCode   0x300000
 
#define b3WireDataLength   0x800
 
#define b3WireAddressLength   0x400
 
#define b3WireRFPowerDown   0x1
 
#define b5GPAPEPolarity   0x40000000
 
#define b2GPAPEPolarity   0x80000000
 
#define bRFSW_TxDefaultAnt   0x3
 
#define bRFSW_TxOptionAnt   0x30
 
#define bRFSW_RxDefaultAnt   0x300
 
#define bRFSW_RxOptionAnt   0x3000
 
#define bRFSI_3WireData   0x1
 
#define bRFSI_3WireClock   0x2
 
#define bRFSI_3WireLoad   0x4
 
#define bRFSI_3WireRW   0x8
 
#define bRFSI_3Wire   0xf
 
#define bRFSI_RFENV   0x10
 
#define bRFSI_TRSW   0x20
 
#define bRFSI_TRSWB   0x40
 
#define bRFSI_ANTSW   0x100
 
#define bRFSI_ANTSWB   0x200
 
#define bRFSI_PAPE   0x400
 
#define bRFSI_PAPE5G   0x800
 
#define bBandSelect   0x1
 
#define bHTSIG2_GI   0x80
 
#define bHTSIG2_Smoothing   0x01
 
#define bHTSIG2_Sounding   0x02
 
#define bHTSIG2_Aggreaton   0x08
 
#define bHTSIG2_STBC   0x30
 
#define bHTSIG2_AdvCoding   0x40
 
#define bHTSIG2_NumOfHTLTF   0x300
 
#define bHTSIG2_CRC8   0x3fc
 
#define bHTSIG1_MCS   0x7f
 
#define bHTSIG1_BandWidth   0x80
 
#define bHTSIG1_HTLength   0xffff
 
#define bLSIG_Rate   0xf
 
#define bLSIG_Reserved   0x10
 
#define bLSIG_Length   0x1fffe
 
#define bLSIG_Parity   0x20
 
#define bCCKRxPhase   0x4
 
#define bLSSIReadAddress   0x3f000000
 
#define bLSSIReadEdge   0x80000000
 
#define bLSSIReadBackData   0xfff
 
#define bLSSIReadOKFlag   0x1000
 
#define bCCKSampleRate   0x8
 
#define bRegulator0Standby   0x1
 
#define bRegulatorPLLStandby   0x2
 
#define bRegulator1Standby   0x4
 
#define bPLLPowerUp   0x8
 
#define bDPLLPowerUp   0x10
 
#define bDA10PowerUp   0x20
 
#define bAD7PowerUp   0x200
 
#define bDA6PowerUp   0x2000
 
#define bXtalPowerUp   0x4000
 
#define b40MDClkPowerUP   0x8000
 
#define bDA6DebugMode   0x20000
 
#define bDA6Swing   0x380000
 
#define bADClkPhase   0x4000000
 
#define b80MClkDelay   0x18000000
 
#define bAFEWatchDogEnable   0x20000000
 
#define bXtalCap   0x0f000000
 
#define bXtalCap01   0xc0000000
 
#define bXtalCap23   0x3
 
#define bXtalCap92x   0x0f000000
 
#define bIntDifClkEnable   0x400
 
#define bExtSigClkEnable   0x800
 
#define bBandgapMbiasPowerUp   0x10000
 
#define bAD11SHGain   0xc0000
 
#define bAD11InputRange   0x700000
 
#define bAD11OPCurrent   0x3800000
 
#define bIPathLoopback   0x4000000
 
#define bQPathLoopback   0x8000000
 
#define bAFELoopback   0x10000000
 
#define bDA10Swing   0x7e0
 
#define bDA10Reverse   0x800
 
#define bDAClkSource   0x1000
 
#define bAD7InputRange   0x6000
 
#define bAD7Gain   0x38000
 
#define bAD7OutputCMMode   0x40000
 
#define bAD7InputCMMode   0x380000
 
#define bAD7Current   0xc00000
 
#define bRegulatorAdjust   0x7000000
 
#define bAD11PowerUpAtTx   0x1
 
#define bDA10PSAtTx   0x10
 
#define bAD11PowerUpAtRx   0x100
 
#define bDA10PSAtRx   0x1000
 
#define bCCKRxAGCFormat   0x200
 
#define bPSDFFTSamplepPoint   0xc000
 
#define bPSDAverageNum   0x3000
 
#define bIQPathControl   0xc00
 
#define bPSDFreq   0x3ff
 
#define bPSDAntennaPath   0x30
 
#define bPSDIQSwitch   0x40
 
#define bPSDRxTrigger   0x400000
 
#define bPSDTxTrigger   0x80000000
 
#define bPSDSineToneScale   0x7f000000
 
#define bPSDReport   0xffff
 
#define bOFDMTxSC   0x30000000
 
#define bCCKTxOn   0x1
 
#define bOFDMTxOn   0x2
 
#define bDebugPage   0xfff
 
#define bDebugItem   0xff
 
#define bAntL   0x10
 
#define bAntNonHT   0x100
 
#define bAntHT1   0x1000
 
#define bAntHT2   0x10000
 
#define bAntHT1S1   0x100000
 
#define bAntNonHTS1   0x1000000
 
#define bCCKBBMode   0x3
 
#define bCCKTxPowerSaving   0x80
 
#define bCCKRxPowerSaving   0x40
 
#define bCCKSideBand   0x10
 
#define bCCKScramble   0x8
 
#define bCCKAntDiversity   0x8000
 
#define bCCKCarrierRecovery   0x4000
 
#define bCCKTxRate   0x3000
 
#define bCCKDCCancel   0x0800
 
#define bCCKISICancel   0x0400
 
#define bCCKMatchFilter   0x0200
 
#define bCCKEqualizer   0x0100
 
#define bCCKPreambleDetect   0x800000
 
#define bCCKFastFalseCCA   0x400000
 
#define bCCKChEstStart   0x300000
 
#define bCCKCCACount   0x080000
 
#define bCCKcs_lim   0x070000
 
#define bCCKBistMode   0x80000000
 
#define bCCKCCAMask   0x40000000
 
#define bCCKTxDACPhase   0x4
 
#define bCCKRxADCPhase   0x20000000
 
#define bCCKr_cp_mode0   0x0100
 
#define bCCKTxDCOffset   0xf0
 
#define bCCKRxDCOffset   0xf
 
#define bCCKCCAMode   0xc000
 
#define bCCKFalseCS_lim   0x3f00
 
#define bCCKCS_ratio   0xc00000
 
#define bCCKCorgBit_sel   0x300000
 
#define bCCKPD_lim   0x0f0000
 
#define bCCKNewCCA   0x80000000
 
#define bCCKRxHPofIG   0x8000
 
#define bCCKRxIG   0x7f00
 
#define bCCKLNAPolarity   0x800000
 
#define bCCKRx1stGain   0x7f0000
 
#define bCCKRFExtend   0x20000000
 
#define bCCKRxAGCSatLevel   0x1f000000
 
#define bCCKRxAGCSatCount   0xe0
 
#define bCCKRxRFSettle   0x1f
 
#define bCCKFixedRxAGC   0x8000
 
#define bCCKAntennaPolarity   0x2000
 
#define bCCKTxFilterType   0x0c00
 
#define bCCKRxAGCReportType   0x0300
 
#define bCCKRxDAGCEn   0x80000000
 
#define bCCKRxDAGCPeriod   0x20000000
 
#define bCCKRxDAGCSatLevel   0x1f000000
 
#define bCCKTimingRecovery   0x800000
 
#define bCCKTxC0   0x3f0000
 
#define bCCKTxC1   0x3f000000
 
#define bCCKTxC2   0x3f
 
#define bCCKTxC3   0x3f00
 
#define bCCKTxC4   0x3f0000
 
#define bCCKTxC5   0x3f000000
 
#define bCCKTxC6   0x3f
 
#define bCCKTxC7   0x3f00
 
#define bCCKDebugPort   0xff0000
 
#define bCCKDACDebug   0x0f000000
 
#define bCCKFalseAlarmEnable   0x8000
 
#define bCCKFalseAlarmRead   0x4000
 
#define bCCKTRSSI   0x7f
 
#define bCCKRxAGCReport   0xfe
 
#define bCCKRxReport_AntSel   0x80000000
 
#define bCCKRxReport_MFOff   0x40000000
 
#define bCCKRxRxReport_SQLoss   0x20000000
 
#define bCCKRxReport_Pktloss   0x10000000
 
#define bCCKRxReport_Lockedbit   0x08000000
 
#define bCCKRxReport_RateError   0x04000000
 
#define bCCKRxReport_RxRate   0x03000000
 
#define bCCKRxFACounterLower   0xff
 
#define bCCKRxFACounterUpper   0xff000000
 
#define bCCKRxHPAGCStart   0xe000
 
#define bCCKRxHPAGCFinal   0x1c00
 
#define bCCKRxFalseAlarmEnable   0x8000
 
#define bCCKFACounterFreeze   0x4000
 
#define bCCKTxPathSel   0x10000000
 
#define bCCKDefaultRxPath   0xc000000
 
#define bCCKOptionRxPath   0x3000000
 
#define bNumOfSTF   0x3
 
#define bShift_L   0xc0
 
#define bGI_TH   0xc
 
#define bRxPathA   0x1
 
#define bRxPathB   0x2
 
#define bRxPathC   0x4
 
#define bRxPathD   0x8
 
#define bTxPathA   0x1
 
#define bTxPathB   0x2
 
#define bTxPathC   0x4
 
#define bTxPathD   0x8
 
#define bTRSSIFreq   0x200
 
#define bADCBackoff   0x3000
 
#define bDFIRBackoff   0xc000
 
#define bTRSSILatchPhase   0x10000
 
#define bRxIDCOffset   0xff
 
#define bRxQDCOffset   0xff00
 
#define bRxDFIRMode   0x1800000
 
#define bRxDCNFType   0xe000000
 
#define bRXIQImb_A   0x3ff
 
#define bRXIQImb_B   0xfc00
 
#define bRXIQImb_C   0x3f0000
 
#define bRXIQImb_D   0xffc00000
 
#define bDC_dc_Notch   0x60000
 
#define bRxNBINotch   0x1f000000
 
#define bPD_TH   0xf
 
#define bPD_TH_Opt2   0xc000
 
#define bPWED_TH   0x700
 
#define bIfMF_Win_L   0x800
 
#define bPD_Option   0x1000
 
#define bMF_Win_L   0xe000
 
#define bBW_Search_L   0x30000
 
#define bwin_enh_L   0xc0000
 
#define bBW_TH   0x700000
 
#define bED_TH2   0x3800000
 
#define bBW_option   0x4000000
 
#define bRatio_TH   0x18000000
 
#define bWindow_L   0xe0000000
 
#define bSBD_Option   0x1
 
#define bFrame_TH   0x1c
 
#define bFS_Option   0x60
 
#define bDC_Slope_check   0x80
 
#define bFGuard_Counter_DC_L   0xe00
 
#define bFrame_Weight_Short   0x7000
 
#define bSub_Tune   0xe00000
 
#define bFrame_DC_Length   0xe000000
 
#define bSBD_start_offset   0x30000000
 
#define bFrame_TH_2   0x7
 
#define bFrame_GI2_TH   0x38
 
#define bGI2_Sync_en   0x40
 
#define bSarch_Short_Early   0x300
 
#define bSarch_Short_Late   0xc00
 
#define bSarch_GI2_Late   0x70000
 
#define bCFOAntSum   0x1
 
#define bCFOAcc   0x2
 
#define bCFOStartOffset   0xc
 
#define bCFOLookBack   0x70
 
#define bCFOSumWeight   0x80
 
#define bDAGCEnable   0x10000
 
#define bTXIQImb_A   0x3ff
 
#define bTXIQImb_B   0xfc00
 
#define bTXIQImb_C   0x3f0000
 
#define bTXIQImb_D   0xffc00000
 
#define bTxIDCOffset   0xff
 
#define bTxQDCOffset   0xff00
 
#define bTxDFIRMode   0x10000
 
#define bTxPesudoNoiseOn   0x4000000
 
#define bTxPesudoNoise_A   0xff
 
#define bTxPesudoNoise_B   0xff00
 
#define bTxPesudoNoise_C   0xff0000
 
#define bTxPesudoNoise_D   0xff000000
 
#define bCCADropOption   0x20000
 
#define bCCADropThres   0xfff00000
 
#define bEDCCA_H   0xf
 
#define bEDCCA_L   0xf0
 
#define bLambda_ED   0x300
 
#define bRxInitialGain   0x7f
 
#define bRxAntDivEn   0x80
 
#define bRxAGCAddressForLNA   0x7f00
 
#define bRxHighPowerFlow   0x8000
 
#define bRxAGCFreezeThres   0xc0000
 
#define bRxFreezeStep_AGC1   0x300000
 
#define bRxFreezeStep_AGC2   0xc00000
 
#define bRxFreezeStep_AGC3   0x3000000
 
#define bRxFreezeStep_AGC0   0xc000000
 
#define bRxRssi_Cmp_En   0x10000000
 
#define bRxQuickAGCEn   0x20000000
 
#define bRxAGCFreezeThresMode   0x40000000
 
#define bRxOverFlowCheckType   0x80000000
 
#define bRxAGCShift   0x7f
 
#define bTRSW_Tri_Only   0x80
 
#define bPowerThres   0x300
 
#define bRxAGCEn   0x1
 
#define bRxAGCTogetherEn   0x2
 
#define bRxAGCMin   0x4
 
#define bRxHP_Ini   0x7
 
#define bRxHP_TRLNA   0x70
 
#define bRxHP_RSSI   0x700
 
#define bRxHP_BBP1   0x7000
 
#define bRxHP_BBP2   0x70000
 
#define bRxHP_BBP3   0x700000
 
#define bRSSI_H   0x7f0000
 
#define bRSSI_Gen   0x7f000000
 
#define bRxSettle_TRSW   0x7
 
#define bRxSettle_LNA   0x38
 
#define bRxSettle_RSSI   0x1c0
 
#define bRxSettle_BBP   0xe00
 
#define bRxSettle_RxHP   0x7000
 
#define bRxSettle_AntSW_RSSI   0x38000
 
#define bRxSettle_AntSW   0xc0000
 
#define bRxProcessTime_DAGC   0x300000
 
#define bRxSettle_HSSI   0x400000
 
#define bRxProcessTime_BBPPW   0x800000
 
#define bRxAntennaPowerShift   0x3000000
 
#define bRSSITableSelect   0xc000000
 
#define bRxHP_Final   0x7000000
 
#define bRxHTSettle_BBP   0x7
 
#define bRxHTSettle_HSSI   0x8
 
#define bRxHTSettle_RxHP   0x70
 
#define bRxHTSettle_BBPPW   0x80
 
#define bRxHTSettle_Idle   0x300
 
#define bRxHTSettle_Reserved   0x1c00
 
#define bRxHTRxHPEn   0x8000
 
#define bRxHTAGCFreezeThres   0x30000
 
#define bRxHTAGCTogetherEn   0x40000
 
#define bRxHTAGCMin   0x80000
 
#define bRxHTAGCEn   0x100000
 
#define bRxHTDAGCEn   0x200000
 
#define bRxHTRxHP_BBP   0x1c00000
 
#define bRxHTRxHP_Final   0xe0000000
 
#define bRxPWRatioTH   0x3
 
#define bRxPWRatioEn   0x4
 
#define bRxMFHold   0x3800
 
#define bRxPD_Delay_TH1   0x38
 
#define bRxPD_Delay_TH2   0x1c0
 
#define bRxPD_DC_COUNT_MAX   0x600
 
#define bRxPD_Delay_TH   0x8000
 
#define bRxProcess_Delay   0xf0000
 
#define bRxSearchrange_GI2_Early   0x700000
 
#define bRxFrame_Guard_Counter_L   0x3800000
 
#define bRxSGI_Guard_L   0xc000000
 
#define bRxSGI_Search_L   0x30000000
 
#define bRxSGI_TH   0xc0000000
 
#define bDFSCnt0   0xff
 
#define bDFSCnt1   0xff00
 
#define bDFSFlag   0xf0000
 
#define bMFWeightSum   0x300000
 
#define bMinIdxTH   0x7f000000
 
#define bDAFormat   0x40000
 
#define bTxChEmuEnable   0x01000000
 
#define bTRSWIsolation_A   0x7f
 
#define bTRSWIsolation_B   0x7f00
 
#define bTRSWIsolation_C   0x7f0000
 
#define bTRSWIsolation_D   0x7f000000
 
#define bExtLNAGain   0x7c00
 
#define bSTBCEn   0x4
 
#define bAntennaMapping   0x10
 
#define bNss   0x20
 
#define bCFOAntSumD   0x200
 
#define bPHYCounterReset   0x8000000
 
#define bCFOReportGet   0x4000000
 
#define bOFDMContinueTx   0x10000000
 
#define bOFDMSingleCarrier   0x20000000
 
#define bOFDMSingleTone   0x40000000
 
#define bHTDetect   0x100
 
#define bCFOEn   0x10000
 
#define bCFOValue   0xfff00000
 
#define bSigTone_Re   0x3f
 
#define bSigTone_Im   0x7f00
 
#define bCounter_CCA   0xffff
 
#define bCounter_ParityFail   0xffff0000
 
#define bCounter_RateIllegal   0xffff
 
#define bCounter_CRC8Fail   0xffff0000
 
#define bCounter_MCSNoSupport   0xffff
 
#define bCounter_FastSync   0xffff
 
#define bShortCFO   0xfff
 
#define bShortCFOTLength   12
 
#define bShortCFOFLength   11
 
#define bLongCFO   0x7ff
 
#define bLongCFOTLength   11
 
#define bLongCFOFLength   11
 
#define bTailCFO   0x1fff
 
#define bTailCFOTLength   13
 
#define bTailCFOFLength   12
 
#define bmax_en_pwdB   0xffff
 
#define bCC_power_dB   0xffff0000
 
#define bnoise_pwdB   0xffff
 
#define bPowerMeasTLength   10
 
#define bPowerMeasFLength   3
 
#define bRx_HT_BW   0x1
 
#define bRxSC   0x6
 
#define bRx_HT   0x8
 
#define bNB_intf_det_on   0x1
 
#define bIntf_win_len_cfg   0x30
 
#define bNB_Intf_TH_cfg   0x1c0
 
#define bRFGain   0x3f
 
#define bTableSel   0x40
 
#define bTRSW   0x80
 
#define bRxSNR_A   0xff
 
#define bRxSNR_B   0xff00
 
#define bRxSNR_C   0xff0000
 
#define bRxSNR_D   0xff000000
 
#define bSNREVMTLength   8
 
#define bSNREVMFLength   1
 
#define bCSI1st   0xff
 
#define bCSI2nd   0xff00
 
#define bRxEVM1st   0xff0000
 
#define bRxEVM2nd   0xff000000
 
#define bSIGEVM   0xff
 
#define bPWDB   0xff00
 
#define bSGIEN   0x10000
 
#define bSFactorQAM1   0xf
 
#define bSFactorQAM2   0xf0
 
#define bSFactorQAM3   0xf00
 
#define bSFactorQAM4   0xf000
 
#define bSFactorQAM5   0xf0000
 
#define bSFactorQAM6   0xf0000
 
#define bSFactorQAM7   0xf00000
 
#define bSFactorQAM8   0xf000000
 
#define bSFactorQAM9   0xf0000000
 
#define bCSIScheme   0x100000
 
#define bNoiseLvlTopSet   0x3
 
#define bChSmooth   0x4
 
#define bChSmoothCfg1   0x38
 
#define bChSmoothCfg2   0x1c0
 
#define bChSmoothCfg3   0xe00
 
#define bChSmoothCfg4   0x7000
 
#define bMRCMode   0x800000
 
#define bTHEVMCfg   0x7000000
 
#define bLoopFitType   0x1
 
#define bUpdCFO   0x40
 
#define bUpdCFOOffData   0x80
 
#define bAdvUpdCFO   0x100
 
#define bAdvTimeCtrl   0x800
 
#define bUpdClko   0x1000
 
#define bFC   0x6000
 
#define bTrackingMode   0x8000
 
#define bPhCmpEnable   0x10000
 
#define bUpdClkoLTF   0x20000
 
#define bComChCFO   0x40000
 
#define bCSIEstiMode   0x80000
 
#define bAdvUpdEqz   0x100000
 
#define bUChCfg   0x7000000
 
#define bUpdEqz   0x8000000
 
#define bTxAGCRate18_06   0x7f7f7f7f
 
#define bTxAGCRate54_24   0x7f7f7f7f
 
#define bTxAGCRateMCS32   0x7f
 
#define bTxAGCRateCCK   0x7f00
 
#define bTxAGCRateMCS3_MCS0   0x7f7f7f7f
 
#define bTxAGCRateMCS7_MCS4   0x7f7f7f7f
 
#define bTxAGCRateMCS11_MCS8   0x7f7f7f7f
 
#define bTxAGCRateMCS15_MCS12   0x7f7f7f7f
 
#define bRxPesudoNoiseOn   0x20000000
 
#define bRxPesudoNoise_A   0xff
 
#define bRxPesudoNoise_B   0xff00
 
#define bRxPesudoNoise_C   0xff0000
 
#define bRxPesudoNoise_D   0xff000000
 
#define bPesudoNoiseState_A   0xffff
 
#define bPesudoNoiseState_B   0xffff0000
 
#define bPesudoNoiseState_C   0xffff
 
#define bPesudoNoiseState_D   0xffff0000
 
#define bZebra1_HSSIEnable   0x8
 
#define bZebra1_TRxControl   0xc00
 
#define bZebra1_TRxGainSetting   0x07f
 
#define bZebra1_RxCorner   0xc00
 
#define bZebra1_TxChargePump   0x38
 
#define bZebra1_RxChargePump   0x7
 
#define bZebra1_ChannelNum   0xf80
 
#define bZebra1_TxLPFBW   0x400
 
#define bZebra1_RxLPFBW   0x600
 
#define bRTL8256RegModeCtrl1   0x100
 
#define bRTL8256RegModeCtrl0   0x40
 
#define bRTL8256_TxLPFBW   0x18
 
#define bRTL8256_RxLPFBW   0x600
 
#define bRTL8258_TxLPFBW   0xc
 
#define bRTL8258_RxLPFBW   0xc00
 
#define bRTL8258_RSSILPFBW   0xc0
 
#define bByte0   0x1
 
#define bByte1   0x2
 
#define bByte2   0x4
 
#define bByte3   0x8
 
#define bWord0   0x3
 
#define bWord1   0xc
 
#define bDWord   0xf
 
#define bMaskByte0   0xff
 
#define bMaskByte1   0xff00
 
#define bMaskByte2   0xff0000
 
#define bMaskByte3   0xff000000
 
#define bMaskHWord   0xffff0000
 
#define bMaskLWord   0x0000ffff
 
#define bMaskDWord   0xffffffff
 
#define bMask12Bits   0xfff
 
#define bEnable   0x1
 
#define bDisable   0x0
 
#define LeftAntenna   0x0
 
#define RightAntenna   0x1
 
#define tCheckTxStatus   500
 
#define tUpdateRxCounter   100
 
#define rateCCK   0
 
#define rateOFDM   1
 
#define rateHT   2
 
#define bPMAC_End   0x1ff
 
#define bFPGAPHY0_End   0x8ff
 
#define bFPGAPHY1_End   0x9ff
 
#define bCCKPHY0_End   0xaff
 
#define bOFDMPHY0_End   0xcff
 
#define bOFDMPHY1_End   0xdff
 
#define bPMACControl   0x0
 
#define bWMACControl   0x1
 
#define bWNICControl   0x2
 
#define PathA   0x0
 
#define PathB   0x1
 
#define PathC   0x2
 
#define PathD   0x3
 
#define rRTL8256RxMixerPole   0xb
 
#define bZebraRxMixerPole   0x6
 
#define rRTL8256TxBBOPBias   0x9
 
#define bRTL8256TxBBOPBias   0x400
 
#define rRTL8256TxBBBW   19
 
#define bRTL8256TxBBBW   0x18
 

Macro Definition Documentation

#define b2GPAPEPolarity   0x80000000

Definition at line 312 of file r8192E_phyreg.h.

#define b3WireAddressLength   0x400

Definition at line 309 of file r8192E_phyreg.h.

#define b3WireDataLength   0x800

Definition at line 308 of file r8192E_phyreg.h.

#define b3WireRFPowerDown   0x1

Definition at line 310 of file r8192E_phyreg.h.

#define b40MDClkPowerUP   0x8000

Definition at line 361 of file r8192E_phyreg.h.

#define b5GPAPEPolarity   0x40000000

Definition at line 311 of file r8192E_phyreg.h.

#define b80MClkDelay   0x18000000

Definition at line 365 of file r8192E_phyreg.h.

#define bAD11InputRange   0x700000

Definition at line 375 of file r8192E_phyreg.h.

#define bAD11OPCurrent   0x3800000

Definition at line 376 of file r8192E_phyreg.h.

#define bAD11PowerUpAtRx   0x100

Definition at line 391 of file r8192E_phyreg.h.

#define bAD11PowerUpAtTx   0x1

Definition at line 389 of file r8192E_phyreg.h.

#define bAD11SHGain   0xc0000

Definition at line 374 of file r8192E_phyreg.h.

#define bAD7Current   0xc00000

Definition at line 387 of file r8192E_phyreg.h.

#define bAD7Gain   0x38000

Definition at line 384 of file r8192E_phyreg.h.

#define bAD7InputCMMode   0x380000

Definition at line 386 of file r8192E_phyreg.h.

#define bAD7InputRange   0x6000

Definition at line 383 of file r8192E_phyreg.h.

#define bAD7OutputCMMode   0x40000

Definition at line 385 of file r8192E_phyreg.h.

#define bAD7PowerUp   0x200

Definition at line 358 of file r8192E_phyreg.h.

#define bADCBackoff   0x3000

Definition at line 510 of file r8192E_phyreg.h.

#define bADClkPhase   0x4000000

Definition at line 364 of file r8192E_phyreg.h.

#define bAdvTimeCtrl   0x800

Definition at line 746 of file r8192E_phyreg.h.

#define bAdvUpdCFO   0x100

Definition at line 745 of file r8192E_phyreg.h.

#define bAdvUpdEqz   0x100000

Definition at line 754 of file r8192E_phyreg.h.

#define bAFELoopback   0x10000000

Definition at line 379 of file r8192E_phyreg.h.

#define bAFEWatchDogEnable   0x20000000

Definition at line 366 of file r8192E_phyreg.h.

#define bAGCAddress   0x3f

Definition at line 302 of file r8192E_phyreg.h.

#define bAGCRxCode   0x300000

Definition at line 307 of file r8192E_phyreg.h.

#define bAGCTxCode   0xc00000

Definition at line 306 of file r8192E_phyreg.h.

#define bAntennaMapping   0x10

Definition at line 660 of file r8192E_phyreg.h.

#define bAntHT1   0x1000

Definition at line 414 of file r8192E_phyreg.h.

#define bAntHT1S1   0x100000

Definition at line 416 of file r8192E_phyreg.h.

#define bAntHT2   0x10000

Definition at line 415 of file r8192E_phyreg.h.

#define bAntL   0x10

Definition at line 412 of file r8192E_phyreg.h.

#define bAntNonHT   0x100

Definition at line 413 of file r8192E_phyreg.h.

#define bAntNonHTS1   0x1000000

Definition at line 417 of file r8192E_phyreg.h.

#define bBandgapMbiasPowerUp   0x10000

Definition at line 373 of file r8192E_phyreg.h.

#define bBandSelect   0x1

Definition at line 329 of file r8192E_phyreg.h.

#define bBBCCKStart   0x0000000f

Definition at line 292 of file r8192E_phyreg.h.

#define bBBResetB   0x100

Definition at line 232 of file r8192E_phyreg.h.

#define bBBStart   0x000000f0

Definition at line 291 of file r8192E_phyreg.h.

#define bBW_option   0x4000000

Definition at line 533 of file r8192E_phyreg.h.

#define bBW_Search_L   0x30000

Definition at line 529 of file r8192E_phyreg.h.

#define bBW_TH   0x700000

Definition at line 531 of file r8192E_phyreg.h.

#define bByte0   0x1

Definition at line 797 of file r8192E_phyreg.h.

#define bByte1   0x2

Definition at line 798 of file r8192E_phyreg.h.

#define bByte2   0x4

Definition at line 799 of file r8192E_phyreg.h.

#define bByte3   0x8

Definition at line 800 of file r8192E_phyreg.h.

#define bCC_power_dB   0xffff0000

Definition at line 690 of file r8192E_phyreg.h.

#define bCCADropOption   0x20000

Definition at line 569 of file r8192E_phyreg.h.

#define bCCADropThres   0xfff00000

Definition at line 570 of file r8192E_phyreg.h.

#define bCCAMask   0x000000f0

Definition at line 296 of file r8192E_phyreg.h.

#define bCCKAntDiversity   0x8000

Definition at line 424 of file r8192E_phyreg.h.

#define bCCKAntennaPolarity   0x2000

Definition at line 458 of file r8192E_phyreg.h.

#define bCCKBBMode   0x3

Definition at line 419 of file r8192E_phyreg.h.

#define bCCKBistMode   0x80000000

Definition at line 436 of file r8192E_phyreg.h.

#define bCCKCarrierRecovery   0x4000

Definition at line 425 of file r8192E_phyreg.h.

#define bCCKCCACount   0x080000

Definition at line 434 of file r8192E_phyreg.h.

#define bCCKCCAMask   0x40000000

Definition at line 437 of file r8192E_phyreg.h.

#define bCCKCCAMode   0xc000

Definition at line 443 of file r8192E_phyreg.h.

#define bCCKChEstStart   0x300000

Definition at line 433 of file r8192E_phyreg.h.

#define bCCKCorgBit_sel   0x300000

Definition at line 446 of file r8192E_phyreg.h.

#define bCCKcs_lim   0x070000

Definition at line 435 of file r8192E_phyreg.h.

#define bCCKCS_ratio   0xc00000

Definition at line 445 of file r8192E_phyreg.h.

#define bCCKDACDebug   0x0f000000

Definition at line 474 of file r8192E_phyreg.h.

#define bCCKDCCancel   0x0800

Definition at line 427 of file r8192E_phyreg.h.

#define bCCKDebugPort   0xff0000

Definition at line 473 of file r8192E_phyreg.h.

#define bCCKDefaultRxPath   0xc000000

Definition at line 495 of file r8192E_phyreg.h.

#define bCCKEn   0x1000000

Definition at line 280 of file r8192E_phyreg.h.

#define bCCKEqualizer   0x0100

Definition at line 430 of file r8192E_phyreg.h.

#define bCCKFACounterFreeze   0x4000

Definition at line 492 of file r8192E_phyreg.h.

#define bCCKFalseAlarmEnable   0x8000

Definition at line 475 of file r8192E_phyreg.h.

#define bCCKFalseAlarmRead   0x4000

Definition at line 476 of file r8192E_phyreg.h.

#define bCCKFalseCS_lim   0x3f00

Definition at line 444 of file r8192E_phyreg.h.

#define bCCKFastFalseCCA   0x400000

Definition at line 432 of file r8192E_phyreg.h.

#define bCCKFixedRxAGC   0x8000

Definition at line 457 of file r8192E_phyreg.h.

#define bCCKISICancel   0x0400

Definition at line 428 of file r8192E_phyreg.h.

#define bCCKLengthExt   0x8000

Definition at line 271 of file r8192E_phyreg.h.

#define bCCKLNAPolarity   0x800000

Definition at line 451 of file r8192E_phyreg.h.

#define bCCKMatchFilter   0x0200

Definition at line 429 of file r8192E_phyreg.h.

#define bCCKNewCCA   0x80000000

Definition at line 448 of file r8192E_phyreg.h.

#define bCCKOptionRxPath   0x3000000

Definition at line 496 of file r8192E_phyreg.h.

#define bCCKPD_lim   0x0f0000

Definition at line 447 of file r8192E_phyreg.h.

#define bCCKPHY0_End   0xaff

Definition at line 831 of file r8192E_phyreg.h.

#define bCCKPreambleDetect   0x800000

Definition at line 431 of file r8192E_phyreg.h.

#define bCCKr_cp_mode0   0x0100

Definition at line 440 of file r8192E_phyreg.h.

#define bCCKRFExtend   0x20000000

Definition at line 453 of file r8192E_phyreg.h.

#define bCCKRx1stGain   0x7f0000

Definition at line 452 of file r8192E_phyreg.h.

#define bCCKRxADCPhase   0x20000000

Definition at line 439 of file r8192E_phyreg.h.

#define bCCKRxAGCFormat   0x200

Definition at line 394 of file r8192E_phyreg.h.

#define bCCKRxAGCReport   0xfe

Definition at line 478 of file r8192E_phyreg.h.

#define bCCKRxAGCReportType   0x0300

Definition at line 460 of file r8192E_phyreg.h.

#define bCCKRxAGCSatCount   0xe0

Definition at line 455 of file r8192E_phyreg.h.

#define bCCKRxAGCSatLevel   0x1f000000

Definition at line 454 of file r8192E_phyreg.h.

#define bCCKRxDAGCEn   0x80000000

Definition at line 461 of file r8192E_phyreg.h.

#define bCCKRxDAGCPeriod   0x20000000

Definition at line 462 of file r8192E_phyreg.h.

#define bCCKRxDAGCSatLevel   0x1f000000

Definition at line 463 of file r8192E_phyreg.h.

#define bCCKRxDCOffset   0xf

Definition at line 442 of file r8192E_phyreg.h.

#define bCCKRxFACounterLower   0xff

Definition at line 486 of file r8192E_phyreg.h.

#define bCCKRxFACounterUpper   0xff000000

Definition at line 487 of file r8192E_phyreg.h.

#define bCCKRxFalseAlarmEnable   0x8000

Definition at line 491 of file r8192E_phyreg.h.

#define bCCKRxHPAGCFinal   0x1c00

Definition at line 489 of file r8192E_phyreg.h.

#define bCCKRxHPAGCStart   0xe000

Definition at line 488 of file r8192E_phyreg.h.

#define bCCKRxHPofIG   0x8000

Definition at line 449 of file r8192E_phyreg.h.

#define bCCKRxIG   0x7f00

Definition at line 450 of file r8192E_phyreg.h.

#define bCCKRxPhase   0x4

Definition at line 345 of file r8192E_phyreg.h.

#define bCCKRxPowerSaving   0x40

Definition at line 421 of file r8192E_phyreg.h.

#define bCCKRxReport_AntSel   0x80000000

Definition at line 479 of file r8192E_phyreg.h.

#define bCCKRxReport_Lockedbit   0x08000000

Definition at line 483 of file r8192E_phyreg.h.

#define bCCKRxReport_MFOff   0x40000000

Definition at line 480 of file r8192E_phyreg.h.

#define bCCKRxReport_Pktloss   0x10000000

Definition at line 482 of file r8192E_phyreg.h.

#define bCCKRxReport_RateError   0x04000000

Definition at line 484 of file r8192E_phyreg.h.

#define bCCKRxReport_RxRate   0x03000000

Definition at line 485 of file r8192E_phyreg.h.

#define bCCKRxRFSettle   0x1f

Definition at line 456 of file r8192E_phyreg.h.

#define bCCKRxRxReport_SQLoss   0x20000000

Definition at line 481 of file r8192E_phyreg.h.

#define bCCKSampleRate   0x8

Definition at line 350 of file r8192E_phyreg.h.

#define bCCKScramble   0x8

Definition at line 423 of file r8192E_phyreg.h.

#define bCCKSideBand   0x10

Definition at line 422 of file r8192E_phyreg.h.

#define bCCKTimingRecovery   0x800000

Definition at line 464 of file r8192E_phyreg.h.

#define bCCKTRSSI   0x7f

Definition at line 477 of file r8192E_phyreg.h.

#define bCCKTxC0   0x3f0000

Definition at line 465 of file r8192E_phyreg.h.

#define bCCKTxC1   0x3f000000

Definition at line 466 of file r8192E_phyreg.h.

#define bCCKTxC2   0x3f

Definition at line 467 of file r8192E_phyreg.h.

#define bCCKTxC3   0x3f00

Definition at line 468 of file r8192E_phyreg.h.

#define bCCKTxC4   0x3f0000

Definition at line 469 of file r8192E_phyreg.h.

#define bCCKTxC5   0x3f000000

Definition at line 470 of file r8192E_phyreg.h.

#define bCCKTxC6   0x3f

Definition at line 471 of file r8192E_phyreg.h.

#define bCCKTxC7   0x3f00

Definition at line 472 of file r8192E_phyreg.h.

#define bCCKTxCRC16   0xffff

Definition at line 273 of file r8192E_phyreg.h.

#define bCCKTxDACPhase   0x4

Definition at line 438 of file r8192E_phyreg.h.

#define bCCKTxDCOffset   0xf0

Definition at line 441 of file r8192E_phyreg.h.

#define bCCKTxFilterType   0x0c00

Definition at line 459 of file r8192E_phyreg.h.

#define bCCKTxLength   0xffff0000

Definition at line 272 of file r8192E_phyreg.h.

#define bCCKTxOn   0x1

Definition at line 408 of file r8192E_phyreg.h.

#define bCCKTxPathSel   0x10000000

Definition at line 494 of file r8192E_phyreg.h.

#define bCCKTxPowerSaving   0x80

Definition at line 420 of file r8192E_phyreg.h.

#define bCCKTxPreamble   0x1

Definition at line 267 of file r8192E_phyreg.h.

#define bCCKTxRate   0x3000

Definition at line 426 of file r8192E_phyreg.h.

#define bCCKTxSC   0x30

Definition at line 279 of file r8192E_phyreg.h.

#define bCCKTxService   0xff00

Definition at line 270 of file r8192E_phyreg.h.

#define bCCKTxSFD   0xffff0000

Definition at line 268 of file r8192E_phyreg.h.

#define bCCKTxSIG   0xff

Definition at line 269 of file r8192E_phyreg.h.

#define bCCKTxStart   0x8

Definition at line 235 of file r8192E_phyreg.h.

#define bCCKTxStatus   0x1

Definition at line 274 of file r8192E_phyreg.h.

#define bCFOAcc   0x2

Definition at line 552 of file r8192E_phyreg.h.

#define bCFOAntSum   0x1

Definition at line 551 of file r8192E_phyreg.h.

#define bCFOAntSumD   0x200

Definition at line 662 of file r8192E_phyreg.h.

#define bCFOEn   0x10000

Definition at line 669 of file r8192E_phyreg.h.

#define bCFOLookBack   0x70

Definition at line 554 of file r8192E_phyreg.h.

#define bCFOReportGet   0x4000000

Definition at line 664 of file r8192E_phyreg.h.

#define bCFOStartOffset   0xc

Definition at line 553 of file r8192E_phyreg.h.

#define bCFOSumWeight   0x80

Definition at line 555 of file r8192E_phyreg.h.

#define bCFOValue   0xfff00000

Definition at line 670 of file r8192E_phyreg.h.

#define bChSmooth   0x4

Definition at line 734 of file r8192E_phyreg.h.

#define bChSmoothCfg1   0x38

Definition at line 735 of file r8192E_phyreg.h.

#define bChSmoothCfg2   0x1c0

Definition at line 736 of file r8192E_phyreg.h.

#define bChSmoothCfg3   0xe00

Definition at line 737 of file r8192E_phyreg.h.

#define bChSmoothCfg4   0x7000

Definition at line 738 of file r8192E_phyreg.h.

#define bComChCFO   0x40000

Definition at line 752 of file r8192E_phyreg.h.

#define bContTxHSSI   0x400

Definition at line 300 of file r8192E_phyreg.h.

#define bCounter_CCA   0xffff

Definition at line 673 of file r8192E_phyreg.h.

#define bCounter_CRC8Fail   0xffff0000

Definition at line 676 of file r8192E_phyreg.h.

#define bCounter_FastSync   0xffff

Definition at line 678 of file r8192E_phyreg.h.

#define bCounter_MCSNoSupport   0xffff

Definition at line 677 of file r8192E_phyreg.h.

#define bCounter_ParityFail   0xffff0000

Definition at line 674 of file r8192E_phyreg.h.

#define bCounter_RateIllegal   0xffff

Definition at line 675 of file r8192E_phyreg.h.

#define bCounterReset   0x10000

Definition at line 257 of file r8192E_phyreg.h.

#define bCRC32Debug   0x100

Definition at line 236 of file r8192E_phyreg.h.

#define bCSI1st   0xff

Definition at line 713 of file r8192E_phyreg.h.

#define bCSI2nd   0xff00

Definition at line 714 of file r8192E_phyreg.h.

#define bCSIEstiMode   0x80000

Definition at line 753 of file r8192E_phyreg.h.

#define bCSIScheme   0x100000

Definition at line 731 of file r8192E_phyreg.h.

#define bDA10PowerUp   0x20

Definition at line 357 of file r8192E_phyreg.h.

#define bDA10PSAtRx   0x1000

Definition at line 392 of file r8192E_phyreg.h.

#define bDA10PSAtTx   0x10

Definition at line 390 of file r8192E_phyreg.h.

#define bDA10Reverse   0x800

Definition at line 381 of file r8192E_phyreg.h.

#define bDA10Swing   0x7e0

Definition at line 380 of file r8192E_phyreg.h.

#define bDA6DebugMode   0x20000

Definition at line 362 of file r8192E_phyreg.h.

#define bDA6PowerUp   0x2000

Definition at line 359 of file r8192E_phyreg.h.

#define bDA6Swing   0x380000

Definition at line 363 of file r8192E_phyreg.h.

#define bDAClkSource   0x1000

Definition at line 382 of file r8192E_phyreg.h.

#define bDAFormat   0x40000

Definition at line 648 of file r8192E_phyreg.h.

#define bDAGCEnable   0x10000

Definition at line 556 of file r8192E_phyreg.h.

#define bDC_dc_Notch   0x60000

Definition at line 521 of file r8192E_phyreg.h.

#define bDC_Slope_check   0x80

Definition at line 539 of file r8192E_phyreg.h.

#define bDebugItem   0xff

Definition at line 411 of file r8192E_phyreg.h.

#define bDebugPage   0xfff

Definition at line 410 of file r8192E_phyreg.h.

#define bDFIRBackoff   0xc000

Definition at line 511 of file r8192E_phyreg.h.

#define bDFSCnt0   0xff

Definition at line 641 of file r8192E_phyreg.h.

#define bDFSCnt1   0xff00

Definition at line 642 of file r8192E_phyreg.h.

#define bDFSFlag   0xf0000

Definition at line 643 of file r8192E_phyreg.h.

#define bDisable   0x0

Definition at line 816 of file r8192E_phyreg.h.

#define bDPLLPowerUp   0x10

Definition at line 356 of file r8192E_phyreg.h.

#define bDWord   0xf

Definition at line 803 of file r8192E_phyreg.h.

#define bED_TH2   0x3800000

Definition at line 532 of file r8192E_phyreg.h.

#define bEDCCA_H   0xf

Definition at line 571 of file r8192E_phyreg.h.

#define bEDCCA_L   0xf0

Definition at line 572 of file r8192E_phyreg.h.

#define bEnable   0x1

Definition at line 815 of file r8192E_phyreg.h.

#define bExtLNAGain   0x7c00

Definition at line 657 of file r8192E_phyreg.h.

#define bExtSigClkEnable   0x800

Definition at line 372 of file r8192E_phyreg.h.

#define bFC   0x6000

Definition at line 748 of file r8192E_phyreg.h.

#define bFGuard_Counter_DC_L   0xe00

Definition at line 540 of file r8192E_phyreg.h.

#define bFPGAPHY0_End   0x8ff

Definition at line 829 of file r8192E_phyreg.h.

#define bFPGAPHY1_End   0x9ff

Definition at line 830 of file r8192E_phyreg.h.

#define bFrame_DC_Length   0xe000000

Definition at line 543 of file r8192E_phyreg.h.

#define bFrame_GI2_TH   0x38

Definition at line 546 of file r8192E_phyreg.h.

#define bFrame_TH   0x1c

Definition at line 537 of file r8192E_phyreg.h.

#define bFrame_TH_2   0x7

Definition at line 545 of file r8192E_phyreg.h.

#define bFrame_Weight_Short   0x7000

Definition at line 541 of file r8192E_phyreg.h.

#define bFS_Option   0x60

Definition at line 538 of file r8192E_phyreg.h.

#define bGI2_Sync_en   0x40

Definition at line 547 of file r8192E_phyreg.h.

#define bGI_TH   0xc

Definition at line 500 of file r8192E_phyreg.h.

#define bGlobalResetB   0x200

Definition at line 233 of file r8192E_phyreg.h.

#define bHSSI_R2TDelay   0xf8000000

Definition at line 298 of file r8192E_phyreg.h.

#define bHSSI_T2RDelay   0xf80000

Definition at line 299 of file r8192E_phyreg.h.

#define bHTDetect   0x100

Definition at line 668 of file r8192E_phyreg.h.

#define bHTSIG1_BandWidth   0x80

Definition at line 339 of file r8192E_phyreg.h.

#define bHTSIG1_HTLength   0xffff

Definition at line 340 of file r8192E_phyreg.h.

#define bHTSIG1_MCS   0x7f

Definition at line 338 of file r8192E_phyreg.h.

#define bHTSIG2_AdvCoding   0x40

Definition at line 335 of file r8192E_phyreg.h.

#define bHTSIG2_Aggreaton   0x08

Definition at line 333 of file r8192E_phyreg.h.

#define bHTSIG2_CRC8   0x3fc

Definition at line 337 of file r8192E_phyreg.h.

#define bHTSIG2_GI   0x80

Definition at line 330 of file r8192E_phyreg.h.

#define bHTSIG2_NumOfHTLTF   0x300

Definition at line 336 of file r8192E_phyreg.h.

#define bHTSIG2_Smoothing   0x01

Definition at line 331 of file r8192E_phyreg.h.

#define bHTSIG2_Sounding   0x02

Definition at line 332 of file r8192E_phyreg.h.

#define bHTSIG2_STBC   0x30

Definition at line 334 of file r8192E_phyreg.h.

#define bIfMF_Win_L   0x800

Definition at line 526 of file r8192E_phyreg.h.

#define bIGFromCCK   0x200

Definition at line 301 of file r8192E_phyreg.h.

#define bIntDifClkEnable   0x400

Definition at line 371 of file r8192E_phyreg.h.

#define bIntf_win_len_cfg   0x30

Definition at line 699 of file r8192E_phyreg.h.

#define bIPathLoopback   0x4000000

Definition at line 377 of file r8192E_phyreg.h.

#define bIQPathControl   0xc00

Definition at line 398 of file r8192E_phyreg.h.

#define bJapanMode   0x2

Definition at line 278 of file r8192E_phyreg.h.

#define bLambda_ED   0x300

Definition at line 573 of file r8192E_phyreg.h.

#define bLongCFO   0x7ff

Definition at line 682 of file r8192E_phyreg.h.

#define bLongCFOFLength   11

Definition at line 684 of file r8192E_phyreg.h.

#define bLongCFOTLength   11

Definition at line 683 of file r8192E_phyreg.h.

#define bLoopFitType   0x1

Definition at line 742 of file r8192E_phyreg.h.

#define bLSIG_Length   0x1fffe

Definition at line 343 of file r8192E_phyreg.h.

#define bLSIG_Parity   0x20

Definition at line 344 of file r8192E_phyreg.h.

#define bLSIG_Rate   0xf

Definition at line 341 of file r8192E_phyreg.h.

#define bLSIG_Reserved   0x10

Definition at line 342 of file r8192E_phyreg.h.

#define bLSSIReadAddress   0x3f000000

Definition at line 346 of file r8192E_phyreg.h.

#define bLSSIReadBackData   0xfff

Definition at line 348 of file r8192E_phyreg.h.

#define bLSSIReadEdge   0x80000000

Definition at line 347 of file r8192E_phyreg.h.

#define bLSSIReadOKFlag   0x1000

Definition at line 349 of file r8192E_phyreg.h.

#define bMask12Bits   0xfff

Definition at line 813 of file r8192E_phyreg.h.

#define bMaskByte0   0xff

Definition at line 805 of file r8192E_phyreg.h.

#define bMaskByte1   0xff00

Definition at line 806 of file r8192E_phyreg.h.

#define bMaskByte2   0xff0000

Definition at line 807 of file r8192E_phyreg.h.

#define bMaskByte3   0xff000000

Definition at line 808 of file r8192E_phyreg.h.

#define bMaskDWord   0xffffffff

Definition at line 811 of file r8192E_phyreg.h.

#define bMaskHWord   0xffff0000

Definition at line 809 of file r8192E_phyreg.h.

#define bMaskLWord   0x0000ffff

Definition at line 810 of file r8192E_phyreg.h.

#define bmax_en_pwdB   0xffff

Definition at line 689 of file r8192E_phyreg.h.

#define bMF_Win_L   0xe000

Definition at line 528 of file r8192E_phyreg.h.

#define bMFWeightSum   0x300000

Definition at line 645 of file r8192E_phyreg.h.

#define bMinIdxTH   0x7f000000

Definition at line 646 of file r8192E_phyreg.h.

#define bMRCMode   0x800000

Definition at line 739 of file r8192E_phyreg.h.

#define bNB_intf_det_on   0x1

Definition at line 698 of file r8192E_phyreg.h.

#define bNB_Intf_TH_cfg   0x1c0

Definition at line 700 of file r8192E_phyreg.h.

#define bnoise_pwdB   0xffff

Definition at line 691 of file r8192E_phyreg.h.

#define bNoiseLvlTopSet   0x3

Definition at line 733 of file r8192E_phyreg.h.

#define bNss   0x20

Definition at line 661 of file r8192E_phyreg.h.

#define bNumOfCCKTx   0xffff0000

Definition at line 259 of file r8192E_phyreg.h.

#define bNumOfOFDMTx   0xffff

Definition at line 258 of file r8192E_phyreg.h.

#define bNumOfSTF   0x3

Definition at line 498 of file r8192E_phyreg.h.

#define bOFDMContinueTx   0x10000000

Definition at line 665 of file r8192E_phyreg.h.

#define bOFDMEn   0x2000000

Definition at line 281 of file r8192E_phyreg.h.

#define bOFDMPHY0_End   0xcff

Definition at line 832 of file r8192E_phyreg.h.

#define bOFDMPHY1_End   0xdff

Definition at line 833 of file r8192E_phyreg.h.

#define bOFDMRxADCPhase   0x10000

Definition at line 282 of file r8192E_phyreg.h.

#define bOFDMService   0xffff0000

Definition at line 261 of file r8192E_phyreg.h.

#define bOFDMSingleCarrier   0x20000000

Definition at line 666 of file r8192E_phyreg.h.

#define bOFDMSingleTone   0x40000000

Definition at line 667 of file r8192E_phyreg.h.

#define bOFDMTxDACPhase   0x40000

Definition at line 283 of file r8192E_phyreg.h.

#define bOFDMTxLength   0x1ffe0

Definition at line 241 of file r8192E_phyreg.h.

#define bOFDMTxOn   0x2

Definition at line 409 of file r8192E_phyreg.h.

#define bOFDMTxParity   0x20000

Definition at line 242 of file r8192E_phyreg.h.

#define bOFDMTxRate   0xf

Definition at line 239 of file r8192E_phyreg.h.

#define bOFDMTxReserved   0x10

Definition at line 240 of file r8192E_phyreg.h.

#define bOFDMTxSC   0x30000000

Definition at line 407 of file r8192E_phyreg.h.

#define bOFDMTxStart   0x4

Definition at line 234 of file r8192E_phyreg.h.

#define bOFDMTxStatus   0x2

Definition at line 275 of file r8192E_phyreg.h.

#define bPAEnd   0xf

Definition at line 293 of file r8192E_phyreg.h.

#define bPAStart   0xf0000000

Definition at line 288 of file r8192E_phyreg.h.

#define bPD_Option   0x1000

Definition at line 527 of file r8192E_phyreg.h.

#define bPD_TH   0xf

Definition at line 523 of file r8192E_phyreg.h.

#define bPD_TH_Opt2   0xc000

Definition at line 524 of file r8192E_phyreg.h.

#define bPesudoNoiseState_A   0xffff

Definition at line 773 of file r8192E_phyreg.h.

#define bPesudoNoiseState_B   0xffff0000

Definition at line 774 of file r8192E_phyreg.h.

#define bPesudoNoiseState_C   0xffff

Definition at line 775 of file r8192E_phyreg.h.

#define bPesudoNoiseState_D   0xffff0000

Definition at line 776 of file r8192E_phyreg.h.

#define bPhCmpEnable   0x10000

Definition at line 750 of file r8192E_phyreg.h.

#define bPHYCounterReset   0x8000000

Definition at line 663 of file r8192E_phyreg.h.

#define bPLLPowerUp   0x8

Definition at line 355 of file r8192E_phyreg.h.

#define bPMAC_End   0x1ff

Definition at line 828 of file r8192E_phyreg.h.

#define bPMACControl   0x0

Definition at line 836 of file r8192E_phyreg.h.

#define bPMACLoopback   0x10

Definition at line 237 of file r8192E_phyreg.h.

#define bPowerMeasFLength   3

Definition at line 693 of file r8192E_phyreg.h.

#define bPowerMeasTLength   10

Definition at line 692 of file r8192E_phyreg.h.

#define bPowerThres   0x300

Definition at line 589 of file r8192E_phyreg.h.

#define bPSDAntennaPath   0x30

Definition at line 400 of file r8192E_phyreg.h.

#define bPSDAverageNum   0x3000

Definition at line 397 of file r8192E_phyreg.h.

#define bPSDFFTSamplepPoint   0xc000

Definition at line 396 of file r8192E_phyreg.h.

#define bPSDFreq   0x3ff

Definition at line 399 of file r8192E_phyreg.h.

#define bPSDIQSwitch   0x40

Definition at line 401 of file r8192E_phyreg.h.

#define bPSDReport   0xffff

Definition at line 405 of file r8192E_phyreg.h.

#define bPSDRxTrigger   0x400000

Definition at line 402 of file r8192E_phyreg.h.

#define bPSDSineToneScale   0x7f000000

Definition at line 404 of file r8192E_phyreg.h.

#define bPSDTxTrigger   0x80000000

Definition at line 403 of file r8192E_phyreg.h.

#define bPWDB   0xff00

Definition at line 719 of file r8192E_phyreg.h.

#define bPWED_TH   0x700

Definition at line 525 of file r8192E_phyreg.h.

#define bQPathLoopback   0x8000000

Definition at line 378 of file r8192E_phyreg.h.

#define bR2RCCAMask   0x00000f00

Definition at line 297 of file r8192E_phyreg.h.

#define bRatio_TH   0x18000000

Definition at line 534 of file r8192E_phyreg.h.

#define bRegulator0Standby   0x1

Definition at line 352 of file r8192E_phyreg.h.

#define bRegulator1Standby   0x4

Definition at line 354 of file r8192E_phyreg.h.

#define bRegulatorAdjust   0x7000000

Definition at line 388 of file r8192E_phyreg.h.

#define bRegulatorPLLStandby   0x2

Definition at line 353 of file r8192E_phyreg.h.

#define bRFEnd   0x000f0000

Definition at line 295 of file r8192E_phyreg.h.

#define bRFGain   0x3f

Definition at line 702 of file r8192E_phyreg.h.

#define bRFMOD   0x1

Definition at line 277 of file r8192E_phyreg.h.

#define bRFSI_3Wire   0xf

Definition at line 321 of file r8192E_phyreg.h.

#define bRFSI_3WireClock   0x2

Definition at line 318 of file r8192E_phyreg.h.

#define bRFSI_3WireData   0x1

Definition at line 317 of file r8192E_phyreg.h.

#define bRFSI_3WireLoad   0x4

Definition at line 319 of file r8192E_phyreg.h.

#define bRFSI_3WireRW   0x8

Definition at line 320 of file r8192E_phyreg.h.

#define bRFSI_ANTSW   0x100

Definition at line 325 of file r8192E_phyreg.h.

#define bRFSI_ANTSWB   0x200

Definition at line 326 of file r8192E_phyreg.h.

#define bRFSI_PAPE   0x400

Definition at line 327 of file r8192E_phyreg.h.

#define bRFSI_PAPE5G   0x800

Definition at line 328 of file r8192E_phyreg.h.

#define bRFSI_RFENV   0x10

Definition at line 322 of file r8192E_phyreg.h.

#define bRFSI_TRSW   0x20

Definition at line 323 of file r8192E_phyreg.h.

#define bRFSI_TRSWB   0x40

Definition at line 324 of file r8192E_phyreg.h.

#define bRFStart   0x0000f000

Definition at line 290 of file r8192E_phyreg.h.

#define bRFSW_RxDefaultAnt   0x300

Definition at line 315 of file r8192E_phyreg.h.

#define bRFSW_RxOptionAnt   0x3000

Definition at line 316 of file r8192E_phyreg.h.

#define bRFSW_TxDefaultAnt   0x3

Definition at line 313 of file r8192E_phyreg.h.

#define bRFSW_TxOptionAnt   0x30

Definition at line 314 of file r8192E_phyreg.h.

#define bRSSI_Gen   0x7f000000

Definition at line 600 of file r8192E_phyreg.h.

#define bRSSI_H   0x7f0000

Definition at line 599 of file r8192E_phyreg.h.

#define bRSSITableSelect   0xc000000

Definition at line 612 of file r8192E_phyreg.h.

#define bRTL8256_RxLPFBW   0x600

Definition at line 791 of file r8192E_phyreg.h.

#define bRTL8256_TxLPFBW   0x18

Definition at line 790 of file r8192E_phyreg.h.

#define bRTL8256RegModeCtrl0   0x40

Definition at line 789 of file r8192E_phyreg.h.

#define bRTL8256RegModeCtrl1   0x100

Definition at line 788 of file r8192E_phyreg.h.

#define bRTL8256TxBBBW   0x18

Definition at line 850 of file r8192E_phyreg.h.

#define bRTL8256TxBBOPBias   0x400

Definition at line 848 of file r8192E_phyreg.h.

#define bRTL8258_RSSILPFBW   0xc0

Definition at line 795 of file r8192E_phyreg.h.

#define bRTL8258_RxLPFBW   0xc00

Definition at line 794 of file r8192E_phyreg.h.

#define bRTL8258_TxLPFBW   0xc

Definition at line 793 of file r8192E_phyreg.h.

#define bRx_HT   0x8

Definition at line 696 of file r8192E_phyreg.h.

#define bRx_HT_BW   0x1

Definition at line 694 of file r8192E_phyreg.h.

#define bRxAGCAddressForLNA   0x7f00

Definition at line 576 of file r8192E_phyreg.h.

#define bRxAGCEn   0x1

Definition at line 590 of file r8192E_phyreg.h.

#define bRxAGCFreezeThres   0xc0000

Definition at line 578 of file r8192E_phyreg.h.

#define bRxAGCFreezeThresMode   0x40000000

Definition at line 585 of file r8192E_phyreg.h.

#define bRxAGCMin   0x4

Definition at line 592 of file r8192E_phyreg.h.

#define bRxAGCShift   0x7f

Definition at line 587 of file r8192E_phyreg.h.

#define bRxAGCTogetherEn   0x2

Definition at line 591 of file r8192E_phyreg.h.

#define bRxAntDivEn   0x80

Definition at line 575 of file r8192E_phyreg.h.

#define bRxAntennaPowerShift   0x3000000

Definition at line 611 of file r8192E_phyreg.h.

#define bRxDCNFType   0xe000000

Definition at line 516 of file r8192E_phyreg.h.

#define bRxDFIRMode   0x1800000

Definition at line 515 of file r8192E_phyreg.h.

#define bRxEVM1st   0xff0000

Definition at line 715 of file r8192E_phyreg.h.

#define bRxEVM2nd   0xff000000

Definition at line 716 of file r8192E_phyreg.h.

#define bRxFrame_Guard_Counter_L   0x3800000

Definition at line 637 of file r8192E_phyreg.h.

#define bRxFreezeStep_AGC0   0xc000000

Definition at line 582 of file r8192E_phyreg.h.

#define bRxFreezeStep_AGC1   0x300000

Definition at line 579 of file r8192E_phyreg.h.

#define bRxFreezeStep_AGC2   0xc00000

Definition at line 580 of file r8192E_phyreg.h.

#define bRxFreezeStep_AGC3   0x3000000

Definition at line 581 of file r8192E_phyreg.h.

#define bRxHighPowerFlow   0x8000

Definition at line 577 of file r8192E_phyreg.h.

#define bRxHP_BBP1   0x7000

Definition at line 596 of file r8192E_phyreg.h.

#define bRxHP_BBP2   0x70000

Definition at line 597 of file r8192E_phyreg.h.

#define bRxHP_BBP3   0x700000

Definition at line 598 of file r8192E_phyreg.h.

#define bRxHP_Final   0x7000000

Definition at line 613 of file r8192E_phyreg.h.

#define bRxHP_Ini   0x7

Definition at line 593 of file r8192E_phyreg.h.

#define bRxHP_RSSI   0x700

Definition at line 595 of file r8192E_phyreg.h.

#define bRxHP_TRLNA   0x70

Definition at line 594 of file r8192E_phyreg.h.

#define bRxHPCCKIni   0xc0000

Definition at line 305 of file r8192E_phyreg.h.

#define bRxHPT2R   0x38000

Definition at line 304 of file r8192E_phyreg.h.

#define bRxHPTx   0x7000

Definition at line 303 of file r8192E_phyreg.h.

#define bRxHTAGCEn   0x100000

Definition at line 624 of file r8192E_phyreg.h.

#define bRxHTAGCFreezeThres   0x30000

Definition at line 621 of file r8192E_phyreg.h.

#define bRxHTAGCMin   0x80000

Definition at line 623 of file r8192E_phyreg.h.

#define bRxHTAGCTogetherEn   0x40000

Definition at line 622 of file r8192E_phyreg.h.

#define bRxHTDAGCEn   0x200000

Definition at line 625 of file r8192E_phyreg.h.

#define bRxHTRxHP_BBP   0x1c00000

Definition at line 626 of file r8192E_phyreg.h.

#define bRxHTRxHP_Final   0xe0000000

Definition at line 627 of file r8192E_phyreg.h.

#define bRxHTRxHPEn   0x8000

Definition at line 620 of file r8192E_phyreg.h.

#define bRxHTSettle_BBP   0x7

Definition at line 614 of file r8192E_phyreg.h.

#define bRxHTSettle_BBPPW   0x80

Definition at line 617 of file r8192E_phyreg.h.

#define bRxHTSettle_HSSI   0x8

Definition at line 615 of file r8192E_phyreg.h.

#define bRxHTSettle_Idle   0x300

Definition at line 618 of file r8192E_phyreg.h.

#define bRxHTSettle_Reserved   0x1c00

Definition at line 619 of file r8192E_phyreg.h.

#define bRxHTSettle_RxHP   0x70

Definition at line 616 of file r8192E_phyreg.h.

#define bRxIDCOffset   0xff

Definition at line 513 of file r8192E_phyreg.h.

#define bRxInitialGain   0x7f

Definition at line 574 of file r8192E_phyreg.h.

#define bRXIQImb_A   0x3ff

Definition at line 517 of file r8192E_phyreg.h.

#define bRXIQImb_B   0xfc00

Definition at line 518 of file r8192E_phyreg.h.

#define bRXIQImb_C   0x3f0000

Definition at line 519 of file r8192E_phyreg.h.

#define bRXIQImb_D   0xffc00000

Definition at line 520 of file r8192E_phyreg.h.

#define bRxMFHold   0x3800

Definition at line 630 of file r8192E_phyreg.h.

#define bRxNBINotch   0x1f000000

Definition at line 522 of file r8192E_phyreg.h.

#define bRxOverFlowCheckType   0x80000000

Definition at line 586 of file r8192E_phyreg.h.

#define bRxPathA   0x1

Definition at line 501 of file r8192E_phyreg.h.

#define bRxPathB   0x2

Definition at line 502 of file r8192E_phyreg.h.

#define bRxPathC   0x4

Definition at line 503 of file r8192E_phyreg.h.

#define bRxPathD   0x8

Definition at line 504 of file r8192E_phyreg.h.

#define bRxPD_DC_COUNT_MAX   0x600

Definition at line 633 of file r8192E_phyreg.h.

#define bRxPD_Delay_TH   0x8000

Definition at line 634 of file r8192E_phyreg.h.

#define bRxPD_Delay_TH1   0x38

Definition at line 631 of file r8192E_phyreg.h.

#define bRxPD_Delay_TH2   0x1c0

Definition at line 632 of file r8192E_phyreg.h.

#define bRxPesudoNoise_A   0xff

Definition at line 769 of file r8192E_phyreg.h.

#define bRxPesudoNoise_B   0xff00

Definition at line 770 of file r8192E_phyreg.h.

#define bRxPesudoNoise_C   0xff0000

Definition at line 771 of file r8192E_phyreg.h.

#define bRxPesudoNoise_D   0xff000000

Definition at line 772 of file r8192E_phyreg.h.

#define bRxPesudoNoiseOn   0x20000000

Definition at line 768 of file r8192E_phyreg.h.

#define bRxProcess_Delay   0xf0000

Definition at line 635 of file r8192E_phyreg.h.

#define bRxProcessTime_BBPPW   0x800000

Definition at line 610 of file r8192E_phyreg.h.

#define bRxProcessTime_DAGC   0x300000

Definition at line 608 of file r8192E_phyreg.h.

#define bRxPWRatioEn   0x4

Definition at line 629 of file r8192E_phyreg.h.

#define bRxPWRatioTH   0x3

Definition at line 628 of file r8192E_phyreg.h.

#define bRxQDCOffset   0xff00

Definition at line 514 of file r8192E_phyreg.h.

#define bRxQuickAGCEn   0x20000000

Definition at line 584 of file r8192E_phyreg.h.

#define bRxRssi_Cmp_En   0x10000000

Definition at line 583 of file r8192E_phyreg.h.

#define bRxSC   0x6

Definition at line 695 of file r8192E_phyreg.h.

#define bRxSearchrange_GI2_Early   0x700000

Definition at line 636 of file r8192E_phyreg.h.

#define bRxSettle_AntSW   0xc0000

Definition at line 607 of file r8192E_phyreg.h.

#define bRxSettle_AntSW_RSSI   0x38000

Definition at line 606 of file r8192E_phyreg.h.

#define bRxSettle_BBP   0xe00

Definition at line 604 of file r8192E_phyreg.h.

#define bRxSettle_HSSI   0x400000

Definition at line 609 of file r8192E_phyreg.h.

#define bRxSettle_LNA   0x38

Definition at line 602 of file r8192E_phyreg.h.

#define bRxSettle_RSSI   0x1c0

Definition at line 603 of file r8192E_phyreg.h.

#define bRxSettle_RxHP   0x7000

Definition at line 605 of file r8192E_phyreg.h.

#define bRxSettle_TRSW   0x7

Definition at line 601 of file r8192E_phyreg.h.

#define bRxSGI_Guard_L   0xc000000

Definition at line 638 of file r8192E_phyreg.h.

#define bRxSGI_Search_L   0x30000000

Definition at line 639 of file r8192E_phyreg.h.

#define bRxSGI_TH   0xc0000000

Definition at line 640 of file r8192E_phyreg.h.

#define bRxSNR_A   0xff

Definition at line 706 of file r8192E_phyreg.h.

#define bRxSNR_B   0xff00

Definition at line 707 of file r8192E_phyreg.h.

#define bRxSNR_C   0xff0000

Definition at line 708 of file r8192E_phyreg.h.

#define bRxSNR_D   0xff000000

Definition at line 709 of file r8192E_phyreg.h.

#define bSarch_GI2_Late   0x70000

Definition at line 550 of file r8192E_phyreg.h.

#define bSarch_Short_Early   0x300

Definition at line 548 of file r8192E_phyreg.h.

#define bSarch_Short_Late   0xc00

Definition at line 549 of file r8192E_phyreg.h.

#define bSBD_Option   0x1

Definition at line 536 of file r8192E_phyreg.h.

#define bSBD_start_offset   0x30000000

Definition at line 544 of file r8192E_phyreg.h.

#define bSFactorQAM1   0xf

Definition at line 722 of file r8192E_phyreg.h.

#define bSFactorQAM2   0xf0

Definition at line 723 of file r8192E_phyreg.h.

#define bSFactorQAM3   0xf00

Definition at line 724 of file r8192E_phyreg.h.

#define bSFactorQAM4   0xf000

Definition at line 725 of file r8192E_phyreg.h.

#define bSFactorQAM5   0xf0000

Definition at line 726 of file r8192E_phyreg.h.

#define bSFactorQAM6   0xf0000

Definition at line 727 of file r8192E_phyreg.h.

#define bSFactorQAM7   0xf00000

Definition at line 728 of file r8192E_phyreg.h.

#define bSFactorQAM8   0xf000000

Definition at line 729 of file r8192E_phyreg.h.

#define bSFactorQAM9   0xf0000000

Definition at line 730 of file r8192E_phyreg.h.

#define bSGIEN   0x10000

Definition at line 720 of file r8192E_phyreg.h.

#define bShift_L   0xc0

Definition at line 499 of file r8192E_phyreg.h.

#define bShortCFO   0xfff

Definition at line 679 of file r8192E_phyreg.h.

#define bShortCFOFLength   11

Definition at line 681 of file r8192E_phyreg.h.

#define bShortCFOTLength   12

Definition at line 680 of file r8192E_phyreg.h.

#define bSIGEVM   0xff

Definition at line 718 of file r8192E_phyreg.h.

#define bSigTone_Im   0x7f00

Definition at line 672 of file r8192E_phyreg.h.

#define bSigTone_Re   0x3f

Definition at line 671 of file r8192E_phyreg.h.

#define bSNREVMFLength   1

Definition at line 711 of file r8192E_phyreg.h.

#define bSNREVMTLength   8

Definition at line 710 of file r8192E_phyreg.h.

#define bSTBCEn   0x4

Definition at line 659 of file r8192E_phyreg.h.

#define bSub_Tune   0xe00000

Definition at line 542 of file r8192E_phyreg.h.

#define bTableSel   0x40

Definition at line 703 of file r8192E_phyreg.h.

#define bTailCFO   0x1fff

Definition at line 685 of file r8192E_phyreg.h.

#define bTailCFOFLength   12

Definition at line 687 of file r8192E_phyreg.h.

#define bTailCFOTLength   13

Definition at line 686 of file r8192E_phyreg.h.

#define bTHEVMCfg   0x7000000

Definition at line 740 of file r8192E_phyreg.h.

#define bTrackingMode   0x8000

Definition at line 749 of file r8192E_phyreg.h.

#define bTREnd   0x0f000000

Definition at line 294 of file r8192E_phyreg.h.

#define bTRSSIFreq   0x200

Definition at line 509 of file r8192E_phyreg.h.

#define bTRSSILatchPhase   0x10000

Definition at line 512 of file r8192E_phyreg.h.

#define bTRStart   0x00f00000

Definition at line 289 of file r8192E_phyreg.h.

#define bTRSW   0x80

Definition at line 704 of file r8192E_phyreg.h.

#define bTRSW_Tri_Only   0x80

Definition at line 588 of file r8192E_phyreg.h.

#define bTRSWIsolation_A   0x7f

Definition at line 652 of file r8192E_phyreg.h.

#define bTRSWIsolation_B   0x7f00

Definition at line 653 of file r8192E_phyreg.h.

#define bTRSWIsolation_C   0x7f0000

Definition at line 654 of file r8192E_phyreg.h.

#define bTRSWIsolation_D   0x7f000000

Definition at line 655 of file r8192E_phyreg.h.

#define bTxAGCRate18_06   0x7f7f7f7f

Definition at line 758 of file r8192E_phyreg.h.

#define bTxAGCRate54_24   0x7f7f7f7f

Definition at line 759 of file r8192E_phyreg.h.

#define bTxAGCRateCCK   0x7f00

Definition at line 761 of file r8192E_phyreg.h.

#define bTxAGCRateMCS11_MCS8   0x7f7f7f7f

Definition at line 764 of file r8192E_phyreg.h.

#define bTxAGCRateMCS15_MCS12   0x7f7f7f7f

Definition at line 765 of file r8192E_phyreg.h.

#define bTxAGCRateMCS32   0x7f

Definition at line 760 of file r8192E_phyreg.h.

#define bTxAGCRateMCS3_MCS0   0x7f7f7f7f

Definition at line 762 of file r8192E_phyreg.h.

#define bTxAGCRateMCS7_MCS4   0x7f7f7f7f

Definition at line 763 of file r8192E_phyreg.h.

#define bTxChEmuEnable   0x01000000

Definition at line 650 of file r8192E_phyreg.h.

#define bTxDataInit   0xff

Definition at line 263 of file r8192E_phyreg.h.

#define bTxDataType   0x30000

Definition at line 265 of file r8192E_phyreg.h.

#define bTxDFIRMode   0x10000

Definition at line 563 of file r8192E_phyreg.h.

#define bTxHTAdvanceCoding   0x40

Definition at line 253 of file r8192E_phyreg.h.

#define bTxHTAggreation   0x8

Definition at line 251 of file r8192E_phyreg.h.

#define bTxHTBW   0x80

Definition at line 245 of file r8192E_phyreg.h.

#define bTxHTCRC8   0x3fc00

Definition at line 256 of file r8192E_phyreg.h.

#define bTxHTLength   0xffff00

Definition at line 246 of file r8192E_phyreg.h.

#define bTxHTMCSRate   0x7f

Definition at line 244 of file r8192E_phyreg.h.

#define bTxHTMode   0x100

Definition at line 264 of file r8192E_phyreg.h.

#define bTxHTNumberHT_LTF   0x300

Definition at line 255 of file r8192E_phyreg.h.

#define bTxHTReserved   0x4

Definition at line 250 of file r8192E_phyreg.h.

#define bTxHTShortGI   0x80

Definition at line 254 of file r8192E_phyreg.h.

#define bTxHTSIG1   0xffffff

Definition at line 243 of file r8192E_phyreg.h.

#define bTxHTSIG2   0xffffff

Definition at line 247 of file r8192E_phyreg.h.

#define bTxHTSmoothing   0x1

Definition at line 248 of file r8192E_phyreg.h.

#define bTxHTSounding   0x2

Definition at line 249 of file r8192E_phyreg.h.

#define bTxHTSTBC   0x30

Definition at line 252 of file r8192E_phyreg.h.

#define bTxIDCOffset   0xff

Definition at line 561 of file r8192E_phyreg.h.

#define bTxIdleInterval   0xffff

Definition at line 260 of file r8192E_phyreg.h.

#define bTXIQImb_A   0x3ff

Definition at line 557 of file r8192E_phyreg.h.

#define bTXIQImb_B   0xfc00

Definition at line 558 of file r8192E_phyreg.h.

#define bTXIQImb_C   0x3f0000

Definition at line 559 of file r8192E_phyreg.h.

#define bTXIQImb_D   0xffc00000

Definition at line 560 of file r8192E_phyreg.h.

#define bTxLSIG   0xffffff

Definition at line 238 of file r8192E_phyreg.h.

#define bTxMACHeader   0xffffffff

Definition at line 262 of file r8192E_phyreg.h.

#define bTxPathA   0x1

Definition at line 505 of file r8192E_phyreg.h.

#define bTxPathB   0x2

Definition at line 506 of file r8192E_phyreg.h.

#define bTxPathC   0x4

Definition at line 507 of file r8192E_phyreg.h.

#define bTxPathD   0x8

Definition at line 508 of file r8192E_phyreg.h.

#define bTxPesudoNoise_A   0xff

Definition at line 565 of file r8192E_phyreg.h.

#define bTxPesudoNoise_B   0xff00

Definition at line 566 of file r8192E_phyreg.h.

#define bTxPesudoNoise_C   0xff0000

Definition at line 567 of file r8192E_phyreg.h.

#define bTxPesudoNoise_D   0xff000000

Definition at line 568 of file r8192E_phyreg.h.

#define bTxPesudoNoiseOn   0x4000000

Definition at line 564 of file r8192E_phyreg.h.

#define bTxQDCOffset   0xff00

Definition at line 562 of file r8192E_phyreg.h.

#define bTxRandomSeed   0xffffffff

Definition at line 266 of file r8192E_phyreg.h.

#define bUChCfg   0x7000000

Definition at line 755 of file r8192E_phyreg.h.

#define bUpdCFO   0x40

Definition at line 743 of file r8192E_phyreg.h.

#define bUpdCFOOffData   0x80

Definition at line 744 of file r8192E_phyreg.h.

#define bUpdClko   0x1000

Definition at line 747 of file r8192E_phyreg.h.

#define bUpdClkoLTF   0x20000

Definition at line 751 of file r8192E_phyreg.h.

#define bUpdEqz   0x8000000

Definition at line 756 of file r8192E_phyreg.h.

#define bwin_enh_L   0xc0000

Definition at line 530 of file r8192E_phyreg.h.

#define bWindow_L   0xe0000000

Definition at line 535 of file r8192E_phyreg.h.

#define bWMACControl   0x1

Definition at line 837 of file r8192E_phyreg.h.

#define bWNICControl   0x2

Definition at line 838 of file r8192E_phyreg.h.

#define bWord0   0x3

Definition at line 801 of file r8192E_phyreg.h.

#define bWord1   0xc

Definition at line 802 of file r8192E_phyreg.h.

#define bXATxAGC   0x3f

Definition at line 284 of file r8192E_phyreg.h.

#define bXBTxAGC   0xf00

Definition at line 285 of file r8192E_phyreg.h.

#define bXCTxAGC   0xf000

Definition at line 286 of file r8192E_phyreg.h.

#define bXDTxAGC   0xf0000

Definition at line 287 of file r8192E_phyreg.h.

#define bXtalCap   0x0f000000

Definition at line 367 of file r8192E_phyreg.h.

#define bXtalCap01   0xc0000000

Definition at line 368 of file r8192E_phyreg.h.

#define bXtalCap23   0x3

Definition at line 369 of file r8192E_phyreg.h.

#define bXtalCap92x   0x0f000000

Definition at line 370 of file r8192E_phyreg.h.

#define bXtalPowerUp   0x4000

Definition at line 360 of file r8192E_phyreg.h.

#define bZebra1_ChannelNum   0xf80

Definition at line 784 of file r8192E_phyreg.h.

#define bZebra1_HSSIEnable   0x8

Definition at line 778 of file r8192E_phyreg.h.

#define bZebra1_RxChargePump   0x7

Definition at line 783 of file r8192E_phyreg.h.

#define bZebra1_RxCorner   0xc00

Definition at line 781 of file r8192E_phyreg.h.

#define bZebra1_RxLPFBW   0x600

Definition at line 786 of file r8192E_phyreg.h.

#define bZebra1_TRxControl   0xc00

Definition at line 779 of file r8192E_phyreg.h.

#define bZebra1_TRxGainSetting   0x07f

Definition at line 780 of file r8192E_phyreg.h.

#define bZebra1_TxChargePump   0x38

Definition at line 782 of file r8192E_phyreg.h.

#define bZebra1_TxLPFBW   0x400

Definition at line 785 of file r8192E_phyreg.h.

#define bZebraRxMixerPole   0x6

Definition at line 846 of file r8192E_phyreg.h.

#define CCK_TXAGC   0x348

Definition at line 54 of file r8192E_phyreg.h.

#define LeftAntenna   0x0

Definition at line 818 of file r8192E_phyreg.h.

#define MacBlkCtrl   0x403

Definition at line 57 of file r8192E_phyreg.h.

#define MCS_TXAGC   0x340

Definition at line 53 of file r8192E_phyreg.h.

#define PathA   0x0

Definition at line 840 of file r8192E_phyreg.h.

#define PathB   0x1

Definition at line 841 of file r8192E_phyreg.h.

#define PathC   0x2

Definition at line 842 of file r8192E_phyreg.h.

#define PathD   0x3

Definition at line 843 of file r8192E_phyreg.h.

#define rateCCK   0

Definition at line 824 of file r8192E_phyreg.h.

#define rateHT   2

Definition at line 826 of file r8192E_phyreg.h.

#define rateOFDM   1

Definition at line 825 of file r8192E_phyreg.h.

#define rCCK0_AFESetting   0xa04

Definition at line 107 of file r8192E_phyreg.h.

#define rCCK0_CCA   0xa08

Definition at line 108 of file r8192E_phyreg.h.

#define rCCK0_DebugPort   0xa28

Definition at line 116 of file r8192E_phyreg.h.

#define rCCK0_DSPParameter1   0xa18

Definition at line 112 of file r8192E_phyreg.h.

#define rCCK0_DSPParameter2   0xa1c

Definition at line 113 of file r8192E_phyreg.h.

#define rCCK0_FACounterLower   0xa5c

Definition at line 120 of file r8192E_phyreg.h.

#define rCCK0_FACounterUpper   0xa58

Definition at line 121 of file r8192E_phyreg.h.

#define rCCK0_FalseAlarmReport   0xa2c

Definition at line 117 of file r8192E_phyreg.h.

#define rCCK0_RxAGC1   0xa0c

Definition at line 109 of file r8192E_phyreg.h.

#define rCCK0_RxAGC2   0xa10

Definition at line 110 of file r8192E_phyreg.h.

#define rCCK0_RxHP   0xa14

Definition at line 111 of file r8192E_phyreg.h.

#define rCCK0_RxReport   0xa54

Definition at line 119 of file r8192E_phyreg.h.

#define rCCK0_System   0xa00

Definition at line 106 of file r8192E_phyreg.h.

#define rCCK0_TRSSIReport   0xa50

Definition at line 118 of file r8192E_phyreg.h.

#define rCCK0_TxFilter1   0xa20

Definition at line 114 of file r8192E_phyreg.h.

#define rCCK0_TxFilter2   0xa24

Definition at line 115 of file r8192E_phyreg.h.

#define RF_DATA   0x1d4

Definition at line 23 of file r8192E_phyreg.h.

#define rFPGA0_AnalogParameter1   0x880

Definition at line 89 of file r8192E_phyreg.h.

#define rFPGA0_AnalogParameter2   0x884

Definition at line 90 of file r8192E_phyreg.h.

#define rFPGA0_AnalogParameter3   0x888

Definition at line 91 of file r8192E_phyreg.h.

#define rFPGA0_AnalogParameter4   0x88c

Definition at line 92 of file r8192E_phyreg.h.

#define rFPGA0_PSDFunction   0x808

Definition at line 61 of file r8192E_phyreg.h.

#define rFPGA0_PSDReport   0x8b4

Definition at line 97 of file r8192E_phyreg.h.

#define rFPGA0_RFMOD   0x800

Definition at line 59 of file r8192E_phyreg.h.

#define rFPGA0_RFSleepUpParameter   0x854

Definition at line 78 of file r8192E_phyreg.h.

#define rFPGA0_RFTiming1   0x810

Definition at line 63 of file r8192E_phyreg.h.

#define rFPGA0_RFTiming2   0x814

Definition at line 64 of file r8192E_phyreg.h.

#define rFPGA0_RFWakeUpParameter   0x850

Definition at line 77 of file r8192E_phyreg.h.

#define rFPGA0_TxGainStage   0x80c

Definition at line 62 of file r8192E_phyreg.h.

#define rFPGA0_TxInfo   0x804

Definition at line 60 of file r8192E_phyreg.h.

#define rFPGA0_XA_HSSIParameter1   0x820

Definition at line 65 of file r8192E_phyreg.h.

#define rFPGA0_XA_HSSIParameter2   0x824

Definition at line 66 of file r8192E_phyreg.h.

#define rFPGA0_XA_LSSIParameter   0x840

Definition at line 73 of file r8192E_phyreg.h.

#define rFPGA0_XA_LSSIReadBack   0x8a0

Definition at line 93 of file r8192E_phyreg.h.

#define rFPGA0_XA_RFInterfaceOE   0x860

Definition at line 81 of file r8192E_phyreg.h.

#define rFPGA0_XAB_RFInterfaceRB   0x8e0

Definition at line 98 of file r8192E_phyreg.h.

#define rFPGA0_XAB_RFInterfaceSW   0x870

Definition at line 85 of file r8192E_phyreg.h.

#define rFPGA0_XAB_RFParameter   0x878

Definition at line 87 of file r8192E_phyreg.h.

#define rFPGA0_XAB_SwitchControl   0x858

Definition at line 79 of file r8192E_phyreg.h.

#define rFPGA0_XB_HSSIParameter1   0x828

Definition at line 67 of file r8192E_phyreg.h.

#define rFPGA0_XB_HSSIParameter2   0x82c

Definition at line 68 of file r8192E_phyreg.h.

#define rFPGA0_XB_LSSIParameter   0x844

Definition at line 74 of file r8192E_phyreg.h.

#define rFPGA0_XB_LSSIReadBack   0x8a4

Definition at line 94 of file r8192E_phyreg.h.

#define rFPGA0_XB_RFInterfaceOE   0x864

Definition at line 82 of file r8192E_phyreg.h.

#define rFPGA0_XC_HSSIParameter1   0x830

Definition at line 69 of file r8192E_phyreg.h.

#define rFPGA0_XC_HSSIParameter2   0x834

Definition at line 70 of file r8192E_phyreg.h.

#define rFPGA0_XC_LSSIParameter   0x848

Definition at line 75 of file r8192E_phyreg.h.

#define rFPGA0_XC_LSSIReadBack   0x8a8

Definition at line 95 of file r8192E_phyreg.h.

#define rFPGA0_XC_RFInterfaceOE   0x868

Definition at line 83 of file r8192E_phyreg.h.

#define rFPGA0_XCD_RFInterfaceRB   0x8e4

Definition at line 99 of file r8192E_phyreg.h.

#define rFPGA0_XCD_RFInterfaceSW   0x874

Definition at line 86 of file r8192E_phyreg.h.

#define rFPGA0_XCD_RFParameter   0x87c

Definition at line 88 of file r8192E_phyreg.h.

#define rFPGA0_XCD_SwitchControl   0x85c

Definition at line 80 of file r8192E_phyreg.h.

#define rFPGA0_XD_HSSIParameter1   0x838

Definition at line 71 of file r8192E_phyreg.h.

#define rFPGA0_XD_HSSIParameter2   0x83c

Definition at line 72 of file r8192E_phyreg.h.

#define rFPGA0_XD_LSSIParameter   0x84c

Definition at line 76 of file r8192E_phyreg.h.

#define rFPGA0_XD_LSSIReadBack   0x8ac

Definition at line 96 of file r8192E_phyreg.h.

#define rFPGA0_XD_RFInterfaceOE   0x86c

Definition at line 84 of file r8192E_phyreg.h.

#define rFPGA1_DebugSelect   0x908

Definition at line 103 of file r8192E_phyreg.h.

#define rFPGA1_RFMOD   0x900

Definition at line 101 of file r8192E_phyreg.h.

#define rFPGA1_TxBlock   0x904

Definition at line 102 of file r8192E_phyreg.h.

#define rFPGA1_TxInfo   0x90c

Definition at line 104 of file r8192E_phyreg.h.

#define rGlobalCtrl   0

Definition at line 224 of file r8192E_phyreg.h.

#define RightAntenna   0x1

Definition at line 819 of file r8192E_phyreg.h.

#define rOFDM0_AGCParameter1   0xc70

Definition at line 151 of file r8192E_phyreg.h.

#define rOFDM0_AGCParameter2   0xc74

Definition at line 152 of file r8192E_phyreg.h.

#define rOFDM0_AGCRSSITable   0xc78

Definition at line 153 of file r8192E_phyreg.h.

#define rOFDM0_CCADropThreshold   0xc48

Definition at line 141 of file r8192E_phyreg.h.

#define rOFDM0_CFOandDAGC   0xc44

Definition at line 140 of file r8192E_phyreg.h.

#define rOFDM0_DFSReport   0xcf4

Definition at line 166 of file r8192E_phyreg.h.

#define rOFDM0_ECCAThreshold   0xc4c

Definition at line 142 of file r8192E_phyreg.h.

#define rOFDM0_FrameSync   0xcf0

Definition at line 165 of file r8192E_phyreg.h.

#define rOFDM0_HTSTFAGC   0xc7c

Definition at line 154 of file r8192E_phyreg.h.

#define rOFDM0_LSTF   0xc00

Definition at line 123 of file r8192E_phyreg.h.

#define rOFDM0_RxDetector1   0xc30

Definition at line 135 of file r8192E_phyreg.h.

#define rOFDM0_RxDetector2   0xc34

Definition at line 136 of file r8192E_phyreg.h.

#define rOFDM0_RxDetector3   0xc38

Definition at line 137 of file r8192E_phyreg.h.

#define rOFDM0_RxDetector4   0xc3c

Definition at line 138 of file r8192E_phyreg.h.

#define rOFDM0_RxDSP   0xc40

Definition at line 139 of file r8192E_phyreg.h.

#define rOFDM0_RxHPParameter   0xce0

Definition at line 163 of file r8192E_phyreg.h.

#define rOFDM0_TRMuxPar   0xc08

Definition at line 125 of file r8192E_phyreg.h.

#define rOFDM0_TRSWIsolation   0xc0c

Definition at line 126 of file r8192E_phyreg.h.

#define rOFDM0_TRxPathEnable   0xc04

Definition at line 124 of file r8192E_phyreg.h.

#define rOFDM0_TxCoeff1   0xca4

Definition at line 167 of file r8192E_phyreg.h.

#define rOFDM0_TxCoeff2   0xca8

Definition at line 168 of file r8192E_phyreg.h.

#define rOFDM0_TxCoeff3   0xcac

Definition at line 169 of file r8192E_phyreg.h.

#define rOFDM0_TxCoeff4   0xcb0

Definition at line 170 of file r8192E_phyreg.h.

#define rOFDM0_TxCoeff5   0xcb4

Definition at line 171 of file r8192E_phyreg.h.

#define rOFDM0_TxCoeff6   0xcb8

Definition at line 172 of file r8192E_phyreg.h.

#define rOFDM0_TxPseudoNoiseWgt   0xce4

Definition at line 164 of file r8192E_phyreg.h.

#define rOFDM0_XAAGCCore1   0xc50

Definition at line 143 of file r8192E_phyreg.h.

#define rOFDM0_XAAGCCore2   0xc54

Definition at line 144 of file r8192E_phyreg.h.

#define rOFDM0_XARxAFE   0xc10

Definition at line 127 of file r8192E_phyreg.h.

#define rOFDM0_XARxIQImbalance   0xc14

Definition at line 128 of file r8192E_phyreg.h.

#define rOFDM0_XATxAFE   0xc84

Definition at line 156 of file r8192E_phyreg.h.

#define rOFDM0_XATxIQImbalance   0xc80

Definition at line 155 of file r8192E_phyreg.h.

#define rOFDM0_XBAGCCore1   0xc58

Definition at line 145 of file r8192E_phyreg.h.

#define rOFDM0_XBAGCCore2   0xc5c

Definition at line 146 of file r8192E_phyreg.h.

#define rOFDM0_XBRxAFE   0xc18

Definition at line 129 of file r8192E_phyreg.h.

#define rOFDM0_XBRxIQImbalance   0xc1c

Definition at line 130 of file r8192E_phyreg.h.

#define rOFDM0_XBTxAFE   0xc8c

Definition at line 158 of file r8192E_phyreg.h.

#define rOFDM0_XBTxIQImbalance   0xc88

Definition at line 157 of file r8192E_phyreg.h.

#define rOFDM0_XCAGCCore1   0xc60

Definition at line 147 of file r8192E_phyreg.h.

#define rOFDM0_XCAGCCore2   0xc64

Definition at line 148 of file r8192E_phyreg.h.

#define rOFDM0_XCRxAFE   0xc20

Definition at line 131 of file r8192E_phyreg.h.

#define rOFDM0_XCRxIQImbalance   0xc24

Definition at line 132 of file r8192E_phyreg.h.

#define rOFDM0_XCTxAFE   0xc94

Definition at line 160 of file r8192E_phyreg.h.

#define rOFDM0_XCTxIQImbalance   0xc90

Definition at line 159 of file r8192E_phyreg.h.

#define rOFDM0_XDAGCCore1   0xc68

Definition at line 149 of file r8192E_phyreg.h.

#define rOFDM0_XDAGCCore2   0xc6c

Definition at line 150 of file r8192E_phyreg.h.

#define rOFDM0_XDRxAFE   0xc28

Definition at line 133 of file r8192E_phyreg.h.

#define rOFDM0_XDRxIQImbalance   0xc2c

Definition at line 134 of file r8192E_phyreg.h.

#define rOFDM0_XDTxAFE   0xc9c

Definition at line 162 of file r8192E_phyreg.h.

#define rOFDM0_XDTxIQImbalance   0xc98

Definition at line 161 of file r8192E_phyreg.h.

#define rOFDM1_CFO   0xd08

Definition at line 177 of file r8192E_phyreg.h.

#define rOFDM1_CFOTracking   0xd2c

Definition at line 181 of file r8192E_phyreg.h.

#define rOFDM1_CSI1   0xd10

Definition at line 178 of file r8192E_phyreg.h.

#define rOFDM1_CSI2   0xd18

Definition at line 180 of file r8192E_phyreg.h.

#define rOFDM1_IntfDet   0xd3c

Definition at line 183 of file r8192E_phyreg.h.

#define rOFDM1_LSTF   0xd00

Definition at line 175 of file r8192E_phyreg.h.

#define rOFDM1_PseudoNoiseStateAB   0xd50

Definition at line 184 of file r8192E_phyreg.h.

#define rOFDM1_PseudoNoiseStateCD   0xd54

Definition at line 185 of file r8192E_phyreg.h.

#define rOFDM1_RxPseudoNoiseWgt   0xd58

Definition at line 186 of file r8192E_phyreg.h.

#define rOFDM1_SBD   0xd14

Definition at line 179 of file r8192E_phyreg.h.

#define rOFDM1_TRxMesaure1   0xd34

Definition at line 182 of file r8192E_phyreg.h.

#define rOFDM1_TRxPathEnable   0xd04

Definition at line 176 of file r8192E_phyreg.h.

#define rOFDM_AGCReport   0xdd0

Definition at line 199 of file r8192E_phyreg.h.

#define rOFDM_BWReport   0xdcc

Definition at line 198 of file r8192E_phyreg.h.

#define rOFDM_LongCFOAB   0xdb4

Definition at line 192 of file r8192E_phyreg.h.

#define rOFDM_LongCFOCD   0xdb8

Definition at line 193 of file r8192E_phyreg.h.

#define rOFDM_PHYCounter1   0xda0

Definition at line 187 of file r8192E_phyreg.h.

#define rOFDM_PHYCounter2   0xda4

Definition at line 188 of file r8192E_phyreg.h.

#define rOFDM_PHYCounter3   0xda8

Definition at line 189 of file r8192E_phyreg.h.

#define rOFDM_PWMeasure1   0xdc4

Definition at line 196 of file r8192E_phyreg.h.

#define rOFDM_PWMeasure2   0xdc8

Definition at line 197 of file r8192E_phyreg.h.

#define rOFDM_RxEVMCSI   0xdd8

Definition at line 201 of file r8192E_phyreg.h.

#define rOFDM_RxSNR   0xdd4

Definition at line 200 of file r8192E_phyreg.h.

#define rOFDM_ShortCFOAB   0xdac

Definition at line 190 of file r8192E_phyreg.h.

#define rOFDM_ShortCFOCD   0xdb0

Definition at line 191 of file r8192E_phyreg.h.

#define rOFDM_SIGReport   0xddc

Definition at line 202 of file r8192E_phyreg.h.

#define rOFDM_TailCFOAB   0xdbc

Definition at line 194 of file r8192E_phyreg.h.

#define rOFDM_TailCFOCD   0xdc0

Definition at line 195 of file r8192E_phyreg.h.

#define rPMAC_CCKCRC16   0x148

Definition at line 43 of file r8192E_phyreg.h.

#define rPMAC_CCKCRxRC16Er   0x180

Definition at line 48 of file r8192E_phyreg.h.

#define rPMAC_CCKCRxRC32Er   0x184

Definition at line 49 of file r8192E_phyreg.h.

#define rPMAC_CCKCRxRC32OK   0x188

Definition at line 50 of file r8192E_phyreg.h.

#define rPMAC_CCKPLCPHeader   0x144

Definition at line 42 of file r8192E_phyreg.h.

#define rPMAC_CCKPLCPPreamble   0x140

Definition at line 41 of file r8192E_phyreg.h.

#define rPMAC_OFDMRxCRC32Er   0x174

Definition at line 45 of file r8192E_phyreg.h.

#define rPMAC_OFDMRxCRC32OK   0x170

Definition at line 44 of file r8192E_phyreg.h.

#define rPMAC_OFDMRxCRC8Er   0x17c

Definition at line 47 of file r8192E_phyreg.h.

#define rPMAC_OFDMRxParityEr   0x178

Definition at line 46 of file r8192E_phyreg.h.

#define rPMAC_PHYDebug   0x114

Definition at line 30 of file r8192E_phyreg.h.

#define rPMAC_Reset   0x100

Definition at line 25 of file r8192E_phyreg.h.

#define rPMAC_TxDataType   0x138

Definition at line 39 of file r8192E_phyreg.h.

#define rPMAC_TxHTSIG1   0x10c

Definition at line 28 of file r8192E_phyreg.h.

#define rPMAC_TxHTSIG2   0x110

Definition at line 29 of file r8192E_phyreg.h.

#define rPMAC_TxIdle   0x11c

Definition at line 32 of file r8192E_phyreg.h.

#define rPMAC_TxLegacySIG   0x108

Definition at line 27 of file r8192E_phyreg.h.

#define rPMAC_TxMACHeader0   0x120

Definition at line 33 of file r8192E_phyreg.h.

#define rPMAC_TxMACHeader1   0x124

Definition at line 34 of file r8192E_phyreg.h.

#define rPMAC_TxMACHeader2   0x128

Definition at line 35 of file r8192E_phyreg.h.

#define rPMAC_TxMACHeader3   0x12c

Definition at line 36 of file r8192E_phyreg.h.

#define rPMAC_TxMACHeader4   0x130

Definition at line 37 of file r8192E_phyreg.h.

#define rPMAC_TxMACHeader5   0x134

Definition at line 38 of file r8192E_phyreg.h.

#define rPMAC_TxPacketNum   0x118

Definition at line 31 of file r8192E_phyreg.h.

#define rPMAC_TxRandomSeed   0x13c

Definition at line 40 of file r8192E_phyreg.h.

#define rPMAC_TxStart   0x104

Definition at line 26 of file r8192E_phyreg.h.

#define rPMAC_TxStatus   0x18c

Definition at line 51 of file r8192E_phyreg.h.

#define rRTL8256_RxLPF   11

Definition at line 226 of file r8192E_phyreg.h.

#define rRTL8256_TxLPF   19

Definition at line 225 of file r8192E_phyreg.h.

#define rRTL8256RxMixerPole   0xb

Definition at line 845 of file r8192E_phyreg.h.

#define rRTL8256TxBBBW   19

Definition at line 849 of file r8192E_phyreg.h.

#define rRTL8256TxBBOPBias   0x9

Definition at line 847 of file r8192E_phyreg.h.

#define rRTL8258_RSSILPF   0xa

Definition at line 230 of file r8192E_phyreg.h.

#define rRTL8258_RxLPF   0x13

Definition at line 229 of file r8192E_phyreg.h.

#define rRTL8258_TxLPF   0x11

Definition at line 228 of file r8192E_phyreg.h.

#define rTxAGC_CCK_Mcs32   0xe08

Definition at line 206 of file r8192E_phyreg.h.

#define rTxAGC_Mcs03_Mcs00   0xe10

Definition at line 207 of file r8192E_phyreg.h.

#define rTxAGC_Mcs07_Mcs04   0xe14

Definition at line 208 of file r8192E_phyreg.h.

#define rTxAGC_Mcs11_Mcs08   0xe18

Definition at line 209 of file r8192E_phyreg.h.

#define rTxAGC_Mcs15_Mcs12   0xe1c

Definition at line 210 of file r8192E_phyreg.h.

#define rTxAGC_Rate18_06   0xe00

Definition at line 204 of file r8192E_phyreg.h.

#define rTxAGC_Rate54_24   0xe04

Definition at line 205 of file r8192E_phyreg.h.

#define rZebra1_AGC   0x4

Definition at line 216 of file r8192E_phyreg.h.

#define rZebra1_Channel   0x7

Definition at line 218 of file r8192E_phyreg.h.

#define rZebra1_ChargePump   0x5

Definition at line 217 of file r8192E_phyreg.h.

#define rZebra1_HSSIEnable   0x0

Definition at line 213 of file r8192E_phyreg.h.

#define rZebra1_RxHPFCorner   0xc

Definition at line 222 of file r8192E_phyreg.h.

#define rZebra1_RxLPF   0xb

Definition at line 221 of file r8192E_phyreg.h.

#define rZebra1_TRxEnable1   0x1

Definition at line 214 of file r8192E_phyreg.h.

#define rZebra1_TRxEnable2   0x2

Definition at line 215 of file r8192E_phyreg.h.

#define rZebra1_TxGain   0x8

Definition at line 219 of file r8192E_phyreg.h.

#define rZebra1_TxLPF   0x9

Definition at line 220 of file r8192E_phyreg.h.

#define tCheckTxStatus   500

Definition at line 821 of file r8192E_phyreg.h.

#define tUpdateRxCounter   100

Definition at line 822 of file r8192E_phyreg.h.

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