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| #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ |
| #define DC_CLES 0x07000000 /* Clear little endian swap mode */ |
| #define DC_DFWT 0x40000000 /* Data cache is forced write through */ |
| #define DC_FLINE 0x0e000000 /* Flush data cache line */ |
| #define DC_LES 0x20000000 /* Caches are little endian mode */ |
| #define DC_SFWT 0x01000000 /* Set forced writethrough mode */ |
| #define DC_SLES 0x05000000 /* Set little endian swap mode */ |
| #define IDC_CERR1 0x00200000 /* Cache error 1 */ |
| #define IDC_CERR2 0x00100000 /* Cache error 2 */ |
| #define IDC_CERR3 0x00080000 /* Cache error 3 */ |
| #define IDC_DISABLE 0x04000000 /* Cache disable */ |
| #define IDC_ENABLE 0x02000000 /* Cache enable */ |
| #define IDC_ENABLED 0x80000000 /* Cache is enabled */ |
| #define IDC_INVALL 0x0c000000 /* Invalidate all */ |
| #define IDC_LDLCK 0x06000000 /* Load and lock */ |
| #define IDC_UNALL 0x0a000000 /* Unlock all */ |
| #define IDC_UNLINE 0x08000000 /* Unlock line */ |
| #define SPRN_DC_DAT 570 /* Read-only data register */ |
| #define SPRN_IC_DAT 562 /* Read-only data register */ |
1.8.2