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Linux Kernel
3.7.1
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#include <mach/hardware.h>Go to the source code of this file.
Macros | |
| #define | MEM_CFG_OFFSET 0x0000 |
| #define | BURST_LEN_OFFSET 0x0010 |
| #define | MEM_RESET_OFFSET 0x0020 |
| #define | INT_ERR_STAT_OFFSET 0x0030 |
| #define | INT_ERR_MASK_OFFSET 0x0040 |
| #define | INT_ERR_ACK_OFFSET 0x0050 |
| #define | ECC_ERR_STAT_OFFSET 0x0060 |
| #define | MANUFACT_ID_OFFSET 0x0070 |
| #define | DEVICE_ID_OFFSET 0x0080 |
| #define | DATA_BUF_SIZE_OFFSET 0x0090 |
| #define | BOOT_BUF_SIZE_OFFSET 0x00A0 |
| #define | BUF_AMOUNT_OFFSET 0x00B0 |
| #define | TECH_OFFSET 0x00C0 |
| #define | FBA_WIDTH_OFFSET 0x00D0 |
| #define | FPA_WIDTH_OFFSET 0x00E0 |
| #define | FSA_WIDTH_OFFSET 0x00F0 |
| #define | TRANS_SPARE_OFFSET 0x0140 |
| #define | DBS_DFS_WIDTH_OFFSET 0x0160 |
| #define | INT_PIN_ENABLE_OFFSET 0x01A0 |
| #define | ACC_CLOCK_OFFSET 0x01C0 |
| #define | FLASH_VER_ID_OFFSET 0x01F0 |
| #define | FLASH_AUX_CNTRL_OFFSET 0x0300 /* s3c64xx only */ |
| #define | ONENAND_MEM_RESET_HOT 0x3 |
| #define | ONENAND_MEM_RESET_COLD 0x2 |
| #define | ONENAND_MEM_RESET_WARM 0x1 |
| #define | CACHE_OP_ERR (1 << 13) |
| #define | RST_CMP (1 << 12) |
| #define | RDY_ACT (1 << 11) |
| #define | INT_ACT (1 << 10) |
| #define | UNSUP_CMD (1 << 9) |
| #define | LOCKED_BLK (1 << 8) |
| #define | BLK_RW_CMP (1 << 7) |
| #define | ERS_CMP (1 << 6) |
| #define | PGM_CMP (1 << 5) |
| #define | LOAD_CMP (1 << 4) |
| #define | ERS_FAIL (1 << 3) |
| #define | PGM_FAIL (1 << 2) |
| #define | INT_TO (1 << 1) |
| #define | LD_FAIL_ECC_ERR (1 << 0) |
| #define | TSRF (1 << 0) |
| #define ACC_CLOCK_OFFSET 0x01C0 |
Definition at line 38 of file regs-onenand.h.
| #define BLK_RW_CMP (1 << 7) |
Definition at line 52 of file regs-onenand.h.
| #define BOOT_BUF_SIZE_OFFSET 0x00A0 |
Definition at line 29 of file regs-onenand.h.
| #define BUF_AMOUNT_OFFSET 0x00B0 |
Definition at line 30 of file regs-onenand.h.
| #define BURST_LEN_OFFSET 0x0010 |
Definition at line 20 of file regs-onenand.h.
| #define CACHE_OP_ERR (1 << 13) |
Definition at line 46 of file regs-onenand.h.
| #define DATA_BUF_SIZE_OFFSET 0x0090 |
Definition at line 28 of file regs-onenand.h.
| #define DBS_DFS_WIDTH_OFFSET 0x0160 |
Definition at line 36 of file regs-onenand.h.
| #define DEVICE_ID_OFFSET 0x0080 |
Definition at line 27 of file regs-onenand.h.
| #define ECC_ERR_STAT_OFFSET 0x0060 |
Definition at line 25 of file regs-onenand.h.
| #define ERS_CMP (1 << 6) |
Definition at line 53 of file regs-onenand.h.
| #define ERS_FAIL (1 << 3) |
Definition at line 56 of file regs-onenand.h.
| #define FBA_WIDTH_OFFSET 0x00D0 |
Definition at line 32 of file regs-onenand.h.
| #define FLASH_AUX_CNTRL_OFFSET 0x0300 /* s3c64xx only */ |
Definition at line 40 of file regs-onenand.h.
| #define FLASH_VER_ID_OFFSET 0x01F0 |
Definition at line 39 of file regs-onenand.h.
| #define FPA_WIDTH_OFFSET 0x00E0 |
Definition at line 33 of file regs-onenand.h.
| #define FSA_WIDTH_OFFSET 0x00F0 |
Definition at line 34 of file regs-onenand.h.
| #define INT_ACT (1 << 10) |
Definition at line 49 of file regs-onenand.h.
| #define INT_ERR_ACK_OFFSET 0x0050 |
Definition at line 24 of file regs-onenand.h.
| #define INT_ERR_MASK_OFFSET 0x0040 |
Definition at line 23 of file regs-onenand.h.
| #define INT_ERR_STAT_OFFSET 0x0030 |
Definition at line 22 of file regs-onenand.h.
| #define INT_PIN_ENABLE_OFFSET 0x01A0 |
Definition at line 37 of file regs-onenand.h.
| #define INT_TO (1 << 1) |
Definition at line 58 of file regs-onenand.h.
| #define LD_FAIL_ECC_ERR (1 << 0) |
Definition at line 59 of file regs-onenand.h.
| #define LOAD_CMP (1 << 4) |
Definition at line 55 of file regs-onenand.h.
| #define LOCKED_BLK (1 << 8) |
Definition at line 51 of file regs-onenand.h.
| #define MANUFACT_ID_OFFSET 0x0070 |
Definition at line 26 of file regs-onenand.h.
| #define MEM_CFG_OFFSET 0x0000 |
Definition at line 19 of file regs-onenand.h.
| #define MEM_RESET_OFFSET 0x0020 |
Definition at line 21 of file regs-onenand.h.
| #define ONENAND_MEM_RESET_COLD 0x2 |
Definition at line 43 of file regs-onenand.h.
| #define ONENAND_MEM_RESET_HOT 0x3 |
Definition at line 42 of file regs-onenand.h.
| #define ONENAND_MEM_RESET_WARM 0x1 |
Definition at line 44 of file regs-onenand.h.
| #define PGM_CMP (1 << 5) |
Definition at line 54 of file regs-onenand.h.
| #define PGM_FAIL (1 << 2) |
Definition at line 57 of file regs-onenand.h.
| #define RDY_ACT (1 << 11) |
Definition at line 48 of file regs-onenand.h.
| #define RST_CMP (1 << 12) |
Definition at line 47 of file regs-onenand.h.
| #define TECH_OFFSET 0x00C0 |
Definition at line 31 of file regs-onenand.h.
| #define TRANS_SPARE_OFFSET 0x0140 |
Definition at line 35 of file regs-onenand.h.
| #define TSRF (1 << 0) |
Definition at line 61 of file regs-onenand.h.
| #define UNSUP_CMD (1 << 9) |
Definition at line 50 of file regs-onenand.h.
1.8.2