Macros
#define	S3C2410_USBDREG(x) (x)

#define	S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)

#define	S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)

#define	S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)

#define	S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)

#define	S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)

#define	S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)

#define	S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)

#define	S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)

#define	S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)

#define	S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)

#define	S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)

#define	S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)

#define	S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)

#define	S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)

#define	S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)

#define	S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)

#define	S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)

#define	S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)

#define	S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)

#define	S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)

#define	S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)

#define	S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)

#define	S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)

#define	S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)

#define	S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)

#define	S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)

#define	S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)

#define	S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)

#define	S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)

#define	S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)

#define	S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)

#define	S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)

#define	S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)

#define	S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)

#define	S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)

#define	S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)

#define	S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)

#define	S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)

#define	S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)

#define	S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)

#define	S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)

#define	S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)

#define	S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)

#define	S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)

#define	S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)

#define	S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)

#define	S3C2410_UDC_FUNCADDR_UPDATE (1 << 7)

#define	S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */

#define	S3C2410_UDC_PWR_RESET (1 << 3) /* R */

#define	S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */

#define	S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */

#define	S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */

#define	S3C2410_UDC_PWR_DEFAULT (0x00)

#define	S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */

#define	S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */

#define	S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */

#define	S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */

#define	S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */

#define	S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */

#define	S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */

#define	S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */

#define	S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */

#define	S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */

#define	S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */

#define	S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */

#define	S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */

#define	S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */

#define	S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */

#define	S3C2410_UDC_INDEX_EP0 (0x00)

#define	S3C2410_UDC_INDEX_EP1 (0x01)

#define	S3C2410_UDC_INDEX_EP2 (0x02)

#define	S3C2410_UDC_INDEX_EP3 (0x03)

#define	S3C2410_UDC_INDEX_EP4 (0x04)

#define	S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */

#define	S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */

#define	S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */

#define	S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */

#define	S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */

#define	S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */

#define	S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */

#define	S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */

#define	S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */

#define	S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */

#define	S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */

#define	S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */

#define	S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */

#define	S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */

#define	S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */

#define	S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */

#define	S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */

#define	S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */

#define	S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */

#define	S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */

#define	S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0)

#define	S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1)

#define	S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2)

#define	S3C2410_UDC_EP0_CSR_DE (1 << 3)

#define	S3C2410_UDC_EP0_CSR_SE (1 << 4)

#define	S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5)

#define	S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6)

#define	S3C2410_UDC_EP0_CSR_SSE (1 << 7)

#define	S3C2410_UDC_MAXP_8 (1 << 0)

#define	S3C2410_UDC_MAXP_16 (1 << 1)

#define	S3C2410_UDC_MAXP_32 (1 << 2)

#define	S3C2410_UDC_MAXP_64 (1 << 3)

Macro Definition Documentation

#define S3C2410_UDC_EP0_CSR_DE (1 << 3)

Definition at line 140 of file regs-udc.h.

#define S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1)

Definition at line 138 of file regs-udc.h.

#define S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0)

Definition at line 137 of file regs-udc.h.

#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)

Definition at line 68 of file regs-udc.h.

#define S3C2410_UDC_EP0_CSR_SE (1 << 4)

Definition at line 141 of file regs-udc.h.

#define S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5)

Definition at line 142 of file regs-udc.h.

#define S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2)

Definition at line 139 of file regs-udc.h.

#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6)

Definition at line 143 of file regs-udc.h.

#define S3C2410_UDC_EP0_CSR_SSE (1 << 7)

Definition at line 144 of file regs-udc.h.

#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)

Definition at line 28 of file regs-udc.h.

#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)

Definition at line 34 of file regs-udc.h.

#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)

Definition at line 36 of file regs-udc.h.

#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)

Definition at line 39 of file regs-udc.h.

#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)

Definition at line 37 of file regs-udc.h.

#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)

Definition at line 38 of file regs-udc.h.

#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)

Definition at line 35 of file regs-udc.h.

#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)

Definition at line 29 of file regs-udc.h.

#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)

Definition at line 41 of file regs-udc.h.

#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)

Definition at line 43 of file regs-udc.h.

#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)

Definition at line 46 of file regs-udc.h.

#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)

Definition at line 44 of file regs-udc.h.

#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)

Definition at line 45 of file regs-udc.h.

#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)

Definition at line 42 of file regs-udc.h.

#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)

Definition at line 30 of file regs-udc.h.

#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)

Definition at line 48 of file regs-udc.h.

#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)

Definition at line 50 of file regs-udc.h.

#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)

Definition at line 53 of file regs-udc.h.

#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)

Definition at line 51 of file regs-udc.h.

#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)

Definition at line 52 of file regs-udc.h.

#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)

Definition at line 49 of file regs-udc.h.

#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)

Definition at line 31 of file regs-udc.h.

#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)

Definition at line 55 of file regs-udc.h.

#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)

Definition at line 57 of file regs-udc.h.

#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)

Definition at line 60 of file regs-udc.h.

#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)

Definition at line 58 of file regs-udc.h.

#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)

Definition at line 59 of file regs-udc.h.

#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)

Definition at line 56 of file regs-udc.h.

#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)

Definition at line 32 of file regs-udc.h.

#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)

Definition at line 21 of file regs-udc.h.

#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)

Definition at line 18 of file regs-udc.h.

#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)

Definition at line 25 of file regs-udc.h.

#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)

Definition at line 26 of file regs-udc.h.

#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)

Definition at line 16 of file regs-udc.h.

#define S3C2410_UDC_FUNCADDR_UPDATE (1 << 7)

Definition at line 78 of file regs-udc.h.

#define S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */

Definition at line 113 of file regs-udc.h.

#define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */

Definition at line 116 of file regs-udc.h.

#define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */

Definition at line 118 of file regs-udc.h.

#define S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */

Definition at line 115 of file regs-udc.h.

#define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */

Definition at line 114 of file regs-udc.h.

#define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */

Definition at line 117 of file regs-udc.h.

#define S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */

Definition at line 120 of file regs-udc.h.

#define S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */

Definition at line 123 of file regs-udc.h.

#define S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */

Definition at line 121 of file regs-udc.h.

#define S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */

Definition at line 122 of file regs-udc.h.

#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)

Definition at line 70 of file regs-udc.h.

#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)

Definition at line 71 of file regs-udc.h.

#define S3C2410_UDC_INDEX_EP0 (0x00)

Definition at line 107 of file regs-udc.h.

#define S3C2410_UDC_INDEX_EP1 (0x01)

Definition at line 108 of file regs-udc.h.

#define S3C2410_UDC_INDEX_EP2 (0x02)

Definition at line 109 of file regs-udc.h.

#define S3C2410_UDC_INDEX_EP3 (0x03)

Definition at line 110 of file regs-udc.h.

#define S3C2410_UDC_INDEX_EP4 (0x04)

Definition at line 111 of file regs-udc.h.

#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)

Definition at line 62 of file regs-udc.h.

#define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */

Definition at line 92 of file regs-udc.h.

#define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */

Definition at line 91 of file regs-udc.h.

#define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */

Definition at line 90 of file regs-udc.h.

#define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */

Definition at line 89 of file regs-udc.h.

#define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */

Definition at line 88 of file regs-udc.h.

#define S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */

Definition at line 102 of file regs-udc.h.

#define S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */

Definition at line 101 of file regs-udc.h.

#define S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */

Definition at line 100 of file regs-udc.h.

#define S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */

Definition at line 99 of file regs-udc.h.

#define S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */

Definition at line 98 of file regs-udc.h.

#define S3C2410_UDC_MAXP_16 (1 << 1)

Definition at line 147 of file regs-udc.h.

#define S3C2410_UDC_MAXP_32 (1 << 2)

Definition at line 148 of file regs-udc.h.

#define S3C2410_UDC_MAXP_64 (1 << 3)

Definition at line 149 of file regs-udc.h.

#define S3C2410_UDC_MAXP_8 (1 << 0)

Definition at line 146 of file regs-udc.h.

#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)

Definition at line 66 of file regs-udc.h.

#define S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */

Definition at line 125 of file regs-udc.h.

#define S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */

Definition at line 129 of file regs-udc.h.

#define S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */

Definition at line 128 of file regs-udc.h.

#define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */

Definition at line 130 of file regs-udc.h.

#define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */

Definition at line 131 of file regs-udc.h.

#define S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */

Definition at line 127 of file regs-udc.h.

#define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */

Definition at line 126 of file regs-udc.h.

#define S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */

Definition at line 133 of file regs-udc.h.

#define S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */

Definition at line 135 of file regs-udc.h.

#define S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */

Definition at line 134 of file regs-udc.h.

#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)

Definition at line 73 of file regs-udc.h.

#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)

Definition at line 74 of file regs-udc.h.

#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)

Definition at line 75 of file regs-udc.h.

#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)

Definition at line 76 of file regs-udc.h.

#define S3C2410_UDC_PWR_DEFAULT (0x00)

Definition at line 86 of file regs-udc.h.

#define S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */

Definition at line 84 of file regs-udc.h.

#define S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */

Definition at line 80 of file regs-udc.h.

#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)

Definition at line 17 of file regs-udc.h.

#define S3C2410_UDC_PWR_RESET (1 << 3) /* R */

Definition at line 81 of file regs-udc.h.

#define S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */

Definition at line 82 of file regs-udc.h.

#define S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */

Definition at line 83 of file regs-udc.h.

#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)

Definition at line 23 of file regs-udc.h.

#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)

Definition at line 20 of file regs-udc.h.

#define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */

Definition at line 94 of file regs-udc.h.

#define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */

Definition at line 95 of file regs-udc.h.

#define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */

Definition at line 96 of file regs-udc.h.

#define S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */

Definition at line 104 of file regs-udc.h.

#define S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */

Definition at line 105 of file regs-udc.h.

#define S3C2410_USBDREG ( x ) (x)

Definition at line 14 of file regs-udc.h.

Macros

Macro Definition Documentation