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rio_regs.h
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1 /*
2  * RapidIO register definitions
3  *
4  * Copyright 2005 MontaVista Software, Inc.
5  * Matt Porter <[email protected]>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  */
12 
13 #ifndef LINUX_RIO_REGS_H
14 #define LINUX_RIO_REGS_H
15 
16 /*
17  * In RapidIO, each device has a 16MB configuration space that is
18  * accessed via maintenance transactions. Portions of configuration
19  * space are standardized and/or reserved.
20  */
21 #define RIO_MAINT_SPACE_SZ 0x1000000 /* 16MB of RapidIO mainenance space */
22 
23 #define RIO_DEV_ID_CAR 0x00 /* [I] Device Identity CAR */
24 #define RIO_DEV_INFO_CAR 0x04 /* [I] Device Information CAR */
25 #define RIO_ASM_ID_CAR 0x08 /* [I] Assembly Identity CAR */
26 #define RIO_ASM_ID_MASK 0xffff0000 /* [I] Asm ID Mask */
27 #define RIO_ASM_VEN_ID_MASK 0x0000ffff /* [I] Asm Vend Mask */
28 
29 #define RIO_ASM_INFO_CAR 0x0c /* [I] Assembly Information CAR */
30 #define RIO_ASM_REV_MASK 0xffff0000 /* [I] Asm Rev Mask */
31 #define RIO_EXT_FTR_PTR_MASK 0x0000ffff /* [I] EF_PTR Mask */
32 
33 #define RIO_PEF_CAR 0x10 /* [I] Processing Element Features CAR */
34 #define RIO_PEF_BRIDGE 0x80000000 /* [I] Bridge */
35 #define RIO_PEF_MEMORY 0x40000000 /* [I] MMIO */
36 #define RIO_PEF_PROCESSOR 0x20000000 /* [I] Processor */
37 #define RIO_PEF_SWITCH 0x10000000 /* [I] Switch */
38 #define RIO_PEF_MULTIPORT 0x08000000 /* [VI, 2.1] Multiport */
39 #define RIO_PEF_INB_MBOX 0x00f00000 /* [II, <= 1.2] Mailboxes */
40 #define RIO_PEF_INB_MBOX0 0x00800000 /* [II, <= 1.2] Mailbox 0 */
41 #define RIO_PEF_INB_MBOX1 0x00400000 /* [II, <= 1.2] Mailbox 1 */
42 #define RIO_PEF_INB_MBOX2 0x00200000 /* [II, <= 1.2] Mailbox 2 */
43 #define RIO_PEF_INB_MBOX3 0x00100000 /* [II, <= 1.2] Mailbox 3 */
44 #define RIO_PEF_INB_DOORBELL 0x00080000 /* [II, <= 1.2] Doorbells */
45 #define RIO_PEF_EXT_RT 0x00000200 /* [III, 1.3] Extended route table support */
46 #define RIO_PEF_STD_RT 0x00000100 /* [III, 1.3] Standard route table support */
47 #define RIO_PEF_CTLS 0x00000010 /* [III] CTLS */
48 #define RIO_PEF_EXT_FEATURES 0x00000008 /* [I] EFT_PTR valid */
49 #define RIO_PEF_ADDR_66 0x00000004 /* [I] 66 bits */
50 #define RIO_PEF_ADDR_50 0x00000002 /* [I] 50 bits */
51 #define RIO_PEF_ADDR_34 0x00000001 /* [I] 34 bits */
52 
53 #define RIO_SWP_INFO_CAR 0x14 /* [I] Switch Port Information CAR */
54 #define RIO_SWP_INFO_PORT_TOTAL_MASK 0x0000ff00 /* [I] Total number of ports */
55 #define RIO_SWP_INFO_PORT_NUM_MASK 0x000000ff /* [I] Maintenance transaction port number */
56 #define RIO_GET_TOTAL_PORTS(x) ((x & RIO_SWP_INFO_PORT_TOTAL_MASK) >> 8)
57 #define RIO_GET_PORT_NUM(x) (x & RIO_SWP_INFO_PORT_NUM_MASK)
58 
59 #define RIO_SRC_OPS_CAR 0x18 /* [I] Source Operations CAR */
60 #define RIO_SRC_OPS_READ 0x00008000 /* [I] Read op */
61 #define RIO_SRC_OPS_WRITE 0x00004000 /* [I] Write op */
62 #define RIO_SRC_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
63 #define RIO_SRC_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
64 #define RIO_SRC_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
65 #define RIO_SRC_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
66 #define RIO_SRC_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
67 #define RIO_SRC_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
68 #define RIO_SRC_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
69 #define RIO_SRC_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
70 #define RIO_SRC_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
71 #define RIO_SRC_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
72 
73 #define RIO_DST_OPS_CAR 0x1c /* Destination Operations CAR */
74 #define RIO_DST_OPS_READ 0x00008000 /* [I] Read op */
75 #define RIO_DST_OPS_WRITE 0x00004000 /* [I] Write op */
76 #define RIO_DST_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
77 #define RIO_DST_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
78 #define RIO_DST_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
79 #define RIO_DST_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
80 #define RIO_DST_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
81 #define RIO_DST_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
82 #define RIO_DST_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
83 #define RIO_DST_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
84 #define RIO_DST_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
85 #define RIO_DST_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
86 
87 #define RIO_OPS_READ 0x00008000 /* [I] Read op */
88 #define RIO_OPS_WRITE 0x00004000 /* [I] Write op */
89 #define RIO_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
90 #define RIO_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
91 #define RIO_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
92 #define RIO_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
93 #define RIO_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
94 #define RIO_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
95 #define RIO_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
96 #define RIO_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
97 #define RIO_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
98 #define RIO_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
99 
100  /* 0x20-0x30 *//* Reserved */
101 
102 #define RIO_SWITCH_RT_LIMIT 0x34 /* [III, 1.3] Switch Route Table Destination ID Limit CAR */
103 #define RIO_RT_MAX_DESTID 0x0000ffff
104 
105 #define RIO_MBOX_CSR 0x40 /* [II, <= 1.2] Mailbox CSR */
106 #define RIO_MBOX0_AVAIL 0x80000000 /* [II] Mbox 0 avail */
107 #define RIO_MBOX0_FULL 0x40000000 /* [II] Mbox 0 full */
108 #define RIO_MBOX0_EMPTY 0x20000000 /* [II] Mbox 0 empty */
109 #define RIO_MBOX0_BUSY 0x10000000 /* [II] Mbox 0 busy */
110 #define RIO_MBOX0_FAIL 0x08000000 /* [II] Mbox 0 fail */
111 #define RIO_MBOX0_ERROR 0x04000000 /* [II] Mbox 0 error */
112 #define RIO_MBOX1_AVAIL 0x00800000 /* [II] Mbox 1 avail */
113 #define RIO_MBOX1_FULL 0x00200000 /* [II] Mbox 1 full */
114 #define RIO_MBOX1_EMPTY 0x00200000 /* [II] Mbox 1 empty */
115 #define RIO_MBOX1_BUSY 0x00100000 /* [II] Mbox 1 busy */
116 #define RIO_MBOX1_FAIL 0x00080000 /* [II] Mbox 1 fail */
117 #define RIO_MBOX1_ERROR 0x00040000 /* [II] Mbox 1 error */
118 #define RIO_MBOX2_AVAIL 0x00008000 /* [II] Mbox 2 avail */
119 #define RIO_MBOX2_FULL 0x00004000 /* [II] Mbox 2 full */
120 #define RIO_MBOX2_EMPTY 0x00002000 /* [II] Mbox 2 empty */
121 #define RIO_MBOX2_BUSY 0x00001000 /* [II] Mbox 2 busy */
122 #define RIO_MBOX2_FAIL 0x00000800 /* [II] Mbox 2 fail */
123 #define RIO_MBOX2_ERROR 0x00000400 /* [II] Mbox 2 error */
124 #define RIO_MBOX3_AVAIL 0x00000080 /* [II] Mbox 3 avail */
125 #define RIO_MBOX3_FULL 0x00000040 /* [II] Mbox 3 full */
126 #define RIO_MBOX3_EMPTY 0x00000020 /* [II] Mbox 3 empty */
127 #define RIO_MBOX3_BUSY 0x00000010 /* [II] Mbox 3 busy */
128 #define RIO_MBOX3_FAIL 0x00000008 /* [II] Mbox 3 fail */
129 #define RIO_MBOX3_ERROR 0x00000004 /* [II] Mbox 3 error */
130 
131 #define RIO_WRITE_PORT_CSR 0x44 /* [I, <= 1.2] Write Port CSR */
132 #define RIO_DOORBELL_CSR 0x44 /* [II, <= 1.2] Doorbell CSR */
133 #define RIO_DOORBELL_AVAIL 0x80000000 /* [II] Doorbell avail */
134 #define RIO_DOORBELL_FULL 0x40000000 /* [II] Doorbell full */
135 #define RIO_DOORBELL_EMPTY 0x20000000 /* [II] Doorbell empty */
136 #define RIO_DOORBELL_BUSY 0x10000000 /* [II] Doorbell busy */
137 #define RIO_DOORBELL_FAILED 0x08000000 /* [II] Doorbell failed */
138 #define RIO_DOORBELL_ERROR 0x04000000 /* [II] Doorbell error */
139 #define RIO_WRITE_PORT_AVAILABLE 0x00000080 /* [I] Write Port Available */
140 #define RIO_WRITE_PORT_FULL 0x00000040 /* [I] Write Port Full */
141 #define RIO_WRITE_PORT_EMPTY 0x00000020 /* [I] Write Port Empty */
142 #define RIO_WRITE_PORT_BUSY 0x00000010 /* [I] Write Port Busy */
143 #define RIO_WRITE_PORT_FAILED 0x00000008 /* [I] Write Port Failed */
144 #define RIO_WRITE_PORT_ERROR 0x00000004 /* [I] Write Port Error */
145 
146  /* 0x48 *//* Reserved */
147 
148 #define RIO_PELL_CTRL_CSR 0x4c /* [I] PE Logical Layer Control CSR */
149 #define RIO_PELL_ADDR_66 0x00000004 /* [I] 66-bit addr */
150 #define RIO_PELL_ADDR_50 0x00000002 /* [I] 50-bit addr */
151 #define RIO_PELL_ADDR_34 0x00000001 /* [I] 34-bit addr */
152 
153  /* 0x50-0x54 *//* Reserved */
154 
155 #define RIO_LCSH_BA 0x58 /* [I] LCS High Base Address */
156 #define RIO_LCSL_BA 0x5c /* [I] LCS Base Address */
157 
158 #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
159 
160  /* 0x64 *//* Reserved */
161 
162 #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
163 #define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */
164 
165 #define RIO_STD_RTE_CONF_DESTID_SEL_CSR 0x70
166 #define RIO_STD_RTE_CONF_EXTCFGEN 0x80000000
167 #define RIO_STD_RTE_CONF_PORT_SEL_CSR 0x74
168 #define RIO_STD_RTE_DEFAULT_PORT 0x78
169 
170  /* 0x7c-0xf8 *//* Reserved */
171  /* 0x100-0xfff8 *//* [I] Extended Features Space */
172  /* 0x10000-0xfffff8 *//* [I] Implementation-defined Space */
173 
174 /*
175  * Extended Features Space is a configuration space area where
176  * functionality is mapped into extended feature blocks via a
177  * singly linked list of extended feature pointers (EFT_PTR).
178  *
179  * Each extended feature block can be identified/located in
180  * Extended Features Space by walking the extended feature
181  * list starting with the Extended Feature Pointer located
182  * in the Assembly Information CAR.
183  *
184  * Extended Feature Blocks (EFBs) are identified with an assigned
185  * EFB ID. Extended feature block offsets in the definitions are
186  * relative to the offset of the EFB within the Extended Features
187  * Space.
188  */
189 
190 /* Helper macros to parse the Extended Feature Block header */
191 #define RIO_EFB_PTR_MASK 0xffff0000
192 #define RIO_EFB_ID_MASK 0x0000ffff
193 #define RIO_GET_BLOCK_PTR(x) ((x & RIO_EFB_PTR_MASK) >> 16)
194 #define RIO_GET_BLOCK_ID(x) (x & RIO_EFB_ID_MASK)
195 
196 /* Extended Feature Block IDs */
197 #define RIO_EFB_PAR_EP_ID 0x0001 /* [IV] LP/LVDS EP Devices */
198 #define RIO_EFB_PAR_EP_REC_ID 0x0002 /* [IV] LP/LVDS EP Recovery Devices */
199 #define RIO_EFB_PAR_EP_FREE_ID 0x0003 /* [IV] LP/LVDS EP Free Devices */
200 #define RIO_EFB_SER_EP_ID_V13P 0x0001 /* [VI] LP/Serial EP Devices, RapidIO Spec ver 1.3 and above */
201 #define RIO_EFB_SER_EP_REC_ID_V13P 0x0002 /* [VI] LP/Serial EP Recovery Devices, RapidIO Spec ver 1.3 and above */
202 #define RIO_EFB_SER_EP_FREE_ID_V13P 0x0003 /* [VI] LP/Serial EP Free Devices, RapidIO Spec ver 1.3 and above */
203 #define RIO_EFB_SER_EP_ID 0x0004 /* [VI] LP/Serial EP Devices */
204 #define RIO_EFB_SER_EP_REC_ID 0x0005 /* [VI] LP/Serial EP Recovery Devices */
205 #define RIO_EFB_SER_EP_FREE_ID 0x0006 /* [VI] LP/Serial EP Free Devices */
206 #define RIO_EFB_SER_EP_FREC_ID 0x0009 /* [VI] LP/Serial EP Free Recovery Devices */
207 #define RIO_EFB_ERR_MGMNT 0x0007 /* [VIII] Error Management Extensions */
208 
209 /*
210  * Physical 8/16 LP-LVDS
211  * ID=0x0001, Generic End Point Devices
212  * ID=0x0002, Generic End Point Devices, software assisted recovery option
213  * ID=0x0003, Generic End Point Free Devices
214  *
215  * Physical LP-Serial
216  * ID=0x0004, Generic End Point Devices
217  * ID=0x0005, Generic End Point Devices, software assisted recovery option
218  * ID=0x0006, Generic End Point Free Devices
219  */
220 #define RIO_PORT_MNT_HEADER 0x0000
221 #define RIO_PORT_REQ_CTL_CSR 0x0020
222 #define RIO_PORT_RSP_CTL_CSR 0x0024 /* 0x0001/0x0002 */
223 #define RIO_PORT_LINKTO_CTL_CSR 0x0020 /* Serial */
224 #define RIO_PORT_RSPTO_CTL_CSR 0x0024 /* Serial */
225 #define RIO_PORT_GEN_CTL_CSR 0x003c
226 #define RIO_PORT_GEN_HOST 0x80000000
227 #define RIO_PORT_GEN_MASTER 0x40000000
228 #define RIO_PORT_GEN_DISCOVERED 0x20000000
229 #define RIO_PORT_N_MNT_REQ_CSR(x) (0x0040 + x*0x20) /* 0x0002 */
230 #define RIO_MNT_REQ_CMD_RD 0x03 /* Reset-device command */
231 #define RIO_MNT_REQ_CMD_IS 0x04 /* Input-status command */
232 #define RIO_PORT_N_MNT_RSP_CSR(x) (0x0044 + x*0x20) /* 0x0002 */
233 #define RIO_PORT_N_MNT_RSP_RVAL 0x80000000 /* Response Valid */
234 #define RIO_PORT_N_MNT_RSP_ASTAT 0x000007e0 /* ackID Status */
235 #define RIO_PORT_N_MNT_RSP_LSTAT 0x0000001f /* Link Status */
236 #define RIO_PORT_N_ACK_STS_CSR(x) (0x0048 + x*0x20) /* 0x0002 */
237 #define RIO_PORT_N_ACK_CLEAR 0x80000000
238 #define RIO_PORT_N_ACK_INBOUND 0x3f000000
239 #define RIO_PORT_N_ACK_OUTSTAND 0x00003f00
240 #define RIO_PORT_N_ACK_OUTBOUND 0x0000003f
241 #define RIO_PORT_N_ERR_STS_CSR(x) (0x0058 + x*0x20)
242 #define RIO_PORT_N_ERR_STS_PW_OUT_ES 0x00010000 /* Output Error-stopped */
243 #define RIO_PORT_N_ERR_STS_PW_INP_ES 0x00000100 /* Input Error-stopped */
244 #define RIO_PORT_N_ERR_STS_PW_PEND 0x00000010 /* Port-Write Pending */
245 #define RIO_PORT_N_ERR_STS_PORT_ERR 0x00000004
246 #define RIO_PORT_N_ERR_STS_PORT_OK 0x00000002
247 #define RIO_PORT_N_ERR_STS_PORT_UNINIT 0x00000001
248 #define RIO_PORT_N_CTL_CSR(x) (0x005c + x*0x20)
249 #define RIO_PORT_N_CTL_PWIDTH 0xc0000000
250 #define RIO_PORT_N_CTL_PWIDTH_1 0x00000000
251 #define RIO_PORT_N_CTL_PWIDTH_4 0x40000000
252 #define RIO_PORT_N_CTL_P_TYP_SER 0x00000001
253 #define RIO_PORT_N_CTL_LOCKOUT 0x00000002
254 #define RIO_PORT_N_CTL_EN_RX_SER 0x00200000
255 #define RIO_PORT_N_CTL_EN_TX_SER 0x00400000
256 #define RIO_PORT_N_CTL_EN_RX_PAR 0x08000000
257 #define RIO_PORT_N_CTL_EN_TX_PAR 0x40000000
258 
259 /*
260  * Error Management Extensions (RapidIO 1.3+, Part 8)
261  *
262  * Extended Features Block ID=0x0007
263  */
264 
265 /* General EM Registers (Common for all Ports) */
266 
267 #define RIO_EM_EFB_HEADER 0x000 /* Error Management Extensions Block Header */
268 #define RIO_EM_LTL_ERR_DETECT 0x008 /* Logical/Transport Layer Error Detect CSR */
269 #define RIO_EM_LTL_ERR_EN 0x00c /* Logical/Transport Layer Error Enable CSR */
270 #define REM_LTL_ERR_ILLTRAN 0x08000000 /* Illegal Transaction decode */
271 #define REM_LTL_ERR_UNSOLR 0x00800000 /* Unsolicited Response */
272 #define REM_LTL_ERR_UNSUPTR 0x00400000 /* Unsupported Transaction */
273 #define REM_LTL_ERR_IMPSPEC 0x000000ff /* Implementation Specific */
274 #define RIO_EM_LTL_HIADDR_CAP 0x010 /* Logical/Transport Layer High Address Capture CSR */
275 #define RIO_EM_LTL_ADDR_CAP 0x014 /* Logical/Transport Layer Address Capture CSR */
276 #define RIO_EM_LTL_DEVID_CAP 0x018 /* Logical/Transport Layer Device ID Capture CSR */
277 #define RIO_EM_LTL_CTRL_CAP 0x01c /* Logical/Transport Layer Control Capture CSR */
278 #define RIO_EM_PW_TGT_DEVID 0x028 /* Port-write Target deviceID CSR */
279 #define RIO_EM_PKT_TTL 0x02c /* Packet Time-to-live CSR */
280 
281 /* Per-Port EM Registers */
282 
283 #define RIO_EM_PN_ERR_DETECT(x) (0x040 + x*0x40) /* Port N Error Detect CSR */
284 #define REM_PED_IMPL_SPEC 0x80000000
285 #define REM_PED_LINK_TO 0x00000001
286 #define RIO_EM_PN_ERRRATE_EN(x) (0x044 + x*0x40) /* Port N Error Rate Enable CSR */
287 #define RIO_EM_PN_ATTRIB_CAP(x) (0x048 + x*0x40) /* Port N Attributes Capture CSR */
288 #define RIO_EM_PN_PKT_CAP_0(x) (0x04c + x*0x40) /* Port N Packet/Control Symbol Capture 0 CSR */
289 #define RIO_EM_PN_PKT_CAP_1(x) (0x050 + x*0x40) /* Port N Packet Capture 1 CSR */
290 #define RIO_EM_PN_PKT_CAP_2(x) (0x054 + x*0x40) /* Port N Packet Capture 2 CSR */
291 #define RIO_EM_PN_PKT_CAP_3(x) (0x058 + x*0x40) /* Port N Packet Capture 3 CSR */
292 #define RIO_EM_PN_ERRRATE(x) (0x068 + x*0x40) /* Port N Error Rate CSR */
293 #define RIO_EM_PN_ERRRATE_TR(x) (0x06c + x*0x40) /* Port N Error Rate Threshold CSR */
294 
295 #endif /* LINUX_RIO_REGS_H */
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