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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | RF2420 0x0000 |
| #define | RF2421 0x0001 |
| #define | DEFAULT_RSSI_OFFSET 100 |
| #define | CSR_REG_BASE 0x0000 |
| #define | CSR_REG_SIZE 0x014c |
| #define | EEPROM_BASE 0x0000 |
| #define | EEPROM_SIZE 0x0100 |
| #define | BBP_BASE 0x0000 |
| #define | BBP_SIZE 0x0020 |
| #define | RF_BASE 0x0004 |
| #define | RF_SIZE 0x000c |
| #define | NUM_TX_QUEUES 2 |
| #define | CSR0 0x0000 |
| #define | CSR0_REVISION FIELD32(0x0000ffff) |
| #define | CSR1 0x0004 |
| #define | CSR1_SOFT_RESET FIELD32(0x00000001) |
| #define | CSR1_BBP_RESET FIELD32(0x00000002) |
| #define | CSR1_HOST_READY FIELD32(0x00000004) |
| #define | CSR2 0x0008 |
| #define | CSR3 0x000c |
| #define | CSR3_BYTE0 FIELD32(0x000000ff) |
| #define | CSR3_BYTE1 FIELD32(0x0000ff00) |
| #define | CSR3_BYTE2 FIELD32(0x00ff0000) |
| #define | CSR3_BYTE3 FIELD32(0xff000000) |
| #define | CSR4 0x0010 |
| #define | CSR4_BYTE4 FIELD32(0x000000ff) |
| #define | CSR4_BYTE5 FIELD32(0x0000ff00) |
| #define | CSR5 0x0014 |
| #define | CSR5_BYTE0 FIELD32(0x000000ff) |
| #define | CSR5_BYTE1 FIELD32(0x0000ff00) |
| #define | CSR5_BYTE2 FIELD32(0x00ff0000) |
| #define | CSR5_BYTE3 FIELD32(0xff000000) |
| #define | CSR6 0x0018 |
| #define | CSR6_BYTE4 FIELD32(0x000000ff) |
| #define | CSR6_BYTE5 FIELD32(0x0000ff00) |
| #define | CSR7 0x001c |
| #define | CSR7_TBCN_EXPIRE FIELD32(0x00000001) |
| #define | CSR7_TWAKE_EXPIRE FIELD32(0x00000002) |
| #define | CSR7_TATIMW_EXPIRE FIELD32(0x00000004) |
| #define | CSR7_TXDONE_TXRING FIELD32(0x00000008) |
| #define | CSR7_TXDONE_ATIMRING FIELD32(0x00000010) |
| #define | CSR7_TXDONE_PRIORING FIELD32(0x00000020) |
| #define | CSR7_RXDONE FIELD32(0x00000040) |
| #define | CSR8 0x0020 |
| #define | CSR8_TBCN_EXPIRE FIELD32(0x00000001) |
| #define | CSR8_TWAKE_EXPIRE FIELD32(0x00000002) |
| #define | CSR8_TATIMW_EXPIRE FIELD32(0x00000004) |
| #define | CSR8_TXDONE_TXRING FIELD32(0x00000008) |
| #define | CSR8_TXDONE_ATIMRING FIELD32(0x00000010) |
| #define | CSR8_TXDONE_PRIORING FIELD32(0x00000020) |
| #define | CSR8_RXDONE FIELD32(0x00000040) |
| #define | CSR9 0x0024 |
| #define | CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80) |
| #define | CSR11 0x002c |
| #define | CSR11_CWMIN FIELD32(0x0000000f) |
| #define | CSR11_CWMAX FIELD32(0x000000f0) |
| #define | CSR11_SLOT_TIME FIELD32(0x00001f00) |
| #define | CSR11_LONG_RETRY FIELD32(0x00ff0000) |
| #define | CSR11_SHORT_RETRY FIELD32(0xff000000) |
| #define | CSR12 0x0030 |
| #define | CSR12_BEACON_INTERVAL FIELD32(0x0000ffff) |
| #define | CSR12_CFP_MAX_DURATION FIELD32(0xffff0000) |
| #define | CSR13 0x0034 |
| #define | CSR13_ATIMW_DURATION FIELD32(0x0000ffff) |
| #define | CSR13_CFP_PERIOD FIELD32(0x00ff0000) |
| #define | CSR14 0x0038 |
| #define | CSR14_TSF_COUNT FIELD32(0x00000001) |
| #define | CSR14_TSF_SYNC FIELD32(0x00000006) |
| #define | CSR14_TBCN FIELD32(0x00000008) |
| #define | CSR14_TCFP FIELD32(0x00000010) |
| #define | CSR14_TATIMW FIELD32(0x00000020) |
| #define | CSR14_BEACON_GEN FIELD32(0x00000040) |
| #define | CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00) |
| #define | CSR14_TBCM_PRELOAD FIELD32(0xffff0000) |
| #define | CSR15 0x003c |
| #define | CSR15_CFP FIELD32(0x00000001) |
| #define | CSR15_ATIMW FIELD32(0x00000002) |
| #define | CSR15_BEACON_SENT FIELD32(0x00000004) |
| #define | CSR16 0x0040 |
| #define | CSR16_LOW_TSFTIMER FIELD32(0xffffffff) |
| #define | CSR17 0x0044 |
| #define | CSR17_HIGH_TSFTIMER FIELD32(0xffffffff) |
| #define | CSR18 0x0048 |
| #define | CSR18_SIFS FIELD32(0x0000ffff) |
| #define | CSR18_PIFS FIELD32(0xffff0000) |
| #define | CSR19 0x004c |
| #define | CSR19_DIFS FIELD32(0x0000ffff) |
| #define | CSR19_EIFS FIELD32(0xffff0000) |
| #define | CSR20 0x0050 |
| #define | CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff) |
| #define | CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000) |
| #define | CSR20_AUTOWAKE FIELD32(0x01000000) |
| #define | CSR21 0x0054 |
| #define | CSR21_RELOAD FIELD32(0x00000001) |
| #define | CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002) |
| #define | CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004) |
| #define | CSR21_EEPROM_DATA_IN FIELD32(0x00000008) |
| #define | CSR21_EEPROM_DATA_OUT FIELD32(0x00000010) |
| #define | CSR21_TYPE_93C46 FIELD32(0x00000020) |
| #define | CSR22 0x0058 |
| #define | CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff) |
| #define | CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000) |
| #define | TXCSR0 0x0060 |
| #define | TXCSR0_KICK_TX FIELD32(0x00000001) |
| #define | TXCSR0_KICK_ATIM FIELD32(0x00000002) |
| #define | TXCSR0_KICK_PRIO FIELD32(0x00000004) |
| #define | TXCSR0_ABORT FIELD32(0x00000008) |
| #define | TXCSR1 0x0064 |
| #define | TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff) |
| #define | TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00) |
| #define | TXCSR1_TSF_OFFSET FIELD32(0x00fc0000) |
| #define | TXCSR1_AUTORESPONDER FIELD32(0x01000000) |
| #define | TXCSR2 0x0068 |
| #define | TXCSR2_TXD_SIZE FIELD32(0x000000ff) |
| #define | TXCSR2_NUM_TXD FIELD32(0x0000ff00) |
| #define | TXCSR2_NUM_ATIM FIELD32(0x00ff0000) |
| #define | TXCSR2_NUM_PRIO FIELD32(0xff000000) |
| #define | TXCSR3 0x006c |
| #define | TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff) |
| #define | TXCSR4 0x0070 |
| #define | TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff) |
| #define | TXCSR5 0x0074 |
| #define | TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff) |
| #define | TXCSR6 0x0078 |
| #define | TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff) |
| #define | TXCSR7 0x007c |
| #define | TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001) |
| #define | RXCSR0 0x0080 |
| #define | RXCSR0_DISABLE_RX FIELD32(0x00000001) |
| #define | RXCSR0_DROP_CRC FIELD32(0x00000002) |
| #define | RXCSR0_DROP_PHYSICAL FIELD32(0x00000004) |
| #define | RXCSR0_DROP_CONTROL FIELD32(0x00000008) |
| #define | RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010) |
| #define | RXCSR0_DROP_TODS FIELD32(0x00000020) |
| #define | RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040) |
| #define | RXCSR0_PASS_CRC FIELD32(0x00000080) |
| #define | RXCSR1 0x0084 |
| #define | RXCSR1_RXD_SIZE FIELD32(0x000000ff) |
| #define | RXCSR1_NUM_RXD FIELD32(0x0000ff00) |
| #define | RXCSR2 0x0088 |
| #define | RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff) |
| #define | RXCSR3 0x0090 |
| #define | RXCSR3_BBP_ID0 FIELD32(0x0000007f) |
| #define | RXCSR3_BBP_ID0_VALID FIELD32(0x00000080) |
| #define | RXCSR3_BBP_ID1 FIELD32(0x00007f00) |
| #define | RXCSR3_BBP_ID1_VALID FIELD32(0x00008000) |
| #define | RXCSR3_BBP_ID2 FIELD32(0x007f0000) |
| #define | RXCSR3_BBP_ID2_VALID FIELD32(0x00800000) |
| #define | RXCSR3_BBP_ID3 FIELD32(0x7f000000) |
| #define | RXCSR3_BBP_ID3_VALID FIELD32(0x80000000) |
| #define | RXCSR4 0x0094 |
| #define | RXCSR4_BBP_ID4 FIELD32(0x0000007f) |
| #define | RXCSR4_BBP_ID4_VALID FIELD32(0x00000080) |
| #define | RXCSR4_BBP_ID5 FIELD32(0x00007f00) |
| #define | RXCSR4_BBP_ID5_VALID FIELD32(0x00008000) |
| #define | ARCSR0 0x0098 |
| #define | ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff) |
| #define | ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00) |
| #define | ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000) |
| #define | ARCSR0_AR_BBP_ID1 FIELD32(0xff000000) |
| #define | ARCSR1 0x009c |
| #define | ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff) |
| #define | ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00) |
| #define | ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000) |
| #define | ARCSR1_AR_BBP_ID3 FIELD32(0xff000000) |
| #define | PCICSR 0x008c |
| #define | PCICSR_BIG_ENDIAN FIELD32(0x00000001) |
| #define | PCICSR_RX_TRESHOLD FIELD32(0x00000006) |
| #define | PCICSR_TX_TRESHOLD FIELD32(0x00000018) |
| #define | PCICSR_BURST_LENTH FIELD32(0x00000060) |
| #define | PCICSR_ENABLE_CLK FIELD32(0x00000080) |
| #define | CNT0 0x00a0 |
| #define | CNT0_FCS_ERROR FIELD32(0x0000ffff) |
| #define | TIMECSR2 0x00a8 |
| #define | CNT1 0x00ac |
| #define | CNT2 0x00b0 |
| #define | TIMECSR3 0x00b4 |
| #define | CNT3 0x00b8 |
| #define | CNT4 0x00bc |
| #define | CNT5 0x00c0 |
| #define | PWRCSR0 0x00c4 |
| #define | PSCSR0 0x00c8 |
| #define | PSCSR1 0x00cc |
| #define | PSCSR2 0x00d0 |
| #define | PSCSR3 0x00d4 |
| #define | PWRCSR1 0x00d8 |
| #define | PWRCSR1_SET_STATE FIELD32(0x00000001) |
| #define | PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006) |
| #define | PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018) |
| #define | PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060) |
| #define | PWRCSR1_RF_CURR_STATE FIELD32(0x00000180) |
| #define | PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200) |
| #define | TIMECSR 0x00dc |
| #define | TIMECSR_US_COUNT FIELD32(0x000000ff) |
| #define | TIMECSR_US_64_COUNT FIELD32(0x0000ff00) |
| #define | TIMECSR_BEACON_EXPECT FIELD32(0x00070000) |
| #define | MACCSR0 0x00e0 |
| #define | MACCSR1 0x00e4 |
| #define | MACCSR1_KICK_RX FIELD32(0x00000001) |
| #define | MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002) |
| #define | MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004) |
| #define | MACCSR1_AUTO_TXBBP FIELD32(0x00000008) |
| #define | MACCSR1_AUTO_RXBBP FIELD32(0x00000010) |
| #define | MACCSR1_LOOPBACK FIELD32(0x00000060) |
| #define | MACCSR1_INTERSIL_IF FIELD32(0x00000080) |
| #define | RALINKCSR 0x00e8 |
| #define | RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff) |
| #define | RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00) |
| #define | RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000) |
| #define | RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000) |
| #define | BCNCSR 0x00ec |
| #define | BCNCSR_CHANGE FIELD32(0x00000001) |
| #define | BCNCSR_DELTATIME FIELD32(0x0000001e) |
| #define | BCNCSR_NUM_BEACON FIELD32(0x00001fe0) |
| #define | BCNCSR_MODE FIELD32(0x00006000) |
| #define | BCNCSR_PLUS FIELD32(0x00008000) |
| #define | BBPCSR 0x00f0 |
| #define | BBPCSR_VALUE FIELD32(0x000000ff) |
| #define | BBPCSR_REGNUM FIELD32(0x00007f00) |
| #define | BBPCSR_BUSY FIELD32(0x00008000) |
| #define | BBPCSR_WRITE_CONTROL FIELD32(0x00010000) |
| #define | RFCSR 0x00f4 |
| #define | RFCSR_VALUE FIELD32(0x00ffffff) |
| #define | RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000) |
| #define | RFCSR_IF_SELECT FIELD32(0x20000000) |
| #define | RFCSR_PLL_LD FIELD32(0x40000000) |
| #define | RFCSR_BUSY FIELD32(0x80000000) |
| #define | LEDCSR 0x00f8 |
| #define | LEDCSR_ON_PERIOD FIELD32(0x000000ff) |
| #define | LEDCSR_OFF_PERIOD FIELD32(0x0000ff00) |
| #define | LEDCSR_LINK FIELD32(0x00010000) |
| #define | LEDCSR_ACTIVITY FIELD32(0x00020000) |
| #define | RXPTR 0x0100 |
| #define | TXPTR 0x0104 |
| #define | PRIPTR 0x0108 |
| #define | ATIMPTR 0x010c |
| #define | GPIOCSR 0x0120 |
| #define | GPIOCSR_VAL0 FIELD32(0x00000001) |
| #define | GPIOCSR_VAL1 FIELD32(0x00000002) |
| #define | GPIOCSR_VAL2 FIELD32(0x00000004) |
| #define | GPIOCSR_VAL3 FIELD32(0x00000008) |
| #define | GPIOCSR_VAL4 FIELD32(0x00000010) |
| #define | GPIOCSR_VAL5 FIELD32(0x00000020) |
| #define | GPIOCSR_VAL6 FIELD32(0x00000040) |
| #define | GPIOCSR_VAL7 FIELD32(0x00000080) |
| #define | GPIOCSR_DIR0 FIELD32(0x00000100) |
| #define | GPIOCSR_DIR1 FIELD32(0x00000200) |
| #define | GPIOCSR_DIR2 FIELD32(0x00000400) |
| #define | GPIOCSR_DIR3 FIELD32(0x00000800) |
| #define | GPIOCSR_DIR4 FIELD32(0x00001000) |
| #define | GPIOCSR_DIR5 FIELD32(0x00002000) |
| #define | GPIOCSR_DIR6 FIELD32(0x00004000) |
| #define | GPIOCSR_DIR7 FIELD32(0x00008000) |
| #define | BBPPCSR 0x0124 |
| #define | BCNCSR1 0x0130 |
| #define | BCNCSR1_PRELOAD FIELD32(0x0000ffff) |
| #define | MACCSR2 0x0134 |
| #define | MACCSR2_DELAY FIELD32(0x000000ff) |
| #define | ARCSR2 0x013c |
| #define | ARCSR2_SIGNAL FIELD32(0x000000ff) |
| #define | ARCSR2_SERVICE FIELD32(0x0000ff00) |
| #define | ARCSR2_LENGTH_LOW FIELD32(0x00ff0000) |
| #define | ARCSR2_LENGTH FIELD32(0xffff0000) |
| #define | ARCSR3 0x0140 |
| #define | ARCSR3_SIGNAL FIELD32(0x000000ff) |
| #define | ARCSR3_SERVICE FIELD32(0x0000ff00) |
| #define | ARCSR3_LENGTH FIELD32(0xffff0000) |
| #define | ARCSR4 0x0144 |
| #define | ARCSR4_SIGNAL FIELD32(0x000000ff) |
| #define | ARCSR4_SERVICE FIELD32(0x0000ff00) |
| #define | ARCSR4_LENGTH FIELD32(0xffff0000) |
| #define | ARCSR5 0x0148 |
| #define | ARCSR5_SIGNAL FIELD32(0x000000ff) |
| #define | ARCSR5_SERVICE FIELD32(0x0000ff00) |
| #define | ARCSR5_LENGTH FIELD32(0xffff0000) |
| #define | BBP_R1_TX_ANTENNA FIELD8(0x03) |
| #define | BBP_R4_RX_ANTENNA FIELD8(0x06) |
| #define | RF1_TUNER FIELD32(0x00020000) |
| #define | RF3_TUNER FIELD32(0x00000100) |
| #define | RF3_TXPOWER FIELD32(0x00003e00) |
| #define | EEPROM_MAC_ADDR_0 0x0002 |
| #define | EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) |
| #define | EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) |
| #define | EEPROM_MAC_ADDR1 0x0003 |
| #define | EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) |
| #define | EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) |
| #define | EEPROM_MAC_ADDR_2 0x0004 |
| #define | EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) |
| #define | EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) |
| #define | EEPROM_ANTENNA 0x0b |
| #define | EEPROM_ANTENNA_NUM FIELD16(0x0003) |
| #define | EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) |
| #define | EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) |
| #define | EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040) |
| #define | EEPROM_ANTENNA_LED_MODE FIELD16(0x0180) |
| #define | EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200) |
| #define | EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) |
| #define | EEPROM_BBP_START 0x0c |
| #define | EEPROM_BBP_SIZE 7 |
| #define | EEPROM_BBP_VALUE FIELD16(0x00ff) |
| #define | EEPROM_BBP_REG_ID FIELD16(0xff00) |
| #define | EEPROM_TXPOWER_START 0x13 |
| #define | EEPROM_TXPOWER_SIZE 7 |
| #define | EEPROM_TXPOWER_1 FIELD16(0x00ff) |
| #define | EEPROM_TXPOWER_2 FIELD16(0xff00) |
| #define | TXD_DESC_SIZE (8 * sizeof(__le32)) |
| #define | RXD_DESC_SIZE (8 * sizeof(__le32)) |
| #define | TXD_W0_OWNER_NIC FIELD32(0x00000001) |
| #define | TXD_W0_VALID FIELD32(0x00000002) |
| #define | TXD_W0_RESULT FIELD32(0x0000001c) |
| #define | TXD_W0_RETRY_COUNT FIELD32(0x000000e0) |
| #define | TXD_W0_MORE_FRAG FIELD32(0x00000100) |
| #define | TXD_W0_ACK FIELD32(0x00000200) |
| #define | TXD_W0_TIMESTAMP FIELD32(0x00000400) |
| #define | TXD_W0_RTS FIELD32(0x00000800) |
| #define | TXD_W0_IFS FIELD32(0x00006000) |
| #define | TXD_W0_RETRY_MODE FIELD32(0x00008000) |
| #define | TXD_W0_AGC FIELD32(0x00ff0000) |
| #define | TXD_W0_R2 FIELD32(0xff000000) |
| #define | TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) |
| #define | TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) |
| #define | TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000) |
| #define | TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff) |
| #define | TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00) |
| #define | TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000) |
| #define | TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000) |
| #define | TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000) |
| #define | TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000) |
| #define | TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff) |
| #define | TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00) |
| #define | TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000) |
| #define | TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000) |
| #define | TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000) |
| #define | TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000) |
| #define | TXD_W5_BBCR4 FIELD32(0x0000ffff) |
| #define | TXD_W5_AGC_REG FIELD32(0x007f0000) |
| #define | TXD_W5_AGC_REG_VALID FIELD32(0x00800000) |
| #define | TXD_W5_XXX_REG FIELD32(0x7f000000) |
| #define | TXD_W5_XXX_REG_VALID FIELD32(0x80000000) |
| #define | TXD_W6_SK_BUFF FIELD32(0xffffffff) |
| #define | TXD_W7_RESERVED FIELD32(0xffffffff) |
| #define | RXD_W0_OWNER_NIC FIELD32(0x00000001) |
| #define | RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) |
| #define | RXD_W0_MULTICAST FIELD32(0x00000004) |
| #define | RXD_W0_BROADCAST FIELD32(0x00000008) |
| #define | RXD_W0_MY_BSS FIELD32(0x00000010) |
| #define | RXD_W0_CRC_ERROR FIELD32(0x00000020) |
| #define | RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) |
| #define | RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000) |
| #define | RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) |
| #define | RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) |
| #define | RXD_W2_BBR0 FIELD32(0x00ff0000) |
| #define | RXD_W2_SIGNAL FIELD32(0xff000000) |
| #define | RXD_W3_RSSI FIELD32(0x000000ff) |
| #define | RXD_W3_BBR3 FIELD32(0x0000ff00) |
| #define | RXD_W3_BBR4 FIELD32(0x00ff0000) |
| #define | RXD_W3_BBR5 FIELD32(0xff000000) |
| #define | RXD_W4_RX_END_TIME FIELD32(0xffffffff) |
| #define | RXD_W5_RESERVED FIELD32(0xffffffff) |
| #define | RXD_W6_RESERVED FIELD32(0xffffffff) |
| #define | RXD_W7_RESERVED FIELD32(0xffffffff) |
| #define | MIN_TXPOWER 31 |
| #define | MAX_TXPOWER 62 |
| #define | DEFAULT_TXPOWER 39 |
| #define | __CLAMP_TX(__txpower) clamp_t(char, (__txpower), MIN_TXPOWER, MAX_TXPOWER) |
| #define | TXPOWER_FROM_DEV(__txpower) ((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER) |
| #define | TXPOWER_TO_DEV(__txpower) (MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER)) |
| #define __CLAMP_TX | ( | __txpower | ) | clamp_t(char, (__txpower), MIN_TXPOWER, MAX_TXPOWER) |
Definition at line 954 of file rt2400pci.h.
| #define ARCSR0 0x0098 |
Definition at line 442 of file rt2400pci.h.
| #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff) |
Definition at line 443 of file rt2400pci.h.
| #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000) |
Definition at line 445 of file rt2400pci.h.
| #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00) |
Definition at line 444 of file rt2400pci.h.
| #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000) |
Definition at line 446 of file rt2400pci.h.
| #define ARCSR1 0x009c |
Definition at line 453 of file rt2400pci.h.
| #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff) |
Definition at line 454 of file rt2400pci.h.
| #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000) |
Definition at line 456 of file rt2400pci.h.
| #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00) |
Definition at line 455 of file rt2400pci.h.
| #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000) |
Definition at line 457 of file rt2400pci.h.
| #define ARCSR2 0x013c |
Definition at line 706 of file rt2400pci.h.
| #define ARCSR2_LENGTH FIELD32(0xffff0000) |
Definition at line 710 of file rt2400pci.h.
| #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000) |
Definition at line 709 of file rt2400pci.h.
| #define ARCSR2_SERVICE FIELD32(0x0000ff00) |
Definition at line 708 of file rt2400pci.h.
| #define ARCSR2_SIGNAL FIELD32(0x000000ff) |
Definition at line 707 of file rt2400pci.h.
| #define ARCSR3 0x0140 |
Definition at line 715 of file rt2400pci.h.
| #define ARCSR3_LENGTH FIELD32(0xffff0000) |
Definition at line 718 of file rt2400pci.h.
| #define ARCSR3_SERVICE FIELD32(0x0000ff00) |
Definition at line 717 of file rt2400pci.h.
| #define ARCSR3_SIGNAL FIELD32(0x000000ff) |
Definition at line 716 of file rt2400pci.h.
| #define ARCSR4 0x0144 |
Definition at line 723 of file rt2400pci.h.
| #define ARCSR4_LENGTH FIELD32(0xffff0000) |
Definition at line 726 of file rt2400pci.h.
| #define ARCSR4_SERVICE FIELD32(0x0000ff00) |
Definition at line 725 of file rt2400pci.h.
| #define ARCSR4_SIGNAL FIELD32(0x000000ff) |
Definition at line 724 of file rt2400pci.h.
| #define ARCSR5 0x0148 |
Definition at line 731 of file rt2400pci.h.
| #define ARCSR5_LENGTH FIELD32(0xffff0000) |
Definition at line 734 of file rt2400pci.h.
| #define ARCSR5_SERVICE FIELD32(0x0000ff00) |
Definition at line 733 of file rt2400pci.h.
| #define ARCSR5_SIGNAL FIELD32(0x000000ff) |
Definition at line 732 of file rt2400pci.h.
| #define ATIMPTR 0x010c |
Definition at line 655 of file rt2400pci.h.
| #define BBP_BASE 0x0000 |
Definition at line 49 of file rt2400pci.h.
| #define BBP_R1_TX_ANTENNA FIELD8(0x03) |
Definition at line 744 of file rt2400pci.h.
| #define BBP_R4_RX_ANTENNA FIELD8(0x06) |
Definition at line 749 of file rt2400pci.h.
| #define BBP_SIZE 0x0020 |
Definition at line 50 of file rt2400pci.h.
| #define BBPCSR 0x00f0 |
Definition at line 611 of file rt2400pci.h.
| #define BBPCSR_BUSY FIELD32(0x00008000) |
Definition at line 614 of file rt2400pci.h.
| #define BBPCSR_REGNUM FIELD32(0x00007f00) |
Definition at line 613 of file rt2400pci.h.
| #define BBPCSR_VALUE FIELD32(0x000000ff) |
Definition at line 612 of file rt2400pci.h.
| #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000) |
Definition at line 615 of file rt2400pci.h.
| #define BBPPCSR 0x0124 |
Definition at line 687 of file rt2400pci.h.
| #define BCNCSR 0x00ec |
Definition at line 593 of file rt2400pci.h.
| #define BCNCSR1 0x0130 |
Definition at line 693 of file rt2400pci.h.
| #define BCNCSR1_PRELOAD FIELD32(0x0000ffff) |
Definition at line 694 of file rt2400pci.h.
| #define BCNCSR_CHANGE FIELD32(0x00000001) |
Definition at line 594 of file rt2400pci.h.
| #define BCNCSR_DELTATIME FIELD32(0x0000001e) |
Definition at line 595 of file rt2400pci.h.
| #define BCNCSR_MODE FIELD32(0x00006000) |
Definition at line 597 of file rt2400pci.h.
| #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0) |
Definition at line 596 of file rt2400pci.h.
| #define BCNCSR_PLUS FIELD32(0x00008000) |
Definition at line 598 of file rt2400pci.h.
| #define CNT0 0x00a0 |
Definition at line 485 of file rt2400pci.h.
| #define CNT0_FCS_ERROR FIELD32(0x0000ffff) |
Definition at line 486 of file rt2400pci.h.
| #define CNT1 0x00ac |
Definition at line 497 of file rt2400pci.h.
| #define CNT2 0x00b0 |
Definition at line 498 of file rt2400pci.h.
| #define CNT3 0x00b8 |
Definition at line 500 of file rt2400pci.h.
| #define CNT4 0x00bc |
Definition at line 501 of file rt2400pci.h.
| #define CNT5 0x00c0 |
Definition at line 502 of file rt2400pci.h.
| #define CSR0 0x0000 |
Definition at line 67 of file rt2400pci.h.
| #define CSR0_REVISION FIELD32(0x0000ffff) |
Definition at line 68 of file rt2400pci.h.
| #define CSR1 0x0004 |
Definition at line 76 of file rt2400pci.h.
| #define CSR11 0x002c |
Definition at line 173 of file rt2400pci.h.
| #define CSR11_CWMAX FIELD32(0x000000f0) |
Definition at line 175 of file rt2400pci.h.
| #define CSR11_CWMIN FIELD32(0x0000000f) |
Definition at line 174 of file rt2400pci.h.
| #define CSR11_LONG_RETRY FIELD32(0x00ff0000) |
Definition at line 177 of file rt2400pci.h.
| #define CSR11_SHORT_RETRY FIELD32(0xff000000) |
Definition at line 178 of file rt2400pci.h.
| #define CSR11_SLOT_TIME FIELD32(0x00001f00) |
Definition at line 176 of file rt2400pci.h.
| #define CSR12 0x0030 |
Definition at line 186 of file rt2400pci.h.
| #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff) |
Definition at line 187 of file rt2400pci.h.
| #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000) |
Definition at line 188 of file rt2400pci.h.
| #define CSR13 0x0034 |
Definition at line 196 of file rt2400pci.h.
| #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff) |
Definition at line 197 of file rt2400pci.h.
| #define CSR13_CFP_PERIOD FIELD32(0x00ff0000) |
Definition at line 198 of file rt2400pci.h.
| #define CSR14 0x0038 |
Definition at line 211 of file rt2400pci.h.
| #define CSR14_BEACON_GEN FIELD32(0x00000040) |
Definition at line 217 of file rt2400pci.h.
| #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00) |
Definition at line 218 of file rt2400pci.h.
| #define CSR14_TATIMW FIELD32(0x00000020) |
Definition at line 216 of file rt2400pci.h.
| #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000) |
Definition at line 219 of file rt2400pci.h.
| #define CSR14_TBCN FIELD32(0x00000008) |
Definition at line 214 of file rt2400pci.h.
| #define CSR14_TCFP FIELD32(0x00000010) |
Definition at line 215 of file rt2400pci.h.
| #define CSR14_TSF_COUNT FIELD32(0x00000001) |
Definition at line 212 of file rt2400pci.h.
| #define CSR14_TSF_SYNC FIELD32(0x00000006) |
Definition at line 213 of file rt2400pci.h.
| #define CSR15 0x003c |
Definition at line 227 of file rt2400pci.h.
| #define CSR15_ATIMW FIELD32(0x00000002) |
Definition at line 229 of file rt2400pci.h.
| #define CSR15_BEACON_SENT FIELD32(0x00000004) |
Definition at line 230 of file rt2400pci.h.
| #define CSR15_CFP FIELD32(0x00000001) |
Definition at line 228 of file rt2400pci.h.
| #define CSR16 0x0040 |
Definition at line 235 of file rt2400pci.h.
| #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff) |
Definition at line 236 of file rt2400pci.h.
| #define CSR17 0x0044 |
Definition at line 241 of file rt2400pci.h.
| #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff) |
Definition at line 242 of file rt2400pci.h.
| #define CSR18 0x0048 |
Definition at line 249 of file rt2400pci.h.
| #define CSR18_PIFS FIELD32(0xffff0000) |
Definition at line 251 of file rt2400pci.h.
| #define CSR18_SIFS FIELD32(0x0000ffff) |
Definition at line 250 of file rt2400pci.h.
| #define CSR19 0x004c |
Definition at line 258 of file rt2400pci.h.
| #define CSR19_DIFS FIELD32(0x0000ffff) |
Definition at line 259 of file rt2400pci.h.
| #define CSR19_EIFS FIELD32(0xffff0000) |
Definition at line 260 of file rt2400pci.h.
| #define CSR1_BBP_RESET FIELD32(0x00000002) |
Definition at line 78 of file rt2400pci.h.
| #define CSR1_HOST_READY FIELD32(0x00000004) |
Definition at line 79 of file rt2400pci.h.
| #define CSR1_SOFT_RESET FIELD32(0x00000001) |
Definition at line 77 of file rt2400pci.h.
| #define CSR2 0x0008 |
Definition at line 84 of file rt2400pci.h.
| #define CSR20 0x0050 |
Definition at line 268 of file rt2400pci.h.
| #define CSR20_AUTOWAKE FIELD32(0x01000000) |
Definition at line 271 of file rt2400pci.h.
| #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff) |
Definition at line 269 of file rt2400pci.h.
| #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000) |
Definition at line 270 of file rt2400pci.h.
| #define CSR21 0x0054 |
Definition at line 278 of file rt2400pci.h.
| #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004) |
Definition at line 281 of file rt2400pci.h.
| #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002) |
Definition at line 280 of file rt2400pci.h.
| #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008) |
Definition at line 282 of file rt2400pci.h.
| #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010) |
Definition at line 283 of file rt2400pci.h.
| #define CSR21_RELOAD FIELD32(0x00000001) |
Definition at line 279 of file rt2400pci.h.
| #define CSR21_TYPE_93C46 FIELD32(0x00000020) |
Definition at line 284 of file rt2400pci.h.
| #define CSR22 0x0058 |
Definition at line 291 of file rt2400pci.h.
| #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff) |
Definition at line 292 of file rt2400pci.h.
| #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000) |
Definition at line 293 of file rt2400pci.h.
| #define CSR3 0x000c |
Definition at line 89 of file rt2400pci.h.
| #define CSR3_BYTE0 FIELD32(0x000000ff) |
Definition at line 90 of file rt2400pci.h.
| #define CSR3_BYTE1 FIELD32(0x0000ff00) |
Definition at line 91 of file rt2400pci.h.
| #define CSR3_BYTE2 FIELD32(0x00ff0000) |
Definition at line 92 of file rt2400pci.h.
| #define CSR3_BYTE3 FIELD32(0xff000000) |
Definition at line 93 of file rt2400pci.h.
| #define CSR4 0x0010 |
Definition at line 98 of file rt2400pci.h.
| #define CSR4_BYTE4 FIELD32(0x000000ff) |
Definition at line 99 of file rt2400pci.h.
| #define CSR4_BYTE5 FIELD32(0x0000ff00) |
Definition at line 100 of file rt2400pci.h.
| #define CSR5 0x0014 |
Definition at line 105 of file rt2400pci.h.
| #define CSR5_BYTE0 FIELD32(0x000000ff) |
Definition at line 106 of file rt2400pci.h.
| #define CSR5_BYTE1 FIELD32(0x0000ff00) |
Definition at line 107 of file rt2400pci.h.
| #define CSR5_BYTE2 FIELD32(0x00ff0000) |
Definition at line 108 of file rt2400pci.h.
| #define CSR5_BYTE3 FIELD32(0xff000000) |
Definition at line 109 of file rt2400pci.h.
| #define CSR6 0x0018 |
Definition at line 114 of file rt2400pci.h.
| #define CSR6_BYTE4 FIELD32(0x000000ff) |
Definition at line 115 of file rt2400pci.h.
| #define CSR6_BYTE5 FIELD32(0x0000ff00) |
Definition at line 116 of file rt2400pci.h.
| #define CSR7 0x001c |
Definition at line 129 of file rt2400pci.h.
| #define CSR7_RXDONE FIELD32(0x00000040) |
Definition at line 136 of file rt2400pci.h.
| #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004) |
Definition at line 132 of file rt2400pci.h.
| #define CSR7_TBCN_EXPIRE FIELD32(0x00000001) |
Definition at line 130 of file rt2400pci.h.
| #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002) |
Definition at line 131 of file rt2400pci.h.
| #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010) |
Definition at line 134 of file rt2400pci.h.
| #define CSR7_TXDONE_PRIORING FIELD32(0x00000020) |
Definition at line 135 of file rt2400pci.h.
| #define CSR7_TXDONE_TXRING FIELD32(0x00000008) |
Definition at line 133 of file rt2400pci.h.
| #define CSR8 0x0020 |
Definition at line 149 of file rt2400pci.h.
| #define CSR8_RXDONE FIELD32(0x00000040) |
Definition at line 156 of file rt2400pci.h.
| #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004) |
Definition at line 152 of file rt2400pci.h.
| #define CSR8_TBCN_EXPIRE FIELD32(0x00000001) |
Definition at line 150 of file rt2400pci.h.
| #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002) |
Definition at line 151 of file rt2400pci.h.
| #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010) |
Definition at line 154 of file rt2400pci.h.
| #define CSR8_TXDONE_PRIORING FIELD32(0x00000020) |
Definition at line 155 of file rt2400pci.h.
| #define CSR8_TXDONE_TXRING FIELD32(0x00000008) |
Definition at line 153 of file rt2400pci.h.
| #define CSR9 0x0024 |
Definition at line 162 of file rt2400pci.h.
| #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80) |
Definition at line 163 of file rt2400pci.h.
| #define CSR_REG_BASE 0x0000 |
Definition at line 45 of file rt2400pci.h.
| #define CSR_REG_SIZE 0x014c |
Definition at line 46 of file rt2400pci.h.
| #define DEFAULT_RSSI_OFFSET 100 |
Definition at line 40 of file rt2400pci.h.
| #define DEFAULT_TXPOWER 39 |
Definition at line 952 of file rt2400pci.h.
| #define EEPROM_ANTENNA 0x0b |
Definition at line 794 of file rt2400pci.h.
| #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) |
Definition at line 801 of file rt2400pci.h.
| #define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180) |
Definition at line 799 of file rt2400pci.h.
| #define EEPROM_ANTENNA_NUM FIELD16(0x0003) |
Definition at line 795 of file rt2400pci.h.
| #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040) |
Definition at line 798 of file rt2400pci.h.
| #define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200) |
Definition at line 800 of file rt2400pci.h.
| #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) |
Definition at line 797 of file rt2400pci.h.
| #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) |
Definition at line 796 of file rt2400pci.h.
| #define EEPROM_BASE 0x0000 |
Definition at line 47 of file rt2400pci.h.
| #define EEPROM_BBP_REG_ID FIELD16(0xff00) |
Definition at line 809 of file rt2400pci.h.
| #define EEPROM_BBP_SIZE 7 |
Definition at line 807 of file rt2400pci.h.
| #define EEPROM_BBP_START 0x0c |
Definition at line 806 of file rt2400pci.h.
| #define EEPROM_BBP_VALUE FIELD16(0x00ff) |
Definition at line 808 of file rt2400pci.h.
| #define EEPROM_MAC_ADDR1 0x0003 |
Definition at line 777 of file rt2400pci.h.
| #define EEPROM_MAC_ADDR_0 0x0002 |
Definition at line 774 of file rt2400pci.h.
| #define EEPROM_MAC_ADDR_2 0x0004 |
Definition at line 780 of file rt2400pci.h.
| #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) |
Definition at line 775 of file rt2400pci.h.
| #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) |
Definition at line 776 of file rt2400pci.h.
| #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) |
Definition at line 778 of file rt2400pci.h.
| #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) |
Definition at line 779 of file rt2400pci.h.
| #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) |
Definition at line 781 of file rt2400pci.h.
| #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) |
Definition at line 782 of file rt2400pci.h.
| #define EEPROM_SIZE 0x0100 |
Definition at line 48 of file rt2400pci.h.
| #define EEPROM_TXPOWER_1 FIELD16(0x00ff) |
Definition at line 816 of file rt2400pci.h.
| #define EEPROM_TXPOWER_2 FIELD16(0xff00) |
Definition at line 817 of file rt2400pci.h.
| #define EEPROM_TXPOWER_SIZE 7 |
Definition at line 815 of file rt2400pci.h.
| #define EEPROM_TXPOWER_START 0x13 |
Definition at line 814 of file rt2400pci.h.
| #define GPIOCSR 0x0120 |
Definition at line 666 of file rt2400pci.h.
| #define GPIOCSR_DIR0 FIELD32(0x00000100) |
Definition at line 675 of file rt2400pci.h.
| #define GPIOCSR_DIR1 FIELD32(0x00000200) |
Definition at line 676 of file rt2400pci.h.
| #define GPIOCSR_DIR2 FIELD32(0x00000400) |
Definition at line 677 of file rt2400pci.h.
| #define GPIOCSR_DIR3 FIELD32(0x00000800) |
Definition at line 678 of file rt2400pci.h.
| #define GPIOCSR_DIR4 FIELD32(0x00001000) |
Definition at line 679 of file rt2400pci.h.
| #define GPIOCSR_DIR5 FIELD32(0x00002000) |
Definition at line 680 of file rt2400pci.h.
| #define GPIOCSR_DIR6 FIELD32(0x00004000) |
Definition at line 681 of file rt2400pci.h.
| #define GPIOCSR_DIR7 FIELD32(0x00008000) |
Definition at line 682 of file rt2400pci.h.
| #define GPIOCSR_VAL0 FIELD32(0x00000001) |
Definition at line 667 of file rt2400pci.h.
| #define GPIOCSR_VAL1 FIELD32(0x00000002) |
Definition at line 668 of file rt2400pci.h.
| #define GPIOCSR_VAL2 FIELD32(0x00000004) |
Definition at line 669 of file rt2400pci.h.
| #define GPIOCSR_VAL3 FIELD32(0x00000008) |
Definition at line 670 of file rt2400pci.h.
| #define GPIOCSR_VAL4 FIELD32(0x00000010) |
Definition at line 671 of file rt2400pci.h.
| #define GPIOCSR_VAL5 FIELD32(0x00000020) |
Definition at line 672 of file rt2400pci.h.
| #define GPIOCSR_VAL6 FIELD32(0x00000040) |
Definition at line 673 of file rt2400pci.h.
| #define GPIOCSR_VAL7 FIELD32(0x00000080) |
Definition at line 674 of file rt2400pci.h.
| #define LEDCSR 0x00f8 |
Definition at line 639 of file rt2400pci.h.
| #define LEDCSR_ACTIVITY FIELD32(0x00020000) |
Definition at line 643 of file rt2400pci.h.
| #define LEDCSR_LINK FIELD32(0x00010000) |
Definition at line 642 of file rt2400pci.h.
| #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00) |
Definition at line 641 of file rt2400pci.h.
| #define LEDCSR_ON_PERIOD FIELD32(0x000000ff) |
Definition at line 640 of file rt2400pci.h.
| #define MACCSR0 0x00e0 |
Definition at line 553 of file rt2400pci.h.
| #define MACCSR1 0x00e4 |
Definition at line 565 of file rt2400pci.h.
| #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010) |
Definition at line 570 of file rt2400pci.h.
| #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008) |
Definition at line 569 of file rt2400pci.h.
| #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004) |
Definition at line 568 of file rt2400pci.h.
| #define MACCSR1_INTERSIL_IF FIELD32(0x00000080) |
Definition at line 572 of file rt2400pci.h.
| #define MACCSR1_KICK_RX FIELD32(0x00000001) |
Definition at line 566 of file rt2400pci.h.
| #define MACCSR1_LOOPBACK FIELD32(0x00000060) |
Definition at line 571 of file rt2400pci.h.
| #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002) |
Definition at line 567 of file rt2400pci.h.
| #define MACCSR2 0x0134 |
Definition at line 700 of file rt2400pci.h.
| #define MACCSR2_DELAY FIELD32(0x000000ff) |
Definition at line 701 of file rt2400pci.h.
| #define MAX_TXPOWER 62 |
Definition at line 951 of file rt2400pci.h.
| #define MIN_TXPOWER 31 |
Definition at line 950 of file rt2400pci.h.
| #define NUM_TX_QUEUES 2 |
Definition at line 57 of file rt2400pci.h.
| #define PCICSR 0x008c |
Definition at line 474 of file rt2400pci.h.
| #define PCICSR_BIG_ENDIAN FIELD32(0x00000001) |
Definition at line 475 of file rt2400pci.h.
| #define PCICSR_BURST_LENTH FIELD32(0x00000060) |
Definition at line 478 of file rt2400pci.h.
| #define PCICSR_ENABLE_CLK FIELD32(0x00000080) |
Definition at line 479 of file rt2400pci.h.
| #define PCICSR_RX_TRESHOLD FIELD32(0x00000006) |
Definition at line 476 of file rt2400pci.h.
| #define PCICSR_TX_TRESHOLD FIELD32(0x00000018) |
Definition at line 477 of file rt2400pci.h.
| #define PRIPTR 0x0108 |
Definition at line 654 of file rt2400pci.h.
| #define PSCSR0 0x00c8 |
Definition at line 516 of file rt2400pci.h.
| #define PSCSR1 0x00cc |
Definition at line 517 of file rt2400pci.h.
| #define PSCSR2 0x00d0 |
Definition at line 518 of file rt2400pci.h.
| #define PSCSR3 0x00d4 |
Definition at line 519 of file rt2400pci.h.
| #define PWRCSR0 0x00c4 |
Definition at line 511 of file rt2400pci.h.
| #define PWRCSR1 0x00d8 |
Definition at line 531 of file rt2400pci.h.
| #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060) |
Definition at line 535 of file rt2400pci.h.
| #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006) |
Definition at line 533 of file rt2400pci.h.
| #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200) |
Definition at line 537 of file rt2400pci.h.
| #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180) |
Definition at line 536 of file rt2400pci.h.
| #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018) |
Definition at line 534 of file rt2400pci.h.
| #define PWRCSR1_SET_STATE FIELD32(0x00000001) |
Definition at line 532 of file rt2400pci.h.
| #define RALINKCSR 0x00e8 |
Definition at line 579 of file rt2400pci.h.
| #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff) |
Definition at line 580 of file rt2400pci.h.
| #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000) |
Definition at line 582 of file rt2400pci.h.
| #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00) |
Definition at line 581 of file rt2400pci.h.
| #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000) |
Definition at line 583 of file rt2400pci.h.
| #define RF1_TUNER FIELD32(0x00020000) |
Definition at line 758 of file rt2400pci.h.
| #define RF2420 0x0000 |
Definition at line 33 of file rt2400pci.h.
| #define RF2421 0x0001 |
Definition at line 34 of file rt2400pci.h.
| #define RF3_TUNER FIELD32(0x00000100) |
Definition at line 763 of file rt2400pci.h.
| #define RF3_TXPOWER FIELD32(0x00003e00) |
Definition at line 764 of file rt2400pci.h.
| #define RF_BASE 0x0004 |
Definition at line 51 of file rt2400pci.h.
| #define RF_SIZE 0x000c |
Definition at line 52 of file rt2400pci.h.
| #define RFCSR 0x00f4 |
Definition at line 625 of file rt2400pci.h.
| #define RFCSR_BUSY FIELD32(0x80000000) |
Definition at line 630 of file rt2400pci.h.
| #define RFCSR_IF_SELECT FIELD32(0x20000000) |
Definition at line 628 of file rt2400pci.h.
| #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000) |
Definition at line 627 of file rt2400pci.h.
| #define RFCSR_PLL_LD FIELD32(0x40000000) |
Definition at line 629 of file rt2400pci.h.
| #define RFCSR_VALUE FIELD32(0x00ffffff) |
Definition at line 626 of file rt2400pci.h.
| #define RXCSR0 0x0080 |
Definition at line 386 of file rt2400pci.h.
| #define RXCSR0_DISABLE_RX FIELD32(0x00000001) |
Definition at line 387 of file rt2400pci.h.
| #define RXCSR0_DROP_CONTROL FIELD32(0x00000008) |
Definition at line 390 of file rt2400pci.h.
| #define RXCSR0_DROP_CRC FIELD32(0x00000002) |
Definition at line 388 of file rt2400pci.h.
| #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010) |
Definition at line 391 of file rt2400pci.h.
| #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004) |
Definition at line 389 of file rt2400pci.h.
| #define RXCSR0_DROP_TODS FIELD32(0x00000020) |
Definition at line 392 of file rt2400pci.h.
| #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040) |
Definition at line 393 of file rt2400pci.h.
| #define RXCSR0_PASS_CRC FIELD32(0x00000080) |
Definition at line 394 of file rt2400pci.h.
| #define RXCSR1 0x0084 |
Definition at line 401 of file rt2400pci.h.
| #define RXCSR1_NUM_RXD FIELD32(0x0000ff00) |
Definition at line 403 of file rt2400pci.h.
| #define RXCSR1_RXD_SIZE FIELD32(0x000000ff) |
Definition at line 402 of file rt2400pci.h.
| #define RXCSR2 0x0088 |
Definition at line 408 of file rt2400pci.h.
| #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff) |
Definition at line 409 of file rt2400pci.h.
| #define RXCSR3 0x0090 |
Definition at line 416 of file rt2400pci.h.
| #define RXCSR3_BBP_ID0 FIELD32(0x0000007f) |
Definition at line 417 of file rt2400pci.h.
| #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080) |
Definition at line 418 of file rt2400pci.h.
| #define RXCSR3_BBP_ID1 FIELD32(0x00007f00) |
Definition at line 419 of file rt2400pci.h.
| #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000) |
Definition at line 420 of file rt2400pci.h.
| #define RXCSR3_BBP_ID2 FIELD32(0x007f0000) |
Definition at line 421 of file rt2400pci.h.
| #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000) |
Definition at line 422 of file rt2400pci.h.
| #define RXCSR3_BBP_ID3 FIELD32(0x7f000000) |
Definition at line 423 of file rt2400pci.h.
| #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000) |
Definition at line 424 of file rt2400pci.h.
| #define RXCSR4 0x0094 |
Definition at line 431 of file rt2400pci.h.
| #define RXCSR4_BBP_ID4 FIELD32(0x0000007f) |
Definition at line 432 of file rt2400pci.h.
| #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080) |
Definition at line 433 of file rt2400pci.h.
| #define RXCSR4_BBP_ID5 FIELD32(0x00007f00) |
Definition at line 434 of file rt2400pci.h.
| #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000) |
Definition at line 435 of file rt2400pci.h.
Definition at line 823 of file rt2400pci.h.
| #define RXD_W0_BROADCAST FIELD32(0x00000008) |
Definition at line 903 of file rt2400pci.h.
| #define RXD_W0_CRC_ERROR FIELD32(0x00000020) |
Definition at line 905 of file rt2400pci.h.
| #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000) |
Definition at line 907 of file rt2400pci.h.
| #define RXD_W0_MULTICAST FIELD32(0x00000004) |
Definition at line 902 of file rt2400pci.h.
| #define RXD_W0_MY_BSS FIELD32(0x00000010) |
Definition at line 904 of file rt2400pci.h.
| #define RXD_W0_OWNER_NIC FIELD32(0x00000001) |
Definition at line 900 of file rt2400pci.h.
| #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) |
Definition at line 906 of file rt2400pci.h.
| #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) |
Definition at line 901 of file rt2400pci.h.
| #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) |
Definition at line 912 of file rt2400pci.h.
| #define RXD_W2_BBR0 FIELD32(0x00ff0000) |
Definition at line 918 of file rt2400pci.h.
| #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) |
Definition at line 917 of file rt2400pci.h.
| #define RXD_W2_SIGNAL FIELD32(0xff000000) |
Definition at line 919 of file rt2400pci.h.
| #define RXD_W3_BBR3 FIELD32(0x0000ff00) |
Definition at line 925 of file rt2400pci.h.
| #define RXD_W3_BBR4 FIELD32(0x00ff0000) |
Definition at line 926 of file rt2400pci.h.
| #define RXD_W3_BBR5 FIELD32(0xff000000) |
Definition at line 927 of file rt2400pci.h.
| #define RXD_W3_RSSI FIELD32(0x000000ff) |
Definition at line 924 of file rt2400pci.h.
| #define RXD_W4_RX_END_TIME FIELD32(0xffffffff) |
Definition at line 932 of file rt2400pci.h.
| #define RXD_W5_RESERVED FIELD32(0xffffffff) |
Definition at line 937 of file rt2400pci.h.
| #define RXD_W6_RESERVED FIELD32(0xffffffff) |
Definition at line 938 of file rt2400pci.h.
| #define RXD_W7_RESERVED FIELD32(0xffffffff) |
Definition at line 939 of file rt2400pci.h.
| #define RXPTR 0x0100 |
Definition at line 652 of file rt2400pci.h.
| #define TIMECSR 0x00dc |
Definition at line 545 of file rt2400pci.h.
| #define TIMECSR2 0x00a8 |
Definition at line 496 of file rt2400pci.h.
| #define TIMECSR3 0x00b4 |
Definition at line 499 of file rt2400pci.h.
| #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000) |
Definition at line 548 of file rt2400pci.h.
| #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00) |
Definition at line 547 of file rt2400pci.h.
| #define TIMECSR_US_COUNT FIELD32(0x000000ff) |
Definition at line 546 of file rt2400pci.h.
| #define TXCSR0 0x0060 |
Definition at line 307 of file rt2400pci.h.
| #define TXCSR0_ABORT FIELD32(0x00000008) |
Definition at line 311 of file rt2400pci.h.
| #define TXCSR0_KICK_ATIM FIELD32(0x00000002) |
Definition at line 309 of file rt2400pci.h.
| #define TXCSR0_KICK_PRIO FIELD32(0x00000004) |
Definition at line 310 of file rt2400pci.h.
| #define TXCSR0_KICK_TX FIELD32(0x00000001) |
Definition at line 308 of file rt2400pci.h.
| #define TXCSR1 0x0064 |
Definition at line 320 of file rt2400pci.h.
| #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00) |
Definition at line 322 of file rt2400pci.h.
| #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff) |
Definition at line 321 of file rt2400pci.h.
| #define TXCSR1_AUTORESPONDER FIELD32(0x01000000) |
Definition at line 324 of file rt2400pci.h.
| #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000) |
Definition at line 323 of file rt2400pci.h.
| #define TXCSR2 0x0068 |
Definition at line 333 of file rt2400pci.h.
| #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000) |
Definition at line 336 of file rt2400pci.h.
| #define TXCSR2_NUM_PRIO FIELD32(0xff000000) |
Definition at line 337 of file rt2400pci.h.
| #define TXCSR2_NUM_TXD FIELD32(0x0000ff00) |
Definition at line 335 of file rt2400pci.h.
| #define TXCSR2_TXD_SIZE FIELD32(0x000000ff) |
Definition at line 334 of file rt2400pci.h.
| #define TXCSR3 0x006c |
Definition at line 342 of file rt2400pci.h.
| #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff) |
Definition at line 343 of file rt2400pci.h.
| #define TXCSR4 0x0070 |
Definition at line 348 of file rt2400pci.h.
| #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff) |
Definition at line 349 of file rt2400pci.h.
| #define TXCSR5 0x0074 |
Definition at line 354 of file rt2400pci.h.
| #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff) |
Definition at line 355 of file rt2400pci.h.
| #define TXCSR6 0x0078 |
Definition at line 360 of file rt2400pci.h.
| #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff) |
Definition at line 361 of file rt2400pci.h.
| #define TXCSR7 0x007c |
Definition at line 367 of file rt2400pci.h.
| #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001) |
Definition at line 368 of file rt2400pci.h.
Definition at line 822 of file rt2400pci.h.
| #define TXD_W0_ACK FIELD32(0x00000200) |
Definition at line 837 of file rt2400pci.h.
| #define TXD_W0_AGC FIELD32(0x00ff0000) |
Definition at line 842 of file rt2400pci.h.
| #define TXD_W0_IFS FIELD32(0x00006000) |
Definition at line 840 of file rt2400pci.h.
| #define TXD_W0_MORE_FRAG FIELD32(0x00000100) |
Definition at line 836 of file rt2400pci.h.
| #define TXD_W0_OWNER_NIC FIELD32(0x00000001) |
Definition at line 832 of file rt2400pci.h.
| #define TXD_W0_R2 FIELD32(0xff000000) |
Definition at line 843 of file rt2400pci.h.
| #define TXD_W0_RESULT FIELD32(0x0000001c) |
Definition at line 834 of file rt2400pci.h.
| #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0) |
Definition at line 835 of file rt2400pci.h.
| #define TXD_W0_RETRY_MODE FIELD32(0x00008000) |
Definition at line 841 of file rt2400pci.h.
| #define TXD_W0_RTS FIELD32(0x00000800) |
Definition at line 839 of file rt2400pci.h.
| #define TXD_W0_TIMESTAMP FIELD32(0x00000400) |
Definition at line 838 of file rt2400pci.h.
| #define TXD_W0_VALID FIELD32(0x00000002) |
Definition at line 833 of file rt2400pci.h.
| #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) |
Definition at line 848 of file rt2400pci.h.
| #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) |
Definition at line 853 of file rt2400pci.h.
| #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000) |
Definition at line 854 of file rt2400pci.h.
| #define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000) |
Definition at line 872 of file rt2400pci.h.
| #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000) |
Definition at line 871 of file rt2400pci.h.
| #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000) |
Definition at line 869 of file rt2400pci.h.
| #define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00) |
Definition at line 868 of file rt2400pci.h.
| #define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000) |
Definition at line 863 of file rt2400pci.h.
| #define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000) |
Definition at line 865 of file rt2400pci.h.
| #define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000) |
Definition at line 864 of file rt2400pci.h.
| #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff) |
Definition at line 860 of file rt2400pci.h.
| #define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000) |
Definition at line 862 of file rt2400pci.h.
| #define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00) |
Definition at line 861 of file rt2400pci.h.
| #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000) |
Definition at line 870 of file rt2400pci.h.
| #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff) |
Definition at line 867 of file rt2400pci.h.
| #define TXD_W5_AGC_REG FIELD32(0x007f0000) |
Definition at line 878 of file rt2400pci.h.
| #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000) |
Definition at line 879 of file rt2400pci.h.
| #define TXD_W5_BBCR4 FIELD32(0x0000ffff) |
Definition at line 877 of file rt2400pci.h.
| #define TXD_W5_XXX_REG FIELD32(0x7f000000) |
Definition at line 880 of file rt2400pci.h.
| #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000) |
Definition at line 881 of file rt2400pci.h.
| #define TXD_W6_SK_BUFF FIELD32(0xffffffff) |
Definition at line 886 of file rt2400pci.h.
| #define TXD_W7_RESERVED FIELD32(0xffffffff) |
Definition at line 891 of file rt2400pci.h.
| #define TXPOWER_FROM_DEV | ( | __txpower | ) | ((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER) |
Definition at line 957 of file rt2400pci.h.
| #define TXPOWER_TO_DEV | ( | __txpower | ) | (MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER)) |
Definition at line 960 of file rt2400pci.h.
| #define TXPTR 0x0104 |
Definition at line 653 of file rt2400pci.h.
1.8.2