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37 #define RF2525E 0x0004
43 #define RT2560_VERSION_B 2
44 #define RT2560_VERSION_C 3
45 #define RT2560_VERSION_D 4
51 #define DEFAULT_RSSI_OFFSET 121
56 #define CSR_REG_BASE 0x0000
57 #define CSR_REG_SIZE 0x0174
58 #define EEPROM_BASE 0x0000
59 #define EEPROM_SIZE 0x0200
60 #define BBP_BASE 0x0000
61 #define BBP_SIZE 0x0040
62 #define RF_BASE 0x0004
63 #define RF_SIZE 0x0010
68 #define NUM_TX_QUEUES 2
79 #define CSR0_REVISION FIELD32(0x0000ffff)
88 #define CSR1_SOFT_RESET FIELD32(0x00000001)
89 #define CSR1_BBP_RESET FIELD32(0x00000002)
90 #define CSR1_HOST_READY FIELD32(0x00000004)
101 #define CSR3_BYTE0 FIELD32(0x000000ff)
102 #define CSR3_BYTE1 FIELD32(0x0000ff00)
103 #define CSR3_BYTE2 FIELD32(0x00ff0000)
104 #define CSR3_BYTE3 FIELD32(0xff000000)
110 #define CSR4_BYTE4 FIELD32(0x000000ff)
111 #define CSR4_BYTE5 FIELD32(0x0000ff00)
117 #define CSR5_BYTE0 FIELD32(0x000000ff)
118 #define CSR5_BYTE1 FIELD32(0x0000ff00)
119 #define CSR5_BYTE2 FIELD32(0x00ff0000)
120 #define CSR5_BYTE3 FIELD32(0xff000000)
126 #define CSR6_BYTE4 FIELD32(0x000000ff)
127 #define CSR6_BYTE5 FIELD32(0x0000ff00)
155 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
156 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
157 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
158 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
159 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
160 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
161 #define CSR7_RXDONE FIELD32(0x00000040)
162 #define CSR7_DECRYPTION_DONE FIELD32(0x00000080)
163 #define CSR7_ENCRYPTION_DONE FIELD32(0x00000100)
164 #define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200)
165 #define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400)
166 #define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
167 #define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
168 #define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
169 #define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000)
170 #define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000)
171 #define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
172 #define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
173 #define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
174 #define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
201 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
202 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
203 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
204 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
205 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
206 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
207 #define CSR8_RXDONE FIELD32(0x00000040)
208 #define CSR8_DECRYPTION_DONE FIELD32(0x00000080)
209 #define CSR8_ENCRYPTION_DONE FIELD32(0x00000100)
210 #define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200)
211 #define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400)
212 #define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
213 #define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
214 #define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
215 #define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000)
216 #define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000)
217 #define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
218 #define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
219 #define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
220 #define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
227 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
235 #define SECCSR0 0x0028
236 #define SECCSR0_KICK_DECRYPT FIELD32(0x00000001)
237 #define SECCSR0_ONE_SHOT FIELD32(0x00000002)
238 #define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc)
250 #define CSR11_CWMIN FIELD32(0x0000000f)
251 #define CSR11_CWMAX FIELD32(0x000000f0)
252 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
253 #define CSR11_CW_SELECT FIELD32(0x00002000)
254 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
255 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
264 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
265 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
274 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
275 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
289 #define CSR14_TSF_COUNT FIELD32(0x00000001)
290 #define CSR14_TSF_SYNC FIELD32(0x00000006)
291 #define CSR14_TBCN FIELD32(0x00000008)
292 #define CSR14_TCFP FIELD32(0x00000010)
293 #define CSR14_TATIMW FIELD32(0x00000020)
294 #define CSR14_BEACON_GEN FIELD32(0x00000040)
295 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
296 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
305 #define CSR15_CFP FIELD32(0x00000001)
306 #define CSR15_ATIMW FIELD32(0x00000002)
307 #define CSR15_BEACON_SENT FIELD32(0x00000004)
313 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
319 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
327 #define CSR18_SIFS FIELD32(0x000001ff)
328 #define CSR18_PIFS FIELD32(0x001f0000)
336 #define CSR19_DIFS FIELD32(0x0000ffff)
337 #define CSR19_EIFS FIELD32(0xffff0000)
346 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
347 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
348 #define CSR20_AUTOWAKE FIELD32(0x01000000)
356 #define CSR21_RELOAD FIELD32(0x00000001)
357 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
358 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
359 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
360 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
361 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
369 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
370 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
384 #define TXCSR0 0x0060
385 #define TXCSR0_KICK_TX FIELD32(0x00000001)
386 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
387 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
388 #define TXCSR0_ABORT FIELD32(0x00000008)
397 #define TXCSR1 0x0064
398 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
399 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
400 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
401 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
410 #define TXCSR2 0x0068
411 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
412 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
413 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
414 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
419 #define TXCSR3 0x006c
420 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
425 #define TXCSR4 0x0070
426 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
431 #define TXCSR5 0x0074
432 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
437 #define TXCSR6 0x0078
438 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
444 #define TXCSR7 0x007c
445 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
450 #define TXCSR8 0x0098
451 #define TXCSR8_BBP_ID0 FIELD32(0x0000007f)
452 #define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080)
453 #define TXCSR8_BBP_ID1 FIELD32(0x00007f00)
454 #define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000)
455 #define TXCSR8_BBP_ID2 FIELD32(0x007f0000)
456 #define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000)
457 #define TXCSR8_BBP_ID3 FIELD32(0x7f000000)
458 #define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000)
467 #define TXCSR9 0x0094
468 #define TXCSR9_OFDM_RATE FIELD32(0x000000ff)
469 #define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00)
470 #define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000)
471 #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000)
494 #define RXCSR0 0x0080
495 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
496 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
497 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
498 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
499 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
500 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
501 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
502 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
503 #define RXCSR0_PASS_PLCP FIELD32(0x00000100)
504 #define RXCSR0_DROP_MCAST FIELD32(0x00000200)
505 #define RXCSR0_DROP_BCAST FIELD32(0x00000400)
506 #define RXCSR0_ENABLE_QOS FIELD32(0x00000800)
513 #define RXCSR1 0x0084
514 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
515 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
520 #define RXCSR2 0x0088
521 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
528 #define RXCSR3 0x0090
529 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
530 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
531 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
532 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
533 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
534 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
535 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
536 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
543 #define ARCSR1 0x009c
544 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
545 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
546 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
547 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
567 #define PCICSR 0x008c
568 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
569 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
570 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
571 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
572 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
573 #define PCICSR_READ_MULTIPLE FIELD32(0x00000100)
574 #define PCICSR_WRITE_INVALID FIELD32(0x00000200)
581 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
588 #define TIMECSR2 0x00a8
591 #define TIMECSR3 0x00b4
597 #define CNT3_FALSE_CCA FIELD32(0x0000ffff)
614 #define PWRCSR0 0x00c4
619 #define PSCSR0 0x00c8
620 #define PSCSR1 0x00cc
621 #define PSCSR2 0x00d0
622 #define PSCSR3 0x00d4
634 #define PWRCSR1 0x00d8
635 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
636 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
637 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
638 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
639 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
640 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
648 #define TIMECSR 0x00dc
649 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
650 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
651 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
656 #define MACCSR0 0x00e0
668 #define MACCSR1 0x00e4
669 #define MACCSR1_KICK_RX FIELD32(0x00000001)
670 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
671 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
672 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
673 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
674 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
675 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
682 #define RALINKCSR 0x00e8
683 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
684 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00)
685 #define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000)
686 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
687 #define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000)
688 #define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000)
698 #define BCNCSR 0x00ec
699 #define BCNCSR_CHANGE FIELD32(0x00000001)
700 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
701 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
702 #define BCNCSR_MODE FIELD32(0x00006000)
703 #define BCNCSR_PLUS FIELD32(0x00008000)
716 #define BBPCSR 0x00f0
717 #define BBPCSR_VALUE FIELD32(0x000000ff)
718 #define BBPCSR_REGNUM FIELD32(0x00007f00)
719 #define BBPCSR_BUSY FIELD32(0x00008000)
720 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
731 #define RFCSR_VALUE FIELD32(0x00ffffff)
732 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
733 #define RFCSR_IF_SELECT FIELD32(0x20000000)
734 #define RFCSR_PLL_LD FIELD32(0x40000000)
735 #define RFCSR_BUSY FIELD32(0x80000000)
747 #define LEDCSR 0x00f8
748 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
749 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
750 #define LEDCSR_LINK FIELD32(0x00010000)
751 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
752 #define LEDCSR_LINK_POLARITY FIELD32(0x00040000)
753 #define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000)
754 #define LEDCSR_LED_DEFAULT FIELD32(0x00100000)
759 #define SECCSR3 0x00fc
770 #define PRIPTR 0x0108
771 #define ATIMPTR 0x010c
776 #define TXACKCSR0 0x0110
783 #define ACKCNT0 0x0114
784 #define ACKCNT1 0x0118
795 #define GPIOCSR 0x0120
796 #define GPIOCSR_VAL0 FIELD32(0x00000001)
797 #define GPIOCSR_VAL1 FIELD32(0x00000002)
798 #define GPIOCSR_VAL2 FIELD32(0x00000004)
799 #define GPIOCSR_VAL3 FIELD32(0x00000008)
800 #define GPIOCSR_VAL4 FIELD32(0x00000010)
801 #define GPIOCSR_VAL5 FIELD32(0x00000020)
802 #define GPIOCSR_VAL6 FIELD32(0x00000040)
803 #define GPIOCSR_VAL7 FIELD32(0x00000080)
804 #define GPIOCSR_DIR0 FIELD32(0x00000100)
805 #define GPIOCSR_DIR1 FIELD32(0x00000200)
806 #define GPIOCSR_DIR2 FIELD32(0x00000400)
807 #define GPIOCSR_DIR3 FIELD32(0x00000800)
808 #define GPIOCSR_DIR4 FIELD32(0x00001000)
809 #define GPIOCSR_DIR5 FIELD32(0x00002000)
810 #define GPIOCSR_DIR6 FIELD32(0x00004000)
811 #define GPIOCSR_DIR7 FIELD32(0x00008000)
818 #define FIFOCSR0 0x0128
819 #define FIFOCSR1 0x012c
826 #define BCNCSR1 0x0130
827 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
828 #define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000)
834 #define MACCSR2 0x0134
835 #define MACCSR2_DELAY FIELD32(0x000000ff)
840 #define TESTCSR 0x0138
845 #define ARCSR2 0x013c
846 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
847 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
848 #define ARCSR2_LENGTH FIELD32(0xffff0000)
853 #define ARCSR3 0x0140
854 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
855 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
856 #define ARCSR3_LENGTH FIELD32(0xffff0000)
861 #define ARCSR4 0x0144
862 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
863 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
864 #define ARCSR4_LENGTH FIELD32(0xffff0000)
869 #define ARCSR5 0x0148
870 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
871 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
872 #define ARCSR5_LENGTH FIELD32(0xffff0000)
877 #define ARTCSR0 0x014c
878 #define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff)
879 #define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00)
880 #define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000)
881 #define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000)
887 #define ARTCSR1 0x0150
888 #define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff)
889 #define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00)
890 #define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000)
891 #define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000)
896 #define ARTCSR2 0x0154
897 #define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff)
898 #define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00)
899 #define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000)
900 #define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000)
908 #define SECCSR1 0x0158
909 #define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001)
910 #define SECCSR1_ONE_SHOT FIELD32(0x00000002)
911 #define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc)
916 #define BBPCSR1 0x015c
917 #define BBPCSR1_CCK FIELD32(0x00000003)
918 #define BBPCSR1_CCK_FLIP FIELD32(0x00000004)
919 #define BBPCSR1_OFDM FIELD32(0x00030000)
920 #define BBPCSR1_OFDM_FLIP FIELD32(0x00040000)
927 #define DBANDCSR0 0x0160
928 #define DBANDCSR1 0x0164
933 #define BBPPCSR 0x0168
940 #define DBGSEL0 0x016c
941 #define DBGSEL1 0x0170
946 #define BISTCSR 0x0174
953 #define MCAST0 0x0178
954 #define MCAST1 0x017c
967 #define UARTCSR0 0x0180
968 #define UARTCSR1 0x0184
969 #define UARTCSR3 0x0188
970 #define UARTCSR4 0x018c
971 #define UART2CSR0 0x0190
972 #define UART2CSR1 0x0194
973 #define UART2CSR3 0x0198
974 #define UART2CSR4 0x019c
984 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
985 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
990 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
991 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
996 #define BBP_R70_JAPAN_FILTER FIELD8(0x08)
1005 #define RF1_TUNER FIELD32(0x00020000)
1010 #define RF3_TUNER FIELD32(0x00000100)
1011 #define RF3_TXPOWER FIELD32(0x00003e00)
1021 #define EEPROM_MAC_ADDR_0 0x0002
1022 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1023 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1024 #define EEPROM_MAC_ADDR1 0x0003
1025 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1026 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1027 #define EEPROM_MAC_ADDR_2 0x0004
1028 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1029 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1041 #define EEPROM_ANTENNA 0x10
1042 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1043 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1044 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1045 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
1046 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1047 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1048 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1056 #define EEPROM_NIC 0x11
1057 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
1058 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
1059 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
1065 #define EEPROM_GEOGRAPHY 0x12
1066 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
1071 #define EEPROM_BBP_START 0x13
1072 #define EEPROM_BBP_SIZE 16
1073 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1074 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1079 #define EEPROM_TXPOWER_START 0x23
1080 #define EEPROM_TXPOWER_SIZE 7
1081 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
1082 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
1087 #define EEPROM_CALIBRATE_OFFSET 0x3e
1088 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
1093 #define TXD_DESC_SIZE (11 * sizeof(__le32))
1094 #define RXD_DESC_SIZE (11 * sizeof(__le32))
1103 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1104 #define TXD_W0_VALID FIELD32(0x00000002)
1105 #define TXD_W0_RESULT FIELD32(0x0000001c)
1106 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
1107 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
1108 #define TXD_W0_ACK FIELD32(0x00000200)
1109 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
1110 #define TXD_W0_OFDM FIELD32(0x00000800)
1111 #define TXD_W0_CIPHER_OWNER FIELD32(0x00001000)
1112 #define TXD_W0_IFS FIELD32(0x00006000)
1113 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
1114 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1115 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1120 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1125 #define TXD_W2_IV_OFFSET FIELD32(0x0000003f)
1126 #define TXD_W2_AIFS FIELD32(0x000000c0)
1127 #define TXD_W2_CWMIN FIELD32(0x00000f00)
1128 #define TXD_W2_CWMAX FIELD32(0x0000f000)
1133 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
1134 #define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00)
1135 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1136 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1141 #define TXD_W4_IV FIELD32(0xffffffff)
1146 #define TXD_W5_EIV FIELD32(0xffffffff)
1151 #define TXD_W6_KEY FIELD32(0xffffffff)
1152 #define TXD_W7_KEY FIELD32(0xffffffff)
1153 #define TXD_W8_KEY FIELD32(0xffffffff)
1154 #define TXD_W9_KEY FIELD32(0xffffffff)
1159 #define TXD_W10_RTS FIELD32(0x00000001)
1160 #define TXD_W10_TX_RATE FIELD32(0x000000fe)
1169 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1170 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
1171 #define RXD_W0_MULTICAST FIELD32(0x00000004)
1172 #define RXD_W0_BROADCAST FIELD32(0x00000008)
1173 #define RXD_W0_MY_BSS FIELD32(0x00000010)
1174 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
1175 #define RXD_W0_OFDM FIELD32(0x00000040)
1176 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
1177 #define RXD_W0_CIPHER_OWNER FIELD32(0x00000100)
1178 #define RXD_W0_ICV_ERROR FIELD32(0x00000200)
1179 #define RXD_W0_IV_OFFSET FIELD32(0x0000fc00)
1180 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1181 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1186 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1191 #define RXD_W2_SIGNAL FIELD32(0x000000ff)
1192 #define RXD_W2_RSSI FIELD32(0x0000ff00)
1193 #define RXD_W2_TA FIELD32(0xffff0000)
1198 #define RXD_W3_TA FIELD32(0xffffffff)
1203 #define RXD_W4_IV FIELD32(0xffffffff)
1208 #define RXD_W5_EIV FIELD32(0xffffffff)
1213 #define RXD_W6_KEY FIELD32(0xffffffff)
1214 #define RXD_W7_KEY FIELD32(0xffffffff)
1215 #define RXD_W8_KEY FIELD32(0xffffffff)
1216 #define RXD_W9_KEY FIELD32(0xffffffff)
1221 #define RXD_W10_DROP FIELD32(0x00000001)
1227 #define MIN_TXPOWER 0
1228 #define MAX_TXPOWER 31
1229 #define DEFAULT_TXPOWER 24
1231 #define TXPOWER_FROM_DEV(__txpower) \
1232 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1234 #define TXPOWER_TO_DEV(__txpower) \
1235 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)