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rtl8712_syscfg_bitdef.h
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1 /******************************************************************************
2  *
3  * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * Modifications for inclusion into the Linux staging tree are
19  * Copyright(c) 2010 Larry Finger. All rights reserved.
20  *
21  * Contact information:
22  * WLAN FAE <[email protected]>
23  * Larry Finger <[email protected]>
24  *
25  ******************************************************************************/
26 #ifndef __RTL8712_SYSCFG_BITDEF_H__
27 #define __RTL8712_SYSCFG_BITDEF_H__
28 
29 /*SYS_PWR_CTRL*/
30 /*SRCTRL0*/
31 /*SRCTRL1*/
32 /*SYS_CLKR*/
33 
34 /*SYS_IOS_CTRL*/
35 #define iso_LDR2RP_SHT 8 /* EE Loader to Retention Path*/
36 #define iso_LDR2RP BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/
37 
38 /*SYS_CTRL*/
39 #define FEN_DIO_SDIO_SHT 0
40 #define FEN_DIO_SDIO BIT(FEN_DIO_SDIO_SHT)
41 #define FEN_SDIO_SHT 1
42 #define FEN_SDIO BIT(FEN_SDIO_SHT)
43 #define FEN_USBA_SHT 2
44 #define FEN_USBA BIT(FEN_USBA_SHT)
45 #define FEN_UPLL_SHT 3
46 #define FEN_UPLL BIT(FEN_UPLL_SHT)
47 #define FEN_USBD_SHT 4
48 #define FEN_USBD BIT(FEN_USBD_SHT)
49 #define FEN_DIO_PCIE_SHT 5
50 #define FEN_DIO_PCIE BIT(FEN_DIO_PCIE_SHT)
51 #define FEN_PCIEA_SHT 6
52 #define FEN_PCIEA BIT(FEN_PCIEA_SHT)
53 #define FEN_PPLL_SHT 7
54 #define FEN_PPLL BIT(FEN_PPLL_SHT)
55 #define FEN_PCIED_SHT 8
56 #define FEN_PCIED BIT(FEN_PCIED_SHT)
57 #define FEN_CPUEN_SHT 10
58 #define FEN_CPUEN BIT(FEN_CPUEN_SHT)
59 #define FEN_DCORE_SHT 11
60 #define FEN_DCORE BIT(FEN_DCORE_SHT)
61 #define FEN_ELDR_SHT 12
62 #define FEN_ELDR BIT(FEN_ELDR_SHT)
63 #define PWC_DV2LDR_SHT 13
64 #define PWC_DV2LDR BIT(PWC_DV2LDR_SHT) /* Loader Power Enable*/
65 
66 /*=== SYS_CLKR ===*/
67 #define SYS_CLKSEL_SHT 0
68 #define SYS_CLKSEL BIT(SYS_CLKSEL_SHT) /* System Clock 80MHz*/
69 #define PS_CLKSEL_SHT 1
70 #define PS_CLKSEL BIT(PS_CLKSEL_SHT) /*System power save
71  * clock select.*/
72 #define CPU_CLKSEL_SHT 2
73 #define CPU_CLKSEL BIT(CPU_CLKSEL_SHT) /* System Clock select,
74  * 1: AFE source,
75  * 0: System clock(L-Bus)*/
76 #define INT32K_EN_SHT 3
77 #define INT32K_EN BIT(INT32K_EN_SHT)
78 #define MACSLP_SHT 4
79 #define MACSLP BIT(MACSLP_SHT)
80 #define MAC_CLK_EN_SHT 11
81 #define MAC_CLK_EN BIT(MAC_CLK_EN_SHT) /* MAC Clock Enable.*/
82 #define SYS_CLK_EN_SHT 12
83 #define SYS_CLK_EN BIT(SYS_CLK_EN_SHT)
84 #define RING_CLK_EN_SHT 13
85 #define RING_CLK_EN BIT(RING_CLK_EN_SHT)
86 #define SWHW_SEL_SHT 14
87 #define SWHW_SEL BIT(SWHW_SEL_SHT) /* Load done,
88  * control path switch.*/
89 #define FWHW_SEL_SHT 15
90 #define FWHW_SEL BIT(FWHW_SEL_SHT) /* Sleep exit,
91  * control path switch.*/
92 
93 /*9346CR*/
94 #define _VPDIDX_MSK 0xFF00
95 #define _VPDIDX_SHT 8
96 #define _EEM_MSK 0x00C0
97 #define _EEM_SHT 6
98 #define _EEM0 BIT(6)
99 #define _EEM1 BIT(7)
100 #define _EEPROM_EN BIT(5)
101 #define _9356SEL BIT(4)
102 #define _EECS BIT(3)
103 #define _EESK BIT(2)
104 #define _EEDI BIT(1)
105 #define _EEDO BIT(0)
106 
107 /*AFE_MISC*/
108 #define AFE_MISC_USB_MBEN_SHT 7
109 #define AFE_MISC_USB_MBEN BIT(AFE_MISC_USB_MBEN_SHT)
110 #define AFE_MISC_USB_BGEN_SHT 6
111 #define AFE_MISC_USB_BGEN BIT(AFE_MISC_USB_BGEN_SHT)
112 #define AFE_MISC_LD12_VDAJ_SHT 4
113 #define AFE_MISC_LD12_VDAJ_MSK 0X0030
114 #define AFE_MISC_LD12_VDAJ BIT(AFE_MISC_LD12_VDAJ_SHT)
115 #define AFE_MISC_I32_EN_SHT 3
116 #define AFE_MISC_I32_EN BIT(AFE_MISC_I32_EN_SHT)
117 #define AFE_MISC_E32_EN_SHT 2
118 #define AFE_MISC_E32_EN BIT(AFE_MISC_E32_EN_SHT)
119 #define AFE_MISC_MBEN_SHT 1
120 #define AFE_MISC_MBEN BIT(AFE_MISC_MBEN_SHT)/* Enable AFE Macro
121  * Block's Mbias.*/
122 #define AFE_MISC_BGEN_SHT 0
123 #define AFE_MISC_BGEN BIT(AFE_MISC_BGEN_SHT)/* Enable AFE Macro
124  * Block's Bandgap.*/
125 
126 
127 /*--------------------------------------------------------------------------*/
128 /* SPS1_CTRL bits (Offset 0x18-1E, 56bits)*/
129 /*--------------------------------------------------------------------------*/
130 #define SPS1_SWEN BIT(1) /* Enable vsps18 SW Macro Block.*/
131 #define SPS1_LDEN BIT(0) /* Enable VSPS12 LDO Macro block.*/
132 
133 
134 /*----------------------------------------------------------------------------*/
135 /* LDOA15_CTRL bits (Offset 0x20, 8bits)*/
136 /*----------------------------------------------------------------------------*/
137 #define LDA15_EN BIT(0) /* Enable LDOA15 Macro Block*/
138 
139 
140 /*----------------------------------------------------------------------------*/
141 /* 8192S LDOV12D_CTRL bit (Offset 0x21, 8bits)*/
142 /*----------------------------------------------------------------------------*/
143 #define LDV12_EN BIT(0) /* Enable LDOVD12 Macro Block*/
144 #define LDV12_SDBY BIT(1) /* LDOVD12 standby mode*/
145 
146 /*CLK_PS_CTRL*/
147 #define _CLK_GATE_EN BIT(0)
148 
149 
150 /* EFUSE_CTRL*/
151 #define EF_FLAG BIT(31) /* Access Flag, Write:1;
152  * Read:0*/
153 #define EF_PGPD 0x70000000 /* E-fuse Program time*/
154 #define EF_RDT 0x0F000000 /* E-fuse read time: in the
155  * unit of cycle time*/
156 #define EF_PDN_EN BIT(19) /* EFuse Power down enable*/
157 #define ALD_EN BIT(18) /* Autoload Enable*/
158 #define EF_ADDR 0x0003FF00 /* Access Address*/
159 #define EF_DATA 0x000000FF /* Access Data*/
160 
161 /* EFUSE_TEST*/
162 #define LDOE25_EN BIT(31) /* Enable LDOE25 Macro Block*/
163 
164 /* EFUSE_CLK_CTRL*/
165 #define EFUSE_CLK_EN BIT(1) /* E-Fuse Clock Enable*/
166 #define EFUSE_CLK_SEL BIT(0) /* E-Fuse Clock Select,
167  * 0:500K, 1:40M*/
168 
169 #endif /*__RTL8712_SYSCFG_BITDEF_H__*/
170 
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