Macros
#define	iso_LDR2RP_SHT 8 /* EE Loader to Retention Path*/

#define	iso_LDR2RP BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/

#define	FEN_DIO_SDIO_SHT 0

#define	FEN_DIO_SDIO BIT(FEN_DIO_SDIO_SHT)

#define	FEN_SDIO_SHT 1

#define	FEN_SDIO BIT(FEN_SDIO_SHT)

#define	FEN_USBA_SHT 2

#define	FEN_USBA BIT(FEN_USBA_SHT)

#define	FEN_UPLL_SHT 3

#define	FEN_UPLL BIT(FEN_UPLL_SHT)

#define	FEN_USBD_SHT 4

#define	FEN_USBD BIT(FEN_USBD_SHT)

#define	FEN_DIO_PCIE_SHT 5

#define	FEN_DIO_PCIE BIT(FEN_DIO_PCIE_SHT)

#define	FEN_PCIEA_SHT 6

#define	FEN_PCIEA BIT(FEN_PCIEA_SHT)

#define	FEN_PPLL_SHT 7

#define	FEN_PPLL BIT(FEN_PPLL_SHT)

#define	FEN_PCIED_SHT 8

#define	FEN_PCIED BIT(FEN_PCIED_SHT)

#define	FEN_CPUEN_SHT 10

#define	FEN_CPUEN BIT(FEN_CPUEN_SHT)

#define	FEN_DCORE_SHT 11

#define	FEN_DCORE BIT(FEN_DCORE_SHT)

#define	FEN_ELDR_SHT 12

#define	FEN_ELDR BIT(FEN_ELDR_SHT)

#define	PWC_DV2LDR_SHT 13

#define	PWC_DV2LDR BIT(PWC_DV2LDR_SHT) /* Loader Power Enable*/

#define	SYS_CLKSEL_SHT 0

#define	SYS_CLKSEL BIT(SYS_CLKSEL_SHT) /* System Clock 80MHz*/

#define	PS_CLKSEL_SHT 1

#define	PS_CLKSEL

#define	CPU_CLKSEL_SHT 2

#define	CPU_CLKSEL

#define	INT32K_EN_SHT 3

#define	INT32K_EN BIT(INT32K_EN_SHT)

#define	MACSLP_SHT 4

#define	MACSLP BIT(MACSLP_SHT)

#define	MAC_CLK_EN_SHT 11

#define	MAC_CLK_EN BIT(MAC_CLK_EN_SHT) /* MAC Clock Enable.*/

#define	SYS_CLK_EN_SHT 12

#define	SYS_CLK_EN BIT(SYS_CLK_EN_SHT)

#define	RING_CLK_EN_SHT 13

#define	RING_CLK_EN BIT(RING_CLK_EN_SHT)

#define	SWHW_SEL_SHT 14

#define	SWHW_SEL

#define	FWHW_SEL_SHT 15

#define	FWHW_SEL

#define	_VPDIDX_MSK 0xFF00

#define	_VPDIDX_SHT 8

#define	_EEM_MSK 0x00C0

#define	_EEM_SHT 6

#define	_EEM0 BIT(6)

#define	_EEM1 BIT(7)

#define	_EEPROM_EN BIT(5)

#define	_9356SEL BIT(4)

#define	_EECS BIT(3)

#define	_EESK BIT(2)

#define	_EEDI BIT(1)

#define	_EEDO BIT(0)

#define	AFE_MISC_USB_MBEN_SHT 7

#define	AFE_MISC_USB_MBEN BIT(AFE_MISC_USB_MBEN_SHT)

#define	AFE_MISC_USB_BGEN_SHT 6

#define	AFE_MISC_USB_BGEN BIT(AFE_MISC_USB_BGEN_SHT)

#define	AFE_MISC_LD12_VDAJ_SHT 4

#define	AFE_MISC_LD12_VDAJ_MSK 0X0030

#define	AFE_MISC_LD12_VDAJ BIT(AFE_MISC_LD12_VDAJ_SHT)

#define	AFE_MISC_I32_EN_SHT 3

#define	AFE_MISC_I32_EN BIT(AFE_MISC_I32_EN_SHT)

#define	AFE_MISC_E32_EN_SHT 2

#define	AFE_MISC_E32_EN BIT(AFE_MISC_E32_EN_SHT)

#define	AFE_MISC_MBEN_SHT 1

#define	AFE_MISC_MBEN

#define	AFE_MISC_BGEN_SHT 0

#define	AFE_MISC_BGEN

#define	SPS1_SWEN BIT(1) /* Enable vsps18 SW Macro Block.*/

#define	SPS1_LDEN BIT(0) /* Enable VSPS12 LDO Macro block.*/

#define	LDA15_EN BIT(0) /* Enable LDOA15 Macro Block*/

#define	LDV12_EN BIT(0) /* Enable LDOVD12 Macro Block*/

#define	LDV12_SDBY BIT(1) /* LDOVD12 standby mode*/

#define	_CLK_GATE_EN BIT(0)

#define	EF_FLAG

#define	EF_PGPD 0x70000000 /* E-fuse Program time*/

#define	EF_RDT

#define	EF_PDN_EN BIT(19) /* EFuse Power down enable*/

#define	ALD_EN BIT(18) /* Autoload Enable*/

#define	EF_ADDR 0x0003FF00 /* Access Address*/

#define	EF_DATA 0x000000FF /* Access Data*/

#define	LDOE25_EN BIT(31) /* Enable LDOE25 Macro Block*/

#define	EFUSE_CLK_EN BIT(1) /* E-Fuse Clock Enable*/

#define	EFUSE_CLK_SEL

Macro Definition Documentation

#define _9356SEL BIT(4)

Definition at line 96 of file rtl8712_syscfg_bitdef.h.

#define _CLK_GATE_EN BIT(0)

Definition at line 140 of file rtl8712_syscfg_bitdef.h.

#define _EECS BIT(3)

Definition at line 97 of file rtl8712_syscfg_bitdef.h.

#define _EEDI BIT(1)

Definition at line 99 of file rtl8712_syscfg_bitdef.h.

#define _EEDO BIT(0)

Definition at line 100 of file rtl8712_syscfg_bitdef.h.

#define _EEM0 BIT(6)

Definition at line 93 of file rtl8712_syscfg_bitdef.h.

#define _EEM1 BIT(7)

Definition at line 94 of file rtl8712_syscfg_bitdef.h.

#define _EEM_MSK 0x00C0

Definition at line 91 of file rtl8712_syscfg_bitdef.h.

#define _EEM_SHT 6

Definition at line 92 of file rtl8712_syscfg_bitdef.h.

#define _EEPROM_EN BIT(5)

Definition at line 95 of file rtl8712_syscfg_bitdef.h.

#define _EESK BIT(2)

Definition at line 98 of file rtl8712_syscfg_bitdef.h.

#define _VPDIDX_MSK 0xFF00

Definition at line 89 of file rtl8712_syscfg_bitdef.h.

#define _VPDIDX_SHT 8

Definition at line 90 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_BGEN

Value:

BIT(AFE_MISC_BGEN_SHT)/* Enable AFE Macro

* Block's Bandgap.*/

Definition at line 117 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_BGEN_SHT 0

Definition at line 116 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_E32_EN BIT(AFE_MISC_E32_EN_SHT)

Definition at line 113 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_E32_EN_SHT 2

Definition at line 112 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_I32_EN BIT(AFE_MISC_I32_EN_SHT)

Definition at line 111 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_I32_EN_SHT 3

Definition at line 110 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_LD12_VDAJ BIT(AFE_MISC_LD12_VDAJ_SHT)

Definition at line 109 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_LD12_VDAJ_MSK 0X0030

Definition at line 108 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_LD12_VDAJ_SHT 4

Definition at line 107 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_MBEN

Value:

BIT(AFE_MISC_MBEN_SHT)/* Enable AFE Macro

* Block's Mbias.*/

Definition at line 115 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_MBEN_SHT 1

Definition at line 114 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_USB_BGEN BIT(AFE_MISC_USB_BGEN_SHT)

Definition at line 106 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_USB_BGEN_SHT 6

Definition at line 105 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_USB_MBEN BIT(AFE_MISC_USB_MBEN_SHT)

Definition at line 104 of file rtl8712_syscfg_bitdef.h.

#define AFE_MISC_USB_MBEN_SHT 7

Definition at line 103 of file rtl8712_syscfg_bitdef.h.

#define ALD_EN BIT(18) /* Autoload Enable*/

Definition at line 148 of file rtl8712_syscfg_bitdef.h.

#define CPU_CLKSEL

Value:

BIT(CPU_CLKSEL_SHT) /* System Clock select,
                             * 1: AFE source,
                             * 0: System clock(L-Bus)*/

Definition at line 72 of file rtl8712_syscfg_bitdef.h.

#define CPU_CLKSEL_SHT 2

Definition at line 71 of file rtl8712_syscfg_bitdef.h.

#define EF_ADDR 0x0003FF00 /* Access Address*/

Definition at line 149 of file rtl8712_syscfg_bitdef.h.

#define EF_DATA 0x000000FF /* Access Data*/

Definition at line 150 of file rtl8712_syscfg_bitdef.h.

#define EF_FLAG

Value:

BIT(31) /* Access Flag, Write:1;

* Read:0*/

Definition at line 144 of file rtl8712_syscfg_bitdef.h.

#define EF_PDN_EN BIT(19) /* EFuse Power down enable*/

Definition at line 147 of file rtl8712_syscfg_bitdef.h.

#define EF_PGPD 0x70000000 /* E-fuse Program time*/

Definition at line 145 of file rtl8712_syscfg_bitdef.h.

#define EF_RDT

Value:

0x0F000000 /* E-fuse read time: in the

* unit of cycle time*/

Definition at line 146 of file rtl8712_syscfg_bitdef.h.

#define EFUSE_CLK_EN BIT(1) /* E-Fuse Clock Enable*/

Definition at line 156 of file rtl8712_syscfg_bitdef.h.

#define EFUSE_CLK_SEL

Value:

BIT(0) /* E-Fuse Clock Select,

* 0:500K, 1:40M*/

Definition at line 157 of file rtl8712_syscfg_bitdef.h.

#define FEN_CPUEN BIT(FEN_CPUEN_SHT)

Definition at line 58 of file rtl8712_syscfg_bitdef.h.

#define FEN_CPUEN_SHT 10

Definition at line 57 of file rtl8712_syscfg_bitdef.h.

#define FEN_DCORE BIT(FEN_DCORE_SHT)

Definition at line 60 of file rtl8712_syscfg_bitdef.h.

#define FEN_DCORE_SHT 11

Definition at line 59 of file rtl8712_syscfg_bitdef.h.

#define FEN_DIO_PCIE BIT(FEN_DIO_PCIE_SHT)

Definition at line 50 of file rtl8712_syscfg_bitdef.h.

#define FEN_DIO_PCIE_SHT 5

Definition at line 49 of file rtl8712_syscfg_bitdef.h.

#define FEN_DIO_SDIO BIT(FEN_DIO_SDIO_SHT)

Definition at line 40 of file rtl8712_syscfg_bitdef.h.

#define FEN_DIO_SDIO_SHT 0

Definition at line 39 of file rtl8712_syscfg_bitdef.h.

#define FEN_ELDR BIT(FEN_ELDR_SHT)

Definition at line 62 of file rtl8712_syscfg_bitdef.h.

#define FEN_ELDR_SHT 12

Definition at line 61 of file rtl8712_syscfg_bitdef.h.

#define FEN_PCIEA BIT(FEN_PCIEA_SHT)

Definition at line 52 of file rtl8712_syscfg_bitdef.h.

#define FEN_PCIEA_SHT 6

Definition at line 51 of file rtl8712_syscfg_bitdef.h.

#define FEN_PCIED BIT(FEN_PCIED_SHT)

Definition at line 56 of file rtl8712_syscfg_bitdef.h.

#define FEN_PCIED_SHT 8

Definition at line 55 of file rtl8712_syscfg_bitdef.h.

#define FEN_PPLL BIT(FEN_PPLL_SHT)

Definition at line 54 of file rtl8712_syscfg_bitdef.h.

#define FEN_PPLL_SHT 7

Definition at line 53 of file rtl8712_syscfg_bitdef.h.

#define FEN_SDIO BIT(FEN_SDIO_SHT)

Definition at line 42 of file rtl8712_syscfg_bitdef.h.

#define FEN_SDIO_SHT 1

Definition at line 41 of file rtl8712_syscfg_bitdef.h.

#define FEN_UPLL BIT(FEN_UPLL_SHT)

Definition at line 46 of file rtl8712_syscfg_bitdef.h.

#define FEN_UPLL_SHT 3

Definition at line 45 of file rtl8712_syscfg_bitdef.h.

#define FEN_USBA BIT(FEN_USBA_SHT)

Definition at line 44 of file rtl8712_syscfg_bitdef.h.

#define FEN_USBA_SHT 2

Definition at line 43 of file rtl8712_syscfg_bitdef.h.

#define FEN_USBD BIT(FEN_USBD_SHT)

Definition at line 48 of file rtl8712_syscfg_bitdef.h.

#define FEN_USBD_SHT 4

Definition at line 47 of file rtl8712_syscfg_bitdef.h.

#define FWHW_SEL

Value:

BIT(FWHW_SEL_SHT) /* Sleep exit,

* control path switch.*/

Definition at line 86 of file rtl8712_syscfg_bitdef.h.

#define FWHW_SEL_SHT 15

Definition at line 85 of file rtl8712_syscfg_bitdef.h.

#define INT32K_EN BIT(INT32K_EN_SHT)

Definition at line 74 of file rtl8712_syscfg_bitdef.h.

#define INT32K_EN_SHT 3

Definition at line 73 of file rtl8712_syscfg_bitdef.h.

#define iso_LDR2RP BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/

Definition at line 36 of file rtl8712_syscfg_bitdef.h.

#define iso_LDR2RP_SHT 8 /* EE Loader to Retention Path*/

Definition at line 35 of file rtl8712_syscfg_bitdef.h.

#define LDA15_EN BIT(0) /* Enable LDOA15 Macro Block*/

Definition at line 130 of file rtl8712_syscfg_bitdef.h.

#define LDOE25_EN BIT(31) /* Enable LDOE25 Macro Block*/

Definition at line 153 of file rtl8712_syscfg_bitdef.h.

#define LDV12_EN BIT(0) /* Enable LDOVD12 Macro Block*/

Definition at line 136 of file rtl8712_syscfg_bitdef.h.

#define LDV12_SDBY BIT(1) /* LDOVD12 standby mode*/

Definition at line 137 of file rtl8712_syscfg_bitdef.h.

#define MAC_CLK_EN BIT(MAC_CLK_EN_SHT) /* MAC Clock Enable.*/

Definition at line 78 of file rtl8712_syscfg_bitdef.h.

#define MAC_CLK_EN_SHT 11

Definition at line 77 of file rtl8712_syscfg_bitdef.h.

#define MACSLP BIT(MACSLP_SHT)

Definition at line 76 of file rtl8712_syscfg_bitdef.h.

#define MACSLP_SHT 4

Definition at line 75 of file rtl8712_syscfg_bitdef.h.

#define PS_CLKSEL

Value:

BIT(PS_CLKSEL_SHT) /*System power save

* clock select.*/

Definition at line 70 of file rtl8712_syscfg_bitdef.h.

#define PS_CLKSEL_SHT 1

Definition at line 69 of file rtl8712_syscfg_bitdef.h.

#define PWC_DV2LDR BIT(PWC_DV2LDR_SHT) /* Loader Power Enable*/

Definition at line 64 of file rtl8712_syscfg_bitdef.h.

#define PWC_DV2LDR_SHT 13

Definition at line 63 of file rtl8712_syscfg_bitdef.h.

#define RING_CLK_EN BIT(RING_CLK_EN_SHT)

Definition at line 82 of file rtl8712_syscfg_bitdef.h.

#define RING_CLK_EN_SHT 13

Definition at line 81 of file rtl8712_syscfg_bitdef.h.

#define SPS1_LDEN BIT(0) /* Enable VSPS12 LDO Macro block.*/

Definition at line 124 of file rtl8712_syscfg_bitdef.h.

#define SPS1_SWEN BIT(1) /* Enable vsps18 SW Macro Block.*/

Definition at line 123 of file rtl8712_syscfg_bitdef.h.

#define SWHW_SEL

Value:

BIT(SWHW_SEL_SHT) /* Load done,

* control path switch.*/

Definition at line 84 of file rtl8712_syscfg_bitdef.h.

#define SWHW_SEL_SHT 14

Definition at line 83 of file rtl8712_syscfg_bitdef.h.

#define SYS_CLK_EN BIT(SYS_CLK_EN_SHT)

Definition at line 80 of file rtl8712_syscfg_bitdef.h.

#define SYS_CLK_EN_SHT 12

Definition at line 79 of file rtl8712_syscfg_bitdef.h.

#define SYS_CLKSEL BIT(SYS_CLKSEL_SHT) /* System Clock 80MHz*/

Definition at line 68 of file rtl8712_syscfg_bitdef.h.

#define SYS_CLKSEL_SHT 0

Definition at line 67 of file rtl8712_syscfg_bitdef.h.

Macros

Macro Definition Documentation