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rtsx_card.c
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1 /* Driver for Realtek PCI-Express card reader
2  *
3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2, or (at your option) any
8  * later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, see <http://www.gnu.org/licenses/>.
17  *
18  * Author:
19  * wwang ([email protected])
20  * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21  */
22 
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/workqueue.h>
27 #include <linux/kernel.h>
28 
29 #include "rtsx.h"
30 #include "rtsx_transport.h"
31 #include "rtsx_scsi.h"
32 #include "rtsx_card.h"
33 
34 #include "rtsx_sys.h"
35 #include "general.h"
36 
37 #include "sd.h"
38 #include "xd.h"
39 #include "ms.h"
40 
42 {
43  struct sd_info *sd_card = &(chip->sd_card);
44 #ifdef XD_DELAY_WRITE
45  struct xd_info *xd_card = &(chip->xd_card);
46 #endif
47  struct ms_info *ms_card = &(chip->ms_card);
48 
49  if (chip->card_ready & SD_CARD) {
50  if (sd_card->seq_mode) {
52  sd_card->cleanup_counter++;
53  } else {
54  sd_card->cleanup_counter = 0;
55  }
56  }
57 
58 #ifdef XD_DELAY_WRITE
59  if (chip->card_ready & XD_CARD) {
60  if (xd_card->delay_write.delay_write_flag) {
62  xd_card->cleanup_counter++;
63  } else {
64  xd_card->cleanup_counter = 0;
65  }
66  }
67 #endif
68 
69  if (chip->card_ready & MS_CARD) {
70  if (CHK_MSPRO(ms_card)) {
71  if (ms_card->seq_mode) {
73  ms_card->cleanup_counter++;
74  } else {
75  ms_card->cleanup_counter = 0;
76  }
77  } else {
78 #ifdef MS_DELAY_WRITE
79  if (ms_card->delay_write.delay_write_flag) {
81  ms_card->cleanup_counter++;
82  } else {
83  ms_card->cleanup_counter = 0;
84  }
85 #endif
86  }
87  }
88 
89  if (sd_card->cleanup_counter > POLLING_WAIT_CNT)
90  sd_cleanup_work(chip);
91 
92  if (xd_card->cleanup_counter > POLLING_WAIT_CNT)
93  xd_cleanup_work(chip);
94 
95  if (ms_card->cleanup_counter > POLLING_WAIT_CNT)
96  ms_cleanup_work(chip);
97 }
98 
100 {
101  u8 reg1 = 0, reg2 = 0;
102 
103  rtsx_read_register(chip, 0xFF34, &reg1);
104  rtsx_read_register(chip, 0xFF38, &reg2);
105  RTSX_DEBUGP("reg 0xFF34: 0x%x, reg 0xFF38: 0x%x\n", reg1, reg2);
106  if ((reg1 & 0xC0) && (reg2 & 0xC0)) {
107  chip->sd_int = 1;
110  }
111 }
112 
113 #ifdef SUPPORT_SDIO_ASPM
115 {
116  u8 buf[12], reg;
117  int i;
118 
119  for (i = 0; i < 12; i++)
120  rtsx_read_register(chip, 0xFF08 + i, &buf[i]);
121  rtsx_read_register(chip, 0xFF25, &reg);
122  if ((memcmp(buf, chip->sdio_raw_data, 12) != 0) || (reg & 0x03)) {
123  chip->sdio_counter = 0;
124  chip->sdio_idle = 0;
125  } else {
126  if (!chip->sdio_idle) {
127  chip->sdio_counter++;
128  if (chip->sdio_counter >= SDIO_IDLE_COUNT) {
129  chip->sdio_counter = 0;
130  chip->sdio_idle = 1;
131  }
132  }
133  }
134  memcpy(chip->sdio_raw_data, buf, 12);
135 
136  if (chip->sdio_idle) {
137  if (!chip->sdio_aspm) {
138  RTSX_DEBUGP("SDIO enter ASPM!\n");
140  0x30 | (chip->aspm_level[1] << 2));
141  chip->sdio_aspm = 1;
142  }
143  } else {
144  if (chip->sdio_aspm) {
145  RTSX_DEBUGP("SDIO exit ASPM!\n");
146  rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 0x30);
147  chip->sdio_aspm = 0;
148  }
149  }
150 }
151 #endif
152 
154 {
155  int retval;
156 
157  RTSX_DEBUGP("%s: %d, card2lun = 0x%x\n", __func__,
158  chip->sd_reset_counter, chip->card2lun[SD_CARD]);
159 
160  if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT) {
161  clear_bit(SD_NR, &(chip->need_reset));
162  chip->sd_reset_counter = 0;
163  chip->sd_show_cnt = 0;
164  return;
165  }
166 
167  chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
168 
170  rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
171 
172  retval = reset_sd_card(chip);
173  if (chip->need_release & SD_CARD)
174  return;
175  if (retval == STATUS_SUCCESS) {
176  clear_bit(SD_NR, &(chip->need_reset));
177  chip->sd_reset_counter = 0;
178  chip->sd_show_cnt = 0;
179  chip->card_ready |= SD_CARD;
180  chip->card_fail &= ~SD_CARD;
181  chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw;
182  } else {
183  if (chip->sd_io || (chip->sd_reset_counter >= MAX_RESET_CNT)) {
184  clear_bit(SD_NR, &(chip->need_reset));
185  chip->sd_reset_counter = 0;
186  chip->sd_show_cnt = 0;
187  } else {
188  chip->sd_reset_counter++;
189  }
190  chip->card_ready &= ~SD_CARD;
191  chip->card_fail |= SD_CARD;
192  chip->capacity[chip->card2lun[SD_CARD]] = 0;
193  chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
194 
196  if (!chip->ft2_fast_mode)
197  card_power_off(chip, SD_CARD);
198  if (chip->sd_io) {
199  chip->sd_int = 0;
201  } else {
203  }
204  }
205 }
206 
208 {
209  int retval;
210 
211  RTSX_DEBUGP("%s: %d, card2lun = 0x%x\n", __func__,
212  chip->xd_reset_counter, chip->card2lun[XD_CARD]);
213 
214  if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT) {
215  clear_bit(XD_NR, &(chip->need_reset));
216  chip->xd_reset_counter = 0;
217  chip->xd_show_cnt = 0;
218  return;
219  }
220 
221  chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
222 
224  rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
225 
226  retval = reset_xd_card(chip);
227  if (chip->need_release & XD_CARD)
228  return;
229  if (retval == STATUS_SUCCESS) {
230  clear_bit(XD_NR, &(chip->need_reset));
231  chip->xd_reset_counter = 0;
232  chip->card_ready |= XD_CARD;
233  chip->card_fail &= ~XD_CARD;
234  chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw;
235  } else {
236  if (chip->xd_reset_counter >= MAX_RESET_CNT) {
237  clear_bit(XD_NR, &(chip->need_reset));
238  chip->xd_reset_counter = 0;
239  chip->xd_show_cnt = 0;
240  } else {
241  chip->xd_reset_counter++;
242  }
243  chip->card_ready &= ~XD_CARD;
244  chip->card_fail |= XD_CARD;
245  chip->capacity[chip->card2lun[XD_CARD]] = 0;
246  chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
247 
249  if (!chip->ft2_fast_mode)
250  card_power_off(chip, XD_CARD);
252  }
253 }
254 
256 {
257  int retval;
258 
259  RTSX_DEBUGP("%s: %d, card2lun = 0x%x\n", __func__,
260  chip->ms_reset_counter, chip->card2lun[MS_CARD]);
261 
262  if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT) {
263  clear_bit(MS_NR, &(chip->need_reset));
264  chip->ms_reset_counter = 0;
265  chip->ms_show_cnt = 0;
266  return;
267  }
268 
269  chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
270 
272  rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
273 
274  retval = reset_ms_card(chip);
275  if (chip->need_release & MS_CARD)
276  return;
277  if (retval == STATUS_SUCCESS) {
278  clear_bit(MS_NR, &(chip->need_reset));
279  chip->ms_reset_counter = 0;
280  chip->card_ready |= MS_CARD;
281  chip->card_fail &= ~MS_CARD;
282  chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw;
283  } else {
284  if (chip->ms_reset_counter >= MAX_RESET_CNT) {
285  clear_bit(MS_NR, &(chip->need_reset));
286  chip->ms_reset_counter = 0;
287  chip->ms_show_cnt = 0;
288  } else {
289  chip->ms_reset_counter++;
290  }
291  chip->card_ready &= ~MS_CARD;
292  chip->card_fail |= MS_CARD;
293  chip->capacity[chip->card2lun[MS_CARD]] = 0;
294  chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
295 
297  if (!chip->ft2_fast_mode)
298  card_power_off(chip, MS_CARD);
300  }
301 }
302 
303 static void release_sdio(struct rtsx_chip *chip)
304 {
305  if (chip->sd_io) {
307  SD_STOP | SD_CLR_ERR);
308 
309  if (chip->chip_insert_with_sdio) {
310  chip->chip_insert_with_sdio = 0;
311 
312  if (CHECK_PID(chip, 0x5288))
313  rtsx_write_register(chip, 0xFE5A, 0x08, 0x00);
314  else
315  rtsx_write_register(chip, 0xFE70, 0x80, 0x00);
316  }
317 
319  chip->sd_io = 0;
320  }
321 }
322 
323 void rtsx_power_off_card(struct rtsx_chip *chip)
324 {
325  if ((chip->card_ready & SD_CARD) || chip->sd_io) {
326  sd_cleanup_work(chip);
327  sd_power_off_card3v3(chip);
328  }
329 
330  if (chip->card_ready & XD_CARD) {
331  xd_cleanup_work(chip);
332  xd_power_off_card3v3(chip);
333  }
334 
335  if (chip->card_ready & MS_CARD) {
336  ms_cleanup_work(chip);
337  ms_power_off_card3v3(chip);
338  }
339 }
340 
341 void rtsx_release_cards(struct rtsx_chip *chip)
342 {
343  chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
344 
345  if ((chip->card_ready & SD_CARD) || chip->sd_io) {
346  if (chip->int_reg & SD_EXIST)
347  sd_cleanup_work(chip);
348  release_sd_card(chip);
349  }
350 
351  if (chip->card_ready & XD_CARD) {
352  if (chip->int_reg & XD_EXIST)
353  xd_cleanup_work(chip);
354  release_xd_card(chip);
355  }
356 
357  if (chip->card_ready & MS_CARD) {
358  if (chip->int_reg & MS_EXIST)
359  ms_cleanup_work(chip);
360  release_ms_card(chip);
361  }
362 }
363 
364 void rtsx_reset_cards(struct rtsx_chip *chip)
365 {
366  if (!chip->need_reset)
367  return;
368 
370 
372 
373  rtsx_disable_aspm(chip);
374 
375  if ((chip->need_reset & SD_CARD) && chip->chip_insert_with_sdio)
376  clear_bit(SD_NR, &(chip->need_reset));
377 
378  if (chip->need_reset & XD_CARD) {
379  chip->card_exist |= XD_CARD;
380 
381  if (chip->xd_show_cnt >= MAX_SHOW_CNT)
382  do_reset_xd_card(chip);
383  else
384  chip->xd_show_cnt++;
385  }
386  if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
387  if (chip->card_exist & XD_CARD) {
388  clear_bit(SD_NR, &(chip->need_reset));
389  clear_bit(MS_NR, &(chip->need_reset));
390  }
391  }
392  if (chip->need_reset & SD_CARD) {
393  chip->card_exist |= SD_CARD;
394 
395  if (chip->sd_show_cnt >= MAX_SHOW_CNT) {
397  do_reset_sd_card(chip);
398  } else {
399  chip->sd_show_cnt++;
400  }
401  }
402  if (chip->need_reset & MS_CARD) {
403  chip->card_exist |= MS_CARD;
404 
405  if (chip->ms_show_cnt >= MAX_SHOW_CNT)
406  do_reset_ms_card(chip);
407  else
408  chip->ms_show_cnt++;
409  }
410 }
411 
412 void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip)
413 {
415 
417 
418  if (reset_chip)
419  rtsx_reset_chip(chip);
420 
421  chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
422 
423  if ((chip->int_reg & SD_EXIST) && (chip->need_reinit & SD_CARD)) {
424  release_sdio(chip);
425  release_sd_card(chip);
426 
427  wait_timeout(100);
428 
429  chip->card_exist |= SD_CARD;
430  do_reset_sd_card(chip);
431  }
432 
433  if ((chip->int_reg & XD_EXIST) && (chip->need_reinit & XD_CARD)) {
434  release_xd_card(chip);
435 
436  wait_timeout(100);
437 
438  chip->card_exist |= XD_CARD;
439  do_reset_xd_card(chip);
440  }
441 
442  if ((chip->int_reg & MS_EXIST) && (chip->need_reinit & MS_CARD)) {
443  release_ms_card(chip);
444 
445  wait_timeout(100);
446 
447  chip->card_exist |= MS_CARD;
448  do_reset_ms_card(chip);
449  }
450 
451  chip->need_reinit = 0;
452 }
453 
454 #ifdef DISABLE_CARD_INT
455 void card_cd_debounce(struct rtsx_chip *chip, unsigned long *need_reset, unsigned long *need_release)
456 {
457  u8 release_map = 0, reset_map = 0;
458 
459  chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
460 
461  if (chip->card_exist) {
462  if (chip->card_exist & XD_CARD) {
463  if (!(chip->int_reg & XD_EXIST))
464  release_map |= XD_CARD;
465  } else if (chip->card_exist & SD_CARD) {
466  if (!(chip->int_reg & SD_EXIST))
467  release_map |= SD_CARD;
468  } else if (chip->card_exist & MS_CARD) {
469  if (!(chip->int_reg & MS_EXIST))
470  release_map |= MS_CARD;
471  }
472  } else {
473  if (chip->int_reg & XD_EXIST)
474  reset_map |= XD_CARD;
475  else if (chip->int_reg & SD_EXIST)
476  reset_map |= SD_CARD;
477  else if (chip->int_reg & MS_EXIST)
478  reset_map |= MS_CARD;
479  }
480 
481  if (reset_map) {
482  int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
483  int i;
484 
485  for (i = 0; i < (DEBOUNCE_CNT); i++) {
486  chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
487 
488  if (chip->int_reg & XD_EXIST)
489  xd_cnt++;
490  else
491  xd_cnt = 0;
492 
493  if (chip->int_reg & SD_EXIST)
494  sd_cnt++;
495  else
496  sd_cnt = 0;
497 
498  if (chip->int_reg & MS_EXIST)
499  ms_cnt++;
500  else
501  ms_cnt = 0;
502 
503  wait_timeout(30);
504  }
505 
506  reset_map = 0;
507  if (!(chip->card_exist & XD_CARD) && (xd_cnt > (DEBOUNCE_CNT-1)))
508  reset_map |= XD_CARD;
509  if (!(chip->card_exist & SD_CARD) && (sd_cnt > (DEBOUNCE_CNT-1)))
510  reset_map |= SD_CARD;
511  if (!(chip->card_exist & MS_CARD) && (ms_cnt > (DEBOUNCE_CNT-1)))
512  reset_map |= MS_CARD;
513  }
514 
515  if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN))
516  rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0x00);
517 
518  if (need_reset)
519  *need_reset = reset_map;
520  if (need_release)
521  *need_release = release_map;
522 }
523 #endif
524 
525 void rtsx_init_cards(struct rtsx_chip *chip)
526 {
527  if (RTSX_TST_DELINK(chip) && (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
528  RTSX_DEBUGP("Reset chip in polling thread!\n");
529  rtsx_reset_chip(chip);
530  RTSX_CLR_DELINK(chip);
531  }
532 
533 #ifdef DISABLE_CARD_INT
534  card_cd_debounce(chip, &(chip->need_reset), &(chip->need_release));
535 #endif
536 
537  if (chip->need_release) {
538  if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
539  if (chip->int_reg & XD_EXIST) {
540  clear_bit(SD_NR, &(chip->need_release));
541  clear_bit(MS_NR, &(chip->need_release));
542  }
543  }
544 
545  if (!(chip->card_exist & SD_CARD) && !chip->sd_io)
546  clear_bit(SD_NR, &(chip->need_release));
547  if (!(chip->card_exist & XD_CARD))
548  clear_bit(XD_NR, &(chip->need_release));
549  if (!(chip->card_exist & MS_CARD))
550  clear_bit(MS_NR, &(chip->need_release));
551 
552  RTSX_DEBUGP("chip->need_release = 0x%x\n", (unsigned int)(chip->need_release));
553 
554 #ifdef SUPPORT_OCP
555  if (chip->need_release) {
556  if (CHECK_PID(chip, 0x5209)) {
557  u8 mask = 0, val = 0;
558  if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
559  if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
560  mask |= MS_OCP_INT_CLR | MS_OC_CLR;
562  }
563  }
564  if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
565  mask |= SD_OCP_INT_CLR | SD_OC_CLR;
567  }
568  if (mask)
569  rtsx_write_register(chip, OCPCTL, mask, val);
570  } else {
571  if (chip->ocp_stat & (CARD_OC_NOW | CARD_OC_EVER))
575  }
576  chip->ocp_stat = 0;
577  }
578 #endif
579  if (chip->need_release) {
582  }
583 
584  if (chip->need_release & SD_CARD) {
585  clear_bit(SD_NR, &(chip->need_release));
586  chip->card_exist &= ~SD_CARD;
587  chip->card_ejected &= ~SD_CARD;
588  chip->card_fail &= ~SD_CARD;
589  CLR_BIT(chip->lun_mc, chip->card2lun[SD_CARD]);
590  chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
592 
593  release_sdio(chip);
594  release_sd_card(chip);
595  }
596 
597  if (chip->need_release & XD_CARD) {
598  clear_bit(XD_NR, &(chip->need_release));
599  chip->card_exist &= ~XD_CARD;
600  chip->card_ejected &= ~XD_CARD;
601  chip->card_fail &= ~XD_CARD;
602  CLR_BIT(chip->lun_mc, chip->card2lun[XD_CARD]);
603  chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
604 
605  release_xd_card(chip);
606 
607  if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN))
608  rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0xC0);
609  }
610 
611  if (chip->need_release & MS_CARD) {
612  clear_bit(MS_NR, &(chip->need_release));
613  chip->card_exist &= ~MS_CARD;
614  chip->card_ejected &= ~MS_CARD;
615  chip->card_fail &= ~MS_CARD;
616  CLR_BIT(chip->lun_mc, chip->card2lun[MS_CARD]);
617  chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
618 
619  release_ms_card(chip);
620  }
621 
622  RTSX_DEBUGP("chip->card_exist = 0x%x\n", chip->card_exist);
623 
624  if (!chip->card_exist)
625  turn_off_led(chip, LED_GPIO);
626  }
627 
628  if (chip->need_reset) {
629  RTSX_DEBUGP("chip->need_reset = 0x%x\n", (unsigned int)(chip->need_reset));
630 
631  rtsx_reset_cards(chip);
632  }
633 
634  if (chip->need_reinit) {
635  RTSX_DEBUGP("chip->need_reinit = 0x%x\n", (unsigned int)(chip->need_reinit));
636 
637  rtsx_reinit_cards(chip, 0);
638  }
639 }
640 
641 static inline u8 double_depth(u8 depth)
642 {
643  return ((depth > 1) ? (depth - 1) : depth);
644 }
645 
646 int switch_ssc_clock(struct rtsx_chip *chip, int clk)
647 {
648  struct sd_info *sd_card = &(chip->sd_card);
649  struct ms_info *ms_card = &(chip->ms_card);
650  int retval;
651  u8 N = (u8)(clk - 2), min_N, max_N;
652  u8 mcu_cnt, div, max_div, ssc_depth, ssc_depth_mask;
653  int sd_vpclk_phase_reset = 0;
654 
655  if (chip->cur_clk == clk)
656  return STATUS_SUCCESS;
657 
658  if (CHECK_PID(chip, 0x5209)) {
659  min_N = 80;
660  max_N = 208;
661  max_div = CLK_DIV_8;
662  } else {
663  min_N = 60;
664  max_N = 120;
665  max_div = CLK_DIV_4;
666  }
667 
668  if (CHECK_PID(chip, 0x5209) && (chip->cur_card == SD_CARD)) {
669  struct sd_info *sd_card = &(chip->sd_card);
670  if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
671  sd_vpclk_phase_reset = 1;
672  }
673 
674  RTSX_DEBUGP("Switch SSC clock to %dMHz (cur_clk = %d)\n", clk, chip->cur_clk);
675 
676  if ((clk <= 2) || (N > max_N))
677  TRACE_RET(chip, STATUS_FAIL);
678 
679  mcu_cnt = (u8)(125/clk + 3);
680  if (CHECK_PID(chip, 0x5209)) {
681  if (mcu_cnt > 15)
682  mcu_cnt = 15;
683  } else {
684  if (mcu_cnt > 7)
685  mcu_cnt = 7;
686  }
687 
688  div = CLK_DIV_1;
689  while ((N < min_N) && (div < max_div)) {
690  N = (N + 2) * 2 - 2;
691  div++;
692  }
693  RTSX_DEBUGP("N = %d, div = %d\n", N, div);
694 
695  if (chip->ssc_en) {
696  if (CHECK_PID(chip, 0x5209)) {
697  if (chip->cur_card == SD_CARD) {
698  if (CHK_SD_SDR104(sd_card))
699  ssc_depth = chip->ssc_depth_sd_sdr104;
700  else if (CHK_SD_SDR50(sd_card))
701  ssc_depth = chip->ssc_depth_sd_sdr50;
702  else if (CHK_SD_DDR50(sd_card))
703  ssc_depth = double_depth(chip->ssc_depth_sd_ddr50);
704  else if (CHK_SD_HS(sd_card))
705  ssc_depth = double_depth(chip->ssc_depth_sd_hs);
706  else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card))
707  ssc_depth = double_depth(chip->ssc_depth_mmc_52m);
708  else
709  ssc_depth = double_depth(chip->ssc_depth_low_speed);
710  } else if (chip->cur_card == MS_CARD) {
711  if (CHK_MSPRO(ms_card)) {
712  if (CHK_HG8BIT(ms_card))
713  ssc_depth = double_depth(chip->ssc_depth_ms_hg);
714  else
715  ssc_depth = double_depth(chip->ssc_depth_ms_4bit);
716  } else {
717  if (CHK_MS4BIT(ms_card))
718  ssc_depth = double_depth(chip->ssc_depth_ms_4bit);
719  else
720  ssc_depth = double_depth(chip->ssc_depth_low_speed);
721  }
722  } else {
723  ssc_depth = double_depth(chip->ssc_depth_low_speed);
724  }
725 
726  if (ssc_depth) {
727  if (div == CLK_DIV_2) {
728  if (ssc_depth > 1)
729  ssc_depth -= 1;
730  else
731  ssc_depth = SSC_DEPTH_4M;
732 
733  } else if (div == CLK_DIV_4) {
734  if (ssc_depth > 2)
735  ssc_depth -= 2;
736  else
737  ssc_depth = SSC_DEPTH_4M;
738 
739  } else if (div == CLK_DIV_8) {
740  if (ssc_depth > 3)
741  ssc_depth -= 3;
742  else
743  ssc_depth = SSC_DEPTH_4M;
744 
745  }
746  }
747  } else {
748  ssc_depth = 0x01;
749  N -= 2;
750  }
751  } else {
752  ssc_depth = 0;
753  }
754 
755  if (CHECK_PID(chip, 0x5209))
756  ssc_depth_mask = SSC_DEPTH_MASK;
757  else
758  ssc_depth_mask = 0x03;
759 
760  RTSX_DEBUGP("ssc_depth = %d\n", ssc_depth);
761 
762  rtsx_init_cmd(chip);
764  rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);
766  rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth);
767  rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
769  if (sd_vpclk_phase_reset) {
772  }
773 
774  retval = rtsx_send_cmd(chip, 0, WAIT_TIME);
775  if (retval < 0)
776  TRACE_RET(chip, STATUS_ERROR);
777 
778  udelay(10);
780 
781  chip->cur_clk = clk;
782 
783  return STATUS_SUCCESS;
784 }
785 
786 int switch_normal_clock(struct rtsx_chip *chip, int clk)
787 {
788  u8 sel, div, mcu_cnt;
789  int sd_vpclk_phase_reset = 0;
790 
791  if (chip->cur_clk == clk)
792  return STATUS_SUCCESS;
793 
794  if (CHECK_PID(chip, 0x5209) && (chip->cur_card == SD_CARD)) {
795  struct sd_info *sd_card = &(chip->sd_card);
796  if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
797  sd_vpclk_phase_reset = 1;
798  }
799 
800  switch (clk) {
801  case CLK_20:
802  RTSX_DEBUGP("Switch clock to 20MHz\n");
803  sel = SSC_80;
804  div = CLK_DIV_4;
805  mcu_cnt = 7;
806  break;
807 
808  case CLK_30:
809  RTSX_DEBUGP("Switch clock to 30MHz\n");
810  sel = SSC_120;
811  div = CLK_DIV_4;
812  mcu_cnt = 7;
813  break;
814 
815  case CLK_40:
816  RTSX_DEBUGP("Switch clock to 40MHz\n");
817  sel = SSC_80;
818  div = CLK_DIV_2;
819  mcu_cnt = 7;
820  break;
821 
822  case CLK_50:
823  RTSX_DEBUGP("Switch clock to 50MHz\n");
824  sel = SSC_100;
825  div = CLK_DIV_2;
826  mcu_cnt = 6;
827  break;
828 
829  case CLK_60:
830  RTSX_DEBUGP("Switch clock to 60MHz\n");
831  sel = SSC_120;
832  div = CLK_DIV_2;
833  mcu_cnt = 6;
834  break;
835 
836  case CLK_80:
837  RTSX_DEBUGP("Switch clock to 80MHz\n");
838  sel = SSC_80;
839  div = CLK_DIV_1;
840  mcu_cnt = 5;
841  break;
842 
843  case CLK_100:
844  RTSX_DEBUGP("Switch clock to 100MHz\n");
845  sel = SSC_100;
846  div = CLK_DIV_1;
847  mcu_cnt = 5;
848  break;
849 
850  case CLK_120:
851  RTSX_DEBUGP("Switch clock to 120MHz\n");
852  sel = SSC_120;
853  div = CLK_DIV_1;
854  mcu_cnt = 5;
855  break;
856 
857  case CLK_150:
858  RTSX_DEBUGP("Switch clock to 150MHz\n");
859  sel = SSC_150;
860  div = CLK_DIV_1;
861  mcu_cnt = 4;
862  break;
863 
864  case CLK_200:
865  RTSX_DEBUGP("Switch clock to 200MHz\n");
866  sel = SSC_200;
867  div = CLK_DIV_1;
868  mcu_cnt = 4;
869  break;
870 
871  default:
872  RTSX_DEBUGP("Try to switch to an illegal clock (%d)\n", clk);
873  TRACE_RET(chip, STATUS_FAIL);
874  }
875 
876  RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ);
877  if (sd_vpclk_phase_reset) {
880  }
881  RTSX_WRITE_REG(chip, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);
882  RTSX_WRITE_REG(chip, CLK_SEL, 0xFF, sel);
883 
884  if (sd_vpclk_phase_reset) {
885  udelay(200);
888  udelay(200);
889  }
890  RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, 0);
891 
892  chip->cur_clk = clk;
893 
894  return STATUS_SUCCESS;
895 }
896 
897 void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip, u32 byte_cnt, u8 pack_size)
898 {
899  if (pack_size > DMA_1024)
900  pack_size = DMA_512;
901 
903 
904  rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24));
905  rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(byte_cnt >> 16));
906  rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(byte_cnt >> 8));
907  rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC0, 0xFF, (u8)byte_cnt);
908 
909  if (dir == DMA_FROM_DEVICE) {
911  DMA_DIR_FROM_CARD | DMA_EN | pack_size);
912  } else {
914  DMA_DIR_TO_CARD | DMA_EN | pack_size);
915  }
916 
918 }
919 
920 int enable_card_clock(struct rtsx_chip *chip, u8 card)
921 {
922  u8 clk_en = 0;
923 
924  if (card & XD_CARD)
925  clk_en |= XD_CLK_EN;
926  if (card & SD_CARD)
927  clk_en |= SD_CLK_EN;
928  if (card & MS_CARD)
929  clk_en |= MS_CLK_EN;
930 
931  RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);
932 
933  return STATUS_SUCCESS;
934 }
935 
937 {
938  u8 clk_en = 0;
939 
940  if (card & XD_CARD)
941  clk_en |= XD_CLK_EN;
942  if (card & SD_CARD)
943  clk_en |= SD_CLK_EN;
944  if (card & MS_CARD)
945  clk_en |= MS_CLK_EN;
946 
947  RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, 0);
948 
949  return STATUS_SUCCESS;
950 }
951 
952 int card_power_on(struct rtsx_chip *chip, u8 card)
953 {
954  int retval;
955  u8 mask, val1, val2;
956 
957  if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
958  mask = MS_POWER_MASK;
959  val1 = MS_PARTIAL_POWER_ON;
960  val2 = MS_POWER_ON;
961  } else {
962  mask = SD_POWER_MASK;
963  val1 = SD_PARTIAL_POWER_ON;
964  val2 = SD_POWER_ON;
965  }
966 
967  rtsx_init_cmd(chip);
968  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val1);
969  if (CHECK_PID(chip, 0x5209) && (card == SD_CARD))
971 
972  retval = rtsx_send_cmd(chip, 0, 100);
973  if (retval != STATUS_SUCCESS)
974  TRACE_RET(chip, STATUS_FAIL);
975 
977 
978  rtsx_init_cmd(chip);
979  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val2);
980  if (CHECK_PID(chip, 0x5209) && (card == SD_CARD))
982 
983  retval = rtsx_send_cmd(chip, 0, 100);
984  if (retval != STATUS_SUCCESS)
985  TRACE_RET(chip, STATUS_FAIL);
986 
987  return STATUS_SUCCESS;
988 }
989 
990 int card_power_off(struct rtsx_chip *chip, u8 card)
991 {
992  u8 mask, val;
993 
994  if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
995  mask = MS_POWER_MASK;
996  val = MS_POWER_OFF;
997  } else {
998  mask = SD_POWER_MASK;
999  val = SD_POWER_OFF;
1000  }
1001  if (CHECK_PID(chip, 0x5209)) {
1002  mask |= PMOS_STRG_MASK;
1003  val |= PMOS_STRG_400mA;
1004  }
1005 
1006  RTSX_WRITE_REG(chip, CARD_PWR_CTL, mask, val);
1007  if (CHECK_PID(chip, 0x5209) && (card == SD_CARD))
1009 
1010  return STATUS_SUCCESS;
1011 }
1012 
1013 int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 sec_addr, u16 sec_cnt)
1014 {
1015  int retval;
1016  unsigned int lun = SCSI_LUN(srb);
1017  int i;
1018 
1019  if (chip->rw_card[lun] == NULL)
1020  TRACE_RET(chip, STATUS_FAIL);
1021 
1022  for (i = 0; i < 3; i++) {
1023  chip->rw_need_retry = 0;
1024 
1025  retval = chip->rw_card[lun](srb, chip, sec_addr, sec_cnt);
1026  if (retval != STATUS_SUCCESS) {
1027  if (rtsx_check_chip_exist(chip) != STATUS_SUCCESS) {
1028  rtsx_release_chip(chip);
1029  TRACE_RET(chip, STATUS_FAIL);
1030  }
1031  if (detect_card_cd(chip, chip->cur_card) != STATUS_SUCCESS)
1032  TRACE_RET(chip, STATUS_FAIL);
1033 
1034  if (!chip->rw_need_retry) {
1035  RTSX_DEBUGP("RW fail, but no need to retry\n");
1036  break;
1037  }
1038  } else {
1039  chip->rw_need_retry = 0;
1040  break;
1041  }
1042 
1043  RTSX_DEBUGP("Retry RW, (i = %d)\n", i);
1044  }
1045 
1046  return retval;
1047 }
1048 
1049 int card_share_mode(struct rtsx_chip *chip, int card)
1050 {
1051  u8 mask, value;
1052 
1053  if (CHECK_PID(chip, 0x5209) || CHECK_PID(chip, 0x5208)) {
1054  mask = CARD_SHARE_MASK;
1055  if (card == SD_CARD)
1056  value = CARD_SHARE_48_SD;
1057  else if (card == MS_CARD)
1058  value = CARD_SHARE_48_MS;
1059  else if (card == XD_CARD)
1060  value = CARD_SHARE_48_XD;
1061  else
1062  TRACE_RET(chip, STATUS_FAIL);
1063 
1064  } else if (CHECK_PID(chip, 0x5288)) {
1065  mask = 0x03;
1066  if (card == SD_CARD)
1067  value = CARD_SHARE_BAROSSA_SD;
1068  else if (card == MS_CARD)
1069  value = CARD_SHARE_BAROSSA_MS;
1070  else if (card == XD_CARD)
1071  value = CARD_SHARE_BAROSSA_XD;
1072  else
1073  TRACE_RET(chip, STATUS_FAIL);
1074 
1075  } else {
1076  TRACE_RET(chip, STATUS_FAIL);
1077  }
1078 
1079  RTSX_WRITE_REG(chip, CARD_SHARE_MODE, mask, value);
1080 
1081  return STATUS_SUCCESS;
1082 }
1083 
1084 
1085 int select_card(struct rtsx_chip *chip, int card)
1086 {
1087  int retval;
1088 
1089  if (chip->cur_card != card) {
1090  u8 mod;
1091 
1092  if (card == SD_CARD)
1093  mod = SD_MOD_SEL;
1094  else if (card == MS_CARD)
1095  mod = MS_MOD_SEL;
1096  else if (card == XD_CARD)
1097  mod = XD_MOD_SEL;
1098  else if (card == SPI_CARD)
1099  mod = SPI_MOD_SEL;
1100  else
1101  TRACE_RET(chip, STATUS_FAIL);
1102 
1103  RTSX_WRITE_REG(chip, CARD_SELECT, 0x07, mod);
1104  chip->cur_card = card;
1105 
1106  retval = card_share_mode(chip, card);
1107  if (retval != STATUS_SUCCESS)
1108  TRACE_RET(chip, STATUS_FAIL);
1109  }
1110 
1111  return STATUS_SUCCESS;
1112 }
1113 
1114 void toggle_gpio(struct rtsx_chip *chip, u8 gpio)
1115 {
1116  u8 temp_reg;
1117 
1118  rtsx_read_register(chip, CARD_GPIO, &temp_reg);
1119  temp_reg ^= (0x01 << gpio);
1120  rtsx_write_register(chip, CARD_GPIO, 0xFF, temp_reg);
1121 }
1122 
1123 void turn_on_led(struct rtsx_chip *chip, u8 gpio)
1124 {
1125  if (CHECK_PID(chip, 0x5288))
1126  rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), (u8)(1 << gpio));
1127  else
1128  rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1129 }
1130 
1131 void turn_off_led(struct rtsx_chip *chip, u8 gpio)
1132 {
1133  if (CHECK_PID(chip, 0x5288))
1134  rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1135  else
1136  rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), (u8)(1 << gpio));
1137 }
1138 
1139 int detect_card_cd(struct rtsx_chip *chip, int card)
1140 {
1141  u32 card_cd, status;
1142 
1143  if (card == SD_CARD) {
1144  card_cd = SD_EXIST;
1145  } else if (card == MS_CARD) {
1146  card_cd = MS_EXIST;
1147  } else if (card == XD_CARD) {
1148  card_cd = XD_EXIST;
1149  } else {
1150  RTSX_DEBUGP("Wrong card type: 0x%x\n", card);
1151  TRACE_RET(chip, STATUS_FAIL);
1152  }
1153 
1154  status = rtsx_readl(chip, RTSX_BIPR);
1155  if (!(status & card_cd))
1156  TRACE_RET(chip, STATUS_FAIL);
1157 
1158  return STATUS_SUCCESS;
1159 }
1160 
1161 int check_card_exist(struct rtsx_chip *chip, unsigned int lun)
1162 {
1163  if (chip->card_exist & chip->lun2card[lun])
1164  return 1;
1165 
1166  return 0;
1167 }
1168 
1169 int check_card_ready(struct rtsx_chip *chip, unsigned int lun)
1170 {
1171  if (chip->card_ready & chip->lun2card[lun])
1172  return 1;
1173 
1174  return 0;
1175 }
1176 
1177 int check_card_wp(struct rtsx_chip *chip, unsigned int lun)
1178 {
1179  if (chip->card_wp & chip->lun2card[lun])
1180  return 1;
1181 
1182  return 0;
1183 }
1184 
1185 int check_card_fail(struct rtsx_chip *chip, unsigned int lun)
1186 {
1187  if (chip->card_fail & chip->lun2card[lun])
1188  return 1;
1189 
1190  return 0;
1191 }
1192 
1193 int check_card_ejected(struct rtsx_chip *chip, unsigned int lun)
1194 {
1195  if (chip->card_ejected & chip->lun2card[lun])
1196  return 1;
1197 
1198  return 0;
1199 }
1200 
1201 u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun)
1202 {
1203  if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
1204  return (u8)XD_CARD;
1205  else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
1206  return (u8)SD_CARD;
1207  else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
1208  return (u8)MS_CARD;
1209 
1210  return 0;
1211 }
1212 
1213 void eject_card(struct rtsx_chip *chip, unsigned int lun)
1214 {
1215  do_remaining_work(chip);
1216 
1217  if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
1218  release_sd_card(chip);
1219  chip->card_ejected |= SD_CARD;
1220  chip->card_ready &= ~SD_CARD;
1221  chip->capacity[lun] = 0;
1222  } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
1223  release_xd_card(chip);
1224  chip->card_ejected |= XD_CARD;
1225  chip->card_ready &= ~XD_CARD;
1226  chip->capacity[lun] = 0;
1227  } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
1228  release_ms_card(chip);
1229  chip->card_ejected |= MS_CARD;
1230  chip->card_ready &= ~MS_CARD;
1231  chip->capacity[lun] = 0;
1232  }
1233 }