14 #include <linux/kernel.h>
19 #include <linux/slab.h>
27 #define GPIO_BASE(chip) ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
29 #define CON_OFFSET 0x700
30 #define MASK_OFFSET 0x900
31 #define PEND_OFFSET 0xA00
32 #define REG_OFFSET(x) ((x) << 2)
45 static int s5p_gpioint_set_type(
struct irq_data *
d,
unsigned int type)
47 struct irq_chip_generic *
gc = irq_data_get_irq_chip_data(d);
48 struct irq_chip_type *
ct = gc->chip_types;
49 unsigned int shift = (d->
irq - gc->irq_base) << 2;
73 gc->type_cache &= ~(0x7 << shift);
74 gc->type_cache |= type << shift;
75 writel(gc->type_cache, gc->reg_base + ct->regs.type);
79 static void s5p_gpioint_handler(
unsigned int irq,
struct irq_desc *
desc)
82 int group, pend_offset, mask_offset;
86 chained_irq_enter(chip, desc);
88 for (group = 0; group < bank->
nr_groups; group++) {
103 int offset = fls(pend) - 1;
106 pend &= ~
BIT(offset);
109 chained_irq_exit(chip, desc);
114 static int used_gpioint_groups = 0;
115 int group = chip->
group;
117 struct irq_chip_generic *gc;
118 struct irq_chip_type *
ct;
138 irq_set_chained_handler(bank->
irq, s5p_gpioint_handler);
140 bank->
handler = s5p_gpioint_handler;
141 printk(
KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
151 used_gpioint_groups++;
164 ct->chip.irq_set_type = s5p_gpioint_set_type,
169 IRQ_GC_INIT_MASK_CACHE,
183 offset = pin - my_chip->
chip.base;
184 group = my_chip->
group;
191 ret = s5p_gpioint_add(my_chip);
211 bank->
irq = chain_irq;