Macros
#define	XCHAL_CP_NUM 2 /* number of coprocessors */

#define	XCHAL_CP_MAX 7 /* max CP ID + 1 (0 if none) */

#define	XCHAL_CP_MASK 0x41 /* bitmask of all CPs by ID */

#define	XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */

#define	XCHAL_CP0_NAME "FPU"

#define	XCHAL_CP0_IDENT FPU

#define	XCHAL_CP0_SA_SIZE 72 /* size of state save area */

#define	XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */

#define	XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */

#define	XCHAL_CP6_NAME "XAD"

#define	XCHAL_CP6_IDENT XAD

#define	XCHAL_CP6_SA_SIZE 576 /* size of state save area */

#define	XCHAL_CP6_SA_ALIGN 16 /* min alignment of save area */

#define	XCHAL_CP_ID_XAD 6 /* coprocessor ID (0..7) */

#define	XCHAL_CP1_SA_SIZE 0

#define	XCHAL_CP1_SA_ALIGN 1

#define	XCHAL_CP2_SA_SIZE 0

#define	XCHAL_CP2_SA_ALIGN 1

#define	XCHAL_CP3_SA_SIZE 0

#define	XCHAL_CP3_SA_ALIGN 1

#define	XCHAL_CP4_SA_SIZE 0

#define	XCHAL_CP4_SA_ALIGN 1

#define	XCHAL_CP5_SA_SIZE 0

#define	XCHAL_CP5_SA_ALIGN 1

#define	XCHAL_CP7_SA_SIZE 0

#define	XCHAL_CP7_SA_ALIGN 1

#define	XCHAL_NCP_SA_SIZE 4

#define	XCHAL_NCP_SA_ALIGN 4

#define	XCHAL_TOTAL_SA_SIZE 672 /* with 16-byte align padding */

#define	XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */

#define	XCHAL_NCP_SA_NUM 1

#define	XCHAL_NCP_SA_LIST(s) XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0)

#define	XCHAL_CP0_SA_NUM 18

#define	XCHAL_CP0_SA_LIST(s)

#define	XCHAL_CP1_SA_NUM 0

#define	XCHAL_CP1_SA_LIST(s) /* empty */

#define	XCHAL_CP2_SA_NUM 0

#define	XCHAL_CP2_SA_LIST(s) /* empty */

#define	XCHAL_CP3_SA_NUM 0

#define	XCHAL_CP3_SA_LIST(s) /* empty */

#define	XCHAL_CP4_SA_NUM 0

#define	XCHAL_CP4_SA_LIST(s) /* empty */

#define	XCHAL_CP5_SA_NUM 0

#define	XCHAL_CP5_SA_LIST(s) /* empty */

#define	XCHAL_CP6_SA_NUM 46

#define	XCHAL_CP6_SA_LIST(s)

#define	XCHAL_CP7_SA_NUM 0

#define	XCHAL_CP7_SA_LIST(s) /* empty */

#define	XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8

Macro Definition Documentation

#define XCHAL_CP0_IDENT FPU

Definition at line 23 of file tie.h.

#define XCHAL_CP0_NAME "FPU"

Definition at line 22 of file tie.h.

#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */

Definition at line 25 of file tie.h.

#define XCHAL_CP0_SA_LIST ( s )

Value:

XCHAL_SA_REG(s,0,0,1,0,            fcr, 4, 4, 4,0x03E8,  ur,232, 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,1,0,            fsr, 4, 4, 4,0x03E9,  ur,233, 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f0, 4, 4, 4,0x0030,   f,0  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f1, 4, 4, 4,0x0031,   f,1  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f2, 4, 4, 4,0x0032,   f,2  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f3, 4, 4, 4,0x0033,   f,3  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f4, 4, 4, 4,0x0034,   f,4  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f5, 4, 4, 4,0x0035,   f,5  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f6, 4, 4, 4,0x0036,   f,6  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f7, 4, 4, 4,0x0037,   f,7  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f8, 4, 4, 4,0x0038,   f,8  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,             f9, 4, 4, 4,0x0039,   f,9  , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,            f10, 4, 4, 4,0x003A,   f,10 , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,            f11, 4, 4, 4,0x003B,   f,11 , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,            f12, 4, 4, 4,0x003C,   f,12 , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,            f13, 4, 4, 4,0x003D,   f,13 , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,            f14, 4, 4, 4,0x003E,   f,14 , 32,0,0,0) \
 XCHAL_SA_REG(s,0,0,2,0,            f15, 4, 4, 4,0x003F,   f,15 , 32,0,0,0)

Definition at line 100 of file tie.h.

#define XCHAL_CP0_SA_NUM 18

Definition at line 99 of file tie.h.

#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */

Definition at line 24 of file tie.h.

#define XCHAL_CP1_SA_ALIGN 1

Definition at line 35 of file tie.h.

#define XCHAL_CP1_SA_LIST ( s ) /* empty */

Definition at line 121 of file tie.h.

#define XCHAL_CP1_SA_NUM 0

Definition at line 120 of file tie.h.

#define XCHAL_CP1_SA_SIZE 0

Definition at line 34 of file tie.h.

#define XCHAL_CP2_SA_ALIGN 1

Definition at line 37 of file tie.h.

#define XCHAL_CP2_SA_LIST ( s ) /* empty */

Definition at line 124 of file tie.h.

#define XCHAL_CP2_SA_NUM 0

Definition at line 123 of file tie.h.

#define XCHAL_CP2_SA_SIZE 0

Definition at line 36 of file tie.h.

#define XCHAL_CP3_SA_ALIGN 1

Definition at line 39 of file tie.h.

#define XCHAL_CP3_SA_LIST ( s ) /* empty */

Definition at line 127 of file tie.h.

#define XCHAL_CP3_SA_NUM 0

Definition at line 126 of file tie.h.

#define XCHAL_CP3_SA_SIZE 0

Definition at line 38 of file tie.h.

#define XCHAL_CP4_SA_ALIGN 1

Definition at line 41 of file tie.h.

#define XCHAL_CP4_SA_LIST ( s ) /* empty */

Definition at line 130 of file tie.h.

#define XCHAL_CP4_SA_NUM 0

Definition at line 129 of file tie.h.

#define XCHAL_CP4_SA_SIZE 0

Definition at line 40 of file tie.h.

#define XCHAL_CP5_SA_ALIGN 1

Definition at line 43 of file tie.h.

#define XCHAL_CP5_SA_LIST ( s ) /* empty */

Definition at line 133 of file tie.h.

#define XCHAL_CP5_SA_NUM 0

Definition at line 132 of file tie.h.

#define XCHAL_CP5_SA_SIZE 0

Definition at line 42 of file tie.h.

#define XCHAL_CP6_IDENT XAD

Definition at line 28 of file tie.h.

#define XCHAL_CP6_NAME "XAD"

Definition at line 27 of file tie.h.

#define XCHAL_CP6_SA_ALIGN 16 /* min alignment of save area */

Definition at line 30 of file tie.h.

#define XCHAL_CP6_SA_LIST ( s )

Definition at line 136 of file tie.h.

#define XCHAL_CP6_SA_NUM 46

Definition at line 135 of file tie.h.

#define XCHAL_CP6_SA_SIZE 576 /* size of state save area */

Definition at line 29 of file tie.h.

#define XCHAL_CP7_SA_ALIGN 1

Definition at line 45 of file tie.h.

#define XCHAL_CP7_SA_LIST ( s ) /* empty */

Definition at line 185 of file tie.h.

#define XCHAL_CP7_SA_NUM 0

Definition at line 184 of file tie.h.

#define XCHAL_CP7_SA_SIZE 0

Definition at line 44 of file tie.h.

#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */

Definition at line 26 of file tie.h.

#define XCHAL_CP_ID_XAD 6 /* coprocessor ID (0..7) */

Definition at line 31 of file tie.h.

#define XCHAL_CP_MASK 0x41 /* bitmask of all CPs by ID */

Definition at line 18 of file tie.h.

#define XCHAL_CP_MAX 7 /* max CP ID + 1 (0 if none) */

Definition at line 17 of file tie.h.

#define XCHAL_CP_NUM 2 /* number of coprocessors */

Definition at line 16 of file tie.h.

#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */

Definition at line 19 of file tie.h.

#define XCHAL_NCP_SA_ALIGN 4

Definition at line 49 of file tie.h.

#define XCHAL_NCP_SA_LIST ( s ) XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0)

Definition at line 96 of file tie.h.

#define XCHAL_NCP_SA_NUM 1

Definition at line 95 of file tie.h.

#define XCHAL_NCP_SA_SIZE 4

Definition at line 48 of file tie.h.

#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8

Definition at line 188 of file tie.h.

#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */

Definition at line 53 of file tie.h.

#define XCHAL_TOTAL_SA_SIZE 672 /* with 16-byte align padding */

Definition at line 52 of file tie.h.

Macros

Macro Definition Documentation