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savage_drv.h
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1 /* savage_drv.h -- Private header for the savage driver */
2 /*
3  * Copyright 2004 Felix Kuehling
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sub license,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial portions
15  * of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20  * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  */
25 
26 #ifndef __SAVAGE_DRV_H__
27 #define __SAVAGE_DRV_H__
28 
29 #define DRIVER_AUTHOR "Felix Kuehling"
30 
31 #define DRIVER_NAME "savage"
32 #define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]"
33 #define DRIVER_DATE "20050313"
34 
35 #define DRIVER_MAJOR 2
36 #define DRIVER_MINOR 4
37 #define DRIVER_PATCHLEVEL 1
38 /* Interface history:
39  *
40  * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy
41  * 2.0 The first real DRM
42  * 2.1 Scissors registers managed by the DRM, 3D operations clipped by
43  * cliprects of the cmdbuf ioctl
44  * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX
45  * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits
46  * wide and thus very long lived (unlikely to ever wrap). The size
47  * in the struct was 32 bits before, but only 16 bits were used
48  * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is
49  * actually used
50  */
51 
52 typedef struct drm_savage_age {
54  unsigned int wrap;
56 
57 typedef struct drm_savage_buf_priv {
61  struct drm_buf *buf;
63 
64 typedef struct drm_savage_dma_page {
66  unsigned int used, flushed;
68 #define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */
69 /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command
70  * size of 16kbytes or 4k entries. Minimum requirement would be
71  * 10kbytes for 255 40-byte vertices in one drawing command. */
72 #define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4)
73 
74 /* interesting bits of hardware state that are saved in dev_priv */
75 typedef union {
78  } common;
79  struct {
80  unsigned char pad[sizeof(struct drm_savage_common_state)];
81  uint32_t texctrl, texaddr;
82  uint32_t scstart, new_scstart;
83  uint32_t scend, new_scend;
84  } s3d;
85  struct {
86  unsigned char pad[sizeof(struct drm_savage_common_state)];
87  uint32_t texdescr, texaddr0, texaddr1;
88  uint32_t drawctrl0, new_drawctrl0;
89  uint32_t drawctrl1, new_drawctrl1;
90  } s4;
92 
93 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */
105 };
106 
107 extern struct drm_ioctl_desc savage_ioctls[];
108 extern int savage_max_ioctl;
109 
110 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
111 
112 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \
113  || (chip==S3_PROSAVAGE) \
114  || (chip==S3_TWISTER) \
115  || (chip==S3_PROSAVAGEDDR))
116 
117 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
118 
119 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
120 
121 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \
122  ||(chip==S3_PROSAVAGEDDR))
123 
124 /* flags */
125 #define SAVAGE_IS_AGP 1
126 
127 typedef struct drm_savage_private {
129 
131 
132  /* who am I? */
134 
135  unsigned int cob_size;
137  unsigned int dma_type;
138 
139  /* frame buffer layout */
140  unsigned int fb_bpp;
141  unsigned int front_offset, front_pitch;
142  unsigned int back_offset, back_pitch;
143  unsigned int depth_bpp;
144  unsigned int depth_offset, depth_pitch;
145 
146  /* bitmap descriptors for swap and clear */
147  unsigned int front_bd, back_bd, depth_bd;
148 
149  /* local textures */
150  unsigned int texture_offset;
151  unsigned int texture_size;
152 
153  /* memory regions in physical memory */
154  drm_local_map_t *sarea;
155  drm_local_map_t *mmio;
156  drm_local_map_t *fb;
157  drm_local_map_t *aperture;
158  drm_local_map_t *status;
159  drm_local_map_t *agp_textures;
160  drm_local_map_t *cmd_dma;
161  drm_local_map_t fake_dma;
162 
163  struct {
164  int handle;
165  unsigned long base, size;
166  } mtrr[3];
167 
168  /* BCI and status-related stuff */
172  unsigned int event_wrap;
173 
174  /* Savage4 command DMA */
178 
179  /* saved hw state for global/local check on S3D */
181  /* and for scissors (global, so don't emit if not changed) */
183 
185 
186  /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */
187  unsigned int waiting;
188 
189  /* config/hardware-dependent function pointers */
190  int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n);
192  /* Err, there is a macro wait_event in include/linux/wait.h.
193  * Avoid unwanted macro expansion. */
195  const struct drm_clip_rect * pbox);
198 
199 /* ioctls */
200 extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv);
201 extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
202 
203 /* BCI functions */
205  unsigned int flags);
206 extern void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf);
208 extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page);
210  unsigned int n);
211 extern int savage_driver_load(struct drm_device *dev, unsigned long chipset);
212 extern int savage_driver_firstopen(struct drm_device *dev);
213 extern void savage_driver_lastclose(struct drm_device *dev);
214 extern int savage_driver_unload(struct drm_device *dev);
215 extern void savage_reclaim_buffers(struct drm_device *dev,
216  struct drm_file *file_priv);
217 
218 /* state functions */
220  const struct drm_clip_rect * pbox);
222  const struct drm_clip_rect * pbox);
223 
224 #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */
225 #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */
226 #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */
227 #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */
228 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */
229 
230 #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region
231  * inside the MMIO region */
232 #define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip
233  * BCI FIFO */
234 
235 /*
236  * MMIO registers
237  */
238 #define SAVAGE_STATUS_WORD0 0x48C00
239 #define SAVAGE_STATUS_WORD1 0x48C04
240 #define SAVAGE_ALT_STATUS_WORD0 0x48C60
242 #define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff
243 #define SAVAGE_FIFO_USED_MASK_S4 0x001fffff
244 
245 /* Copied from savage_bci.h in the 2D driver with some renaming. */
247 /* Bitmap descriptors */
248 #define SAVAGE_BD_STRIDE_SHIFT 0
249 #define SAVAGE_BD_BPP_SHIFT 16
250 #define SAVAGE_BD_TILE_SHIFT 24
251 #define SAVAGE_BD_BW_DISABLE (1<<28)
252 /* common: */
253 #define SAVAGE_BD_TILE_LINEAR 0
254 /* savage4, MX, IX, 3D */
255 #define SAVAGE_BD_TILE_16BPP 2
256 #define SAVAGE_BD_TILE_32BPP 3
257 /* twister, prosavage, DDR, supersavage, 2000 */
258 #define SAVAGE_BD_TILE_DEST 1
259 #define SAVAGE_BD_TILE_TEXTURE 2
260 /* GBD - BCI enable */
261 /* savage4, MX, IX, 3D */
262 #define SAVAGE_GBD_BCI_ENABLE 8
263 /* twister, prosavage, DDR, supersavage, 2000 */
264 #define SAVAGE_GBD_BCI_ENABLE_TWISTER 0
266 #define SAVAGE_GBD_BIG_ENDIAN 4
267 #define SAVAGE_GBD_LITTLE_ENDIAN 0
268 #define SAVAGE_GBD_64 1
270 /* Global Bitmap Descriptor */
271 #define SAVAGE_BCI_GLB_BD_LOW 0x8168
272 #define SAVAGE_BCI_GLB_BD_HIGH 0x816C
273 
274 /*
275  * BCI registers
276  */
277 /* Savage4/Twister/ProSavage 3D registers */
278 #define SAVAGE_DRAWLOCALCTRL_S4 0x1e
279 #define SAVAGE_TEXPALADDR_S4 0x1f
280 #define SAVAGE_TEXCTRL0_S4 0x20
281 #define SAVAGE_TEXCTRL1_S4 0x21
282 #define SAVAGE_TEXADDR0_S4 0x22
283 #define SAVAGE_TEXADDR1_S4 0x23
284 #define SAVAGE_TEXBLEND0_S4 0x24
285 #define SAVAGE_TEXBLEND1_S4 0x25
286 #define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */
287 #define SAVAGE_TEXDESCR_S4 0x27
288 #define SAVAGE_FOGTABLE_S4 0x28
289 #define SAVAGE_FOGCTRL_S4 0x30
290 #define SAVAGE_STENCILCTRL_S4 0x31
291 #define SAVAGE_ZBUFCTRL_S4 0x32
292 #define SAVAGE_ZBUFOFF_S4 0x33
293 #define SAVAGE_DESTCTRL_S4 0x34
294 #define SAVAGE_DRAWCTRL0_S4 0x35
295 #define SAVAGE_DRAWCTRL1_S4 0x36
296 #define SAVAGE_ZWATERMARK_S4 0x37
297 #define SAVAGE_DESTTEXRWWATERMARK_S4 0x38
298 #define SAVAGE_TEXBLENDCOLOR_S4 0x39
299 /* Savage3D/MX/IX 3D registers */
300 #define SAVAGE_TEXPALADDR_S3D 0x18
301 #define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */
302 #define SAVAGE_TEXADDR_S3D 0x1A
303 #define SAVAGE_TEXDESCR_S3D 0x1B
304 #define SAVAGE_TEXCTRL_S3D 0x1C
305 #define SAVAGE_FOGTABLE_S3D 0x20
306 #define SAVAGE_FOGCTRL_S3D 0x30
307 #define SAVAGE_DRAWCTRL_S3D 0x31
308 #define SAVAGE_ZBUFCTRL_S3D 0x32
309 #define SAVAGE_ZBUFOFF_S3D 0x33
310 #define SAVAGE_DESTCTRL_S3D 0x34
311 #define SAVAGE_SCSTART_S3D 0x35
312 #define SAVAGE_SCEND_S3D 0x36
313 #define SAVAGE_ZWATERMARK_S3D 0x37
314 #define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38
315 /* common stuff */
316 #define SAVAGE_VERTBUFADDR 0x3e
317 #define SAVAGE_BITPLANEWTMASK 0xd7
318 #define SAVAGE_DMABUFADDR 0x51
320 /* texture enable bits (needed for tex addr checking) */
321 #define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */
322 #define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */
323 #define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */
324 
325 /* Global fields in Savage4/Twister/ProSavage 3D registers:
326  *
327  * All texture registers and DrawLocalCtrl are local. All other
328  * registers are global. */
329 
330 /* Global fields in Savage3D/MX/IX 3D registers:
331  *
332  * All texture registers are local. DrawCtrl and ZBufCtrl are
333  * partially local. All other registers are global.
334  *
335  * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal
336  * ZBufCtrl global fields: zCmpFunc, zBufEn
337  */
338 #define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c
339 #define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027
340 
341 /* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d)
342  */
343 #define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff
344 #define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff
345 
346 /*
347  * BCI commands
348  */
349 #define BCI_CMD_NOP 0x40000000
350 #define BCI_CMD_RECT 0x48000000
351 #define BCI_CMD_RECT_XP 0x01000000
352 #define BCI_CMD_RECT_YP 0x02000000
353 #define BCI_CMD_SCANLINE 0x50000000
354 #define BCI_CMD_LINE 0x5C000000
355 #define BCI_CMD_LINE_LAST_PIXEL 0x58000000
356 #define BCI_CMD_BYTE_TEXT 0x63000000
357 #define BCI_CMD_NT_BYTE_TEXT 0x67000000
358 #define BCI_CMD_BIT_TEXT 0x6C000000
359 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
360 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
361 #define BCI_CMD_SEND_COLOR 0x00008000
363 #define BCI_CMD_CLIP_NONE 0x00000000
364 #define BCI_CMD_CLIP_CURRENT 0x00002000
365 #define BCI_CMD_CLIP_LR 0x00004000
366 #define BCI_CMD_CLIP_NEW 0x00006000
368 #define BCI_CMD_DEST_GBD 0x00000000
369 #define BCI_CMD_DEST_PBD 0x00000800
370 #define BCI_CMD_DEST_PBD_NEW 0x00000C00
371 #define BCI_CMD_DEST_SBD 0x00001000
372 #define BCI_CMD_DEST_SBD_NEW 0x00001400
374 #define BCI_CMD_SRC_TRANSPARENT 0x00000200
375 #define BCI_CMD_SRC_SOLID 0x00000000
376 #define BCI_CMD_SRC_GBD 0x00000020
377 #define BCI_CMD_SRC_COLOR 0x00000040
378 #define BCI_CMD_SRC_MONO 0x00000060
379 #define BCI_CMD_SRC_PBD_COLOR 0x00000080
380 #define BCI_CMD_SRC_PBD_MONO 0x000000A0
381 #define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0
382 #define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0
383 #define BCI_CMD_SRC_SBD_COLOR 0x00000100
384 #define BCI_CMD_SRC_SBD_MONO 0x00000120
385 #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140
386 #define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160
388 #define BCI_CMD_PAT_TRANSPARENT 0x00000010
389 #define BCI_CMD_PAT_NONE 0x00000000
390 #define BCI_CMD_PAT_COLOR 0x00000002
391 #define BCI_CMD_PAT_MONO 0x00000003
392 #define BCI_CMD_PAT_PBD_COLOR 0x00000004
393 #define BCI_CMD_PAT_PBD_MONO 0x00000005
394 #define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006
395 #define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007
396 #define BCI_CMD_PAT_SBD_COLOR 0x00000008
397 #define BCI_CMD_PAT_SBD_MONO 0x00000009
398 #define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A
399 #define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B
401 #define BCI_BD_BW_DISABLE 0x10000000
402 #define BCI_BD_TILE_MASK 0x03000000
403 #define BCI_BD_TILE_NONE 0x00000000
404 #define BCI_BD_TILE_16 0x02000000
405 #define BCI_BD_TILE_32 0x03000000
406 #define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF)
407 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
408 #define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF)
409 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
410 
411 #define BCI_CMD_SET_REGISTER 0x96000000
413 #define BCI_CMD_WAIT 0xC0000000
414 #define BCI_CMD_WAIT_3D 0x00010000
415 #define BCI_CMD_WAIT_2D 0x00020000
416 
417 #define BCI_CMD_UPDATE_EVENT_TAG 0x98000000
419 #define BCI_CMD_DRAW_PRIM 0x80000000
420 #define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000
421 #define BCI_CMD_DRAW_CONT 0x01000000
422 #define BCI_CMD_DRAW_TRILIST 0x00000000
423 #define BCI_CMD_DRAW_TRISTRIP 0x02000000
424 #define BCI_CMD_DRAW_TRIFAN 0x04000000
425 #define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff
426 #define BCI_CMD_DRAW_NO_Z 0x00000001
427 #define BCI_CMD_DRAW_NO_W 0x00000002
428 #define BCI_CMD_DRAW_NO_CD 0x00000004
429 #define BCI_CMD_DRAW_NO_CS 0x00000008
430 #define BCI_CMD_DRAW_NO_U0 0x00000010
431 #define BCI_CMD_DRAW_NO_V0 0x00000020
432 #define BCI_CMD_DRAW_NO_UV0 0x00000030
433 #define BCI_CMD_DRAW_NO_U1 0x00000040
434 #define BCI_CMD_DRAW_NO_V1 0x00000080
435 #define BCI_CMD_DRAW_NO_UV1 0x000000c0
436 
437 #define BCI_CMD_DMA 0xa8000000
439 #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF)
440 #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF)
441 #define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF)
442 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
443 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
444 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
446 #define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF))
447 #define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF))
448 #define BCI_LINE_MISC(maj, ym, xp, yp, err) \
449  (((maj) & 0x1FFF) | \
450  ((ym) ? 1<<13 : 0) | \
451  ((xp) ? 1<<14 : 0) | \
452  ((yp) ? 1<<15 : 0) | \
453  ((err) << 16))
454 
455 /*
456  * common commands
457  */
458 #define BCI_SET_REGISTERS( first, n ) \
459  BCI_WRITE(BCI_CMD_SET_REGISTER | \
460  ((uint32_t)(n) & 0xff) << 16 | \
461  ((uint32_t)(first) & 0xffff))
462 #define DMA_SET_REGISTERS( first, n ) \
463  DMA_WRITE(BCI_CMD_SET_REGISTER | \
464  ((uint32_t)(n) & 0xff) << 16 | \
465  ((uint32_t)(first) & 0xffff))
466 
467 #define BCI_DRAW_PRIMITIVE(n, type, skip) \
468  BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
469  ((n) << 16))
470 #define DMA_DRAW_PRIMITIVE(n, type, skip) \
471  DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
472  ((n) << 16))
473 
474 #define BCI_DRAW_INDICES_S3D(n, type, i0) \
475  BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
476  ((n) << 16) | (i0))
477 
478 #define BCI_DRAW_INDICES_S4(n, type, skip) \
479  BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
480  (skip) | ((n) << 16))
481 
482 #define BCI_DMA(n) \
483  BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1))
484 
485 /*
486  * access to MMIO
487  */
488 #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
489 #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) )
490 
491 /*
492  * access to the burst command interface (BCI)
493  */
494 #define SAVAGE_BCI_DEBUG 1
495 
496 #define BCI_LOCALS volatile uint32_t *bci_ptr;
497 
498 #define BEGIN_BCI( n ) do { \
499  dev_priv->wait_fifo(dev_priv, (n)); \
500  bci_ptr = dev_priv->bci_ptr; \
501 } while(0)
502 
503 #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val)
504 
505 /*
506  * command DMA support
507  */
508 #define SAVAGE_DMA_DEBUG 1
509 
510 #define DMA_LOCALS uint32_t *dma_ptr;
511 
512 #define BEGIN_DMA( n ) do { \
513  unsigned int cur = dev_priv->current_dma_page; \
514  unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \
515  dev_priv->dma_pages[cur].used; \
516  if ((n) > rest) { \
517  dma_ptr = savage_dma_alloc(dev_priv, (n)); \
518  } else { /* fast path for small allocations */ \
519  dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \
520  cur * SAVAGE_DMA_PAGE_SIZE + \
521  dev_priv->dma_pages[cur].used; \
522  if (dev_priv->dma_pages[cur].used == 0) \
523  savage_dma_wait(dev_priv, cur); \
524  dev_priv->dma_pages[cur].used += (n); \
525  } \
526 } while(0)
527 
528 #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val)
529 
530 #define DMA_COPY(src, n) do { \
531  memcpy(dma_ptr, (src), (n)*4); \
532  dma_ptr += n; \
533 } while(0)
535 #if SAVAGE_DMA_DEBUG
536 #define DMA_COMMIT() do { \
537  unsigned int cur = dev_priv->current_dma_page; \
538  uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \
539  cur * SAVAGE_DMA_PAGE_SIZE + \
540  dev_priv->dma_pages[cur].used; \
541  if (dma_ptr != expected) { \
542  DRM_ERROR("DMA allocation and use don't match: " \
543  "%p != %p\n", expected, dma_ptr); \
544  savage_dma_reset(dev_priv); \
545  } \
546 } while(0)
547 #else
548 #define DMA_COMMIT() do {/* nothing */} while(0)
549 #endif
550 
551 #define DMA_FLUSH() dev_priv->dma_flush(dev_priv)
552 
553 /* Buffer aging via event tag
554  */
555 
556 #define UPDATE_EVENT_COUNTER( ) do { \
557  if (dev_priv->status_ptr) { \
558  uint16_t count; \
559  /* coordinate with Xserver */ \
560  count = dev_priv->status_ptr[1023]; \
561  if (count < dev_priv->event_counter) \
562  dev_priv->event_wrap++; \
563  dev_priv->event_counter = count; \
564  } \
565 } while(0)
566 
567 #define SET_AGE( age, e, w ) do { \
568  (age)->event = e; \
569  (age)->wrap = w; \
570 } while(0)
571 
572 #define TEST_AGE( age, e, w ) \
573  ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) )
574 
575 #endif /* __SAVAGE_DRV_H__ */