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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include <asm/sibyte/sb1250_defs.h>Go to the source code of this file.
Macros | |
| #define | A_MAC_BASE_0 0x0010064000 |
| #define | A_MAC_BASE_1 0x0010065000 |
| #define | MAC_SPACING 0x1000 |
| #define | MAC_DMA_TXRX_SPACING 0x0400 |
| #define | MAC_DMA_CHANNEL_SPACING 0x0100 |
| #define | DMA_RX 0 |
| #define | DMA_TX 1 |
| #define | MAC_NUM_DMACHAN 2 /* channels per direction */ |
| #define | MAC_NUM_PORTS 3 |
| #define | A_MAC_CHANNEL_BASE(macnum) |
| #define | A_MAC_REGISTER(macnum, reg) |
| #define | R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ |
| #define | A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) |
| #define | R_MAC_DMA_CHANNEL_BASE(txrx, chan) |
| #define | A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) |
| #define | R_MAC_DMA_REGISTER(txrx, chan, reg) |
| #define | R_MAC_DMA_CONFIG0 0x00000000 |
| #define | R_MAC_DMA_CONFIG1 0x00000008 |
| #define | R_MAC_DMA_DSCR_BASE 0x00000010 |
| #define | R_MAC_DMA_DSCR_CNT 0x00000018 |
| #define | R_MAC_DMA_CUR_DSCRA 0x00000020 |
| #define | R_MAC_DMA_CUR_DSCRB 0x00000028 |
| #define | R_MAC_DMA_CUR_DSCRADDR 0x00000030 |
| #define | R_MAC_RMON_TX_BYTES 0x00000000 |
| #define | R_MAC_RMON_COLLISIONS 0x00000008 |
| #define | R_MAC_RMON_LATE_COL 0x00000010 |
| #define | R_MAC_RMON_EX_COL 0x00000018 |
| #define | R_MAC_RMON_FCS_ERROR 0x00000020 |
| #define | R_MAC_RMON_TX_ABORT 0x00000028 |
| #define | R_MAC_RMON_TX_BAD 0x00000038 |
| #define | R_MAC_RMON_TX_GOOD 0x00000040 |
| #define | R_MAC_RMON_TX_RUNT 0x00000048 |
| #define | R_MAC_RMON_TX_OVERSIZE 0x00000050 |
| #define | R_MAC_RMON_RX_BYTES 0x00000080 |
| #define | R_MAC_RMON_RX_MCAST 0x00000088 |
| #define | R_MAC_RMON_RX_BCAST 0x00000090 |
| #define | R_MAC_RMON_RX_BAD 0x00000098 |
| #define | R_MAC_RMON_RX_GOOD 0x000000A0 |
| #define | R_MAC_RMON_RX_RUNT 0x000000A8 |
| #define | R_MAC_RMON_RX_OVERSIZE 0x000000B0 |
| #define | R_MAC_RMON_RX_FCS_ERROR 0x000000B8 |
| #define | R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 |
| #define | R_MAC_RMON_RX_CODE_ERROR 0x000000C8 |
| #define | R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 |
| #define | R_MAC_CFG 0x00000100 |
| #define | R_MAC_THRSH_CFG 0x00000108 |
| #define | R_MAC_VLANTAG 0x00000110 |
| #define | R_MAC_FRAMECFG 0x00000118 |
| #define | R_MAC_EOPCNT 0x00000120 |
| #define | R_MAC_FIFO_PTRS 0x00000128 |
| #define | R_MAC_ADFILTER_CFG 0x00000200 |
| #define | R_MAC_ETHERNET_ADDR 0x00000208 |
| #define | R_MAC_PKT_TYPE 0x00000210 |
| #define | R_MAC_HASH_BASE 0x00000240 |
| #define | R_MAC_ADDR_BASE 0x00000280 |
| #define | R_MAC_CHLO0_BASE 0x00000300 |
| #define | R_MAC_CHUP0_BASE 0x00000320 |
| #define | R_MAC_ENABLE 0x00000400 |
| #define | R_MAC_STATUS 0x00000408 |
| #define | R_MAC_INT_MASK 0x00000410 |
| #define | R_MAC_TXD_CTL 0x00000420 |
| #define | R_MAC_MDIO 0x00000428 |
| #define | R_MAC_DEBUG_STATUS 0x00000448 |
| #define | MAC_HASH_COUNT 8 |
| #define | MAC_ADDR_COUNT 8 |
| #define | MAC_CHMAP_COUNT 4 |
| #define | R_DUART_MODE_REG_1 0x000 |
| #define | R_DUART_MODE_REG_2 0x010 |
| #define | R_DUART_STATUS 0x020 |
| #define | R_DUART_CLK_SEL 0x030 |
| #define | R_DUART_CMD 0x050 |
| #define | R_DUART_RX_HOLD 0x060 |
| #define | R_DUART_TX_HOLD 0x070 |
| #define | R_DUART_AUX_CTRL 0x010 |
| #define | R_DUART_ISR_A 0x020 |
| #define | R_DUART_IMR_A 0x030 |
| #define | R_DUART_ISR_B 0x040 |
| #define | R_DUART_IMR_B 0x050 |
| #define | R_DUART_OUT_PORT 0x060 |
| #define | R_DUART_OPCR 0x070 |
| #define | R_DUART_IN_PORT 0x080 |
| #define | R_DUART_SET_OPR 0x0B0 |
| #define | R_DUART_CLEAR_OPR 0x0C0 |
| #define | R_DUART_IN_CHNG_A 0x0D0 |
| #define | R_DUART_IN_CHNG_B 0x0E0 |
| #define | A_DUART_MODE_REG_1_A 0x0010060100 |
| #define | A_DUART_MODE_REG_2_A 0x0010060110 |
| #define | A_DUART_STATUS_A 0x0010060120 |
| #define | A_DUART_CLK_SEL_A 0x0010060130 |
| #define | A_DUART_CMD_A 0x0010060150 |
| #define | A_DUART_RX_HOLD_A 0x0010060160 |
| #define | A_DUART_TX_HOLD_A 0x0010060170 |
| #define | A_DUART_MODE_REG_1_B 0x0010060200 |
| #define | A_DUART_MODE_REG_2_B 0x0010060210 |
| #define | A_DUART_STATUS_B 0x0010060220 |
| #define | A_DUART_CLK_SEL_B 0x0010060230 |
| #define | A_DUART_CMD_B 0x0010060250 |
| #define | A_DUART_RX_HOLD_B 0x0010060260 |
| #define | A_DUART_TX_HOLD_B 0x0010060270 |
| #define | A_DUART_INPORT_CHNG 0x0010060300 |
| #define | A_DUART_AUX_CTRL 0x0010060310 |
| #define | A_DUART_ISR_A 0x0010060320 |
| #define | A_DUART_IMR_A 0x0010060330 |
| #define | A_DUART_ISR_B 0x0010060340 |
| #define | A_DUART_IMR_B 0x0010060350 |
| #define | A_DUART_OUT_PORT 0x0010060360 |
| #define | A_DUART_OPCR 0x0010060370 |
| #define | A_DUART_IN_PORT 0x0010060380 |
| #define | A_DUART_ISR 0x0010060390 |
| #define | A_DUART_IMR 0x00100603A0 |
| #define | A_DUART_SET_OPR 0x00100603B0 |
| #define | A_DUART_CLEAR_OPR 0x00100603C0 |
| #define | A_DUART_INPORT_CHNG_A 0x00100603D0 |
| #define | A_DUART_INPORT_CHNG_B 0x00100603E0 |
| #define | IO_EXT_CFG_COUNT 8 |
| #define | A_IO_EXT_BASE 0x0010061000 |
| #define | A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) |
| #define | A_IO_EXT_CFG_BASE 0x0010061000 |
| #define | A_IO_EXT_MULT_SIZE_BASE 0x0010061100 |
| #define | A_IO_EXT_START_ADDR_BASE 0x0010061200 |
| #define | A_IO_EXT_TIME_CFG0_BASE 0x0010061600 |
| #define | A_IO_EXT_TIME_CFG1_BASE 0x0010061700 |
| #define | IO_EXT_REGISTER_SPACING 8 |
| #define | A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) |
| #define | R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) |
| #define | R_IO_EXT_CFG 0x0000 |
| #define | R_IO_EXT_MULT_SIZE 0x0100 |
| #define | R_IO_EXT_START_ADDR 0x0200 |
| #define | R_IO_EXT_TIME_CFG0 0x0600 |
| #define | R_IO_EXT_TIME_CFG1 0x0700 |
| #define | A_IO_INTERRUPT_STATUS 0x0010061A00 |
| #define | A_IO_INTERRUPT_DATA0 0x0010061A10 |
| #define | A_IO_INTERRUPT_DATA1 0x0010061A18 |
| #define | A_IO_INTERRUPT_DATA2 0x0010061A20 |
| #define | A_IO_INTERRUPT_DATA3 0x0010061A28 |
| #define | A_IO_INTERRUPT_ADDR0 0x0010061A30 |
| #define | A_IO_INTERRUPT_ADDR1 0x0010061A40 |
| #define | A_IO_INTERRUPT_PARITY 0x0010061A50 |
| #define | A_IO_PCMCIA_CFG 0x0010061A60 |
| #define | A_IO_PCMCIA_STATUS 0x0010061A70 |
| #define | A_IO_DRIVE_0 0x0010061300 |
| #define | A_IO_DRIVE_1 0x0010061308 |
| #define | A_IO_DRIVE_2 0x0010061310 |
| #define | A_IO_DRIVE_3 0x0010061318 |
| #define | A_IO_DRIVE_BASE A_IO_DRIVE_0 |
| #define | IO_DRIVE_REGISTER_SPACING 8 |
| #define | R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) |
| #define | A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) |
| #define | R_IO_INTERRUPT_STATUS 0x0A00 |
| #define | R_IO_INTERRUPT_DATA0 0x0A10 |
| #define | R_IO_INTERRUPT_DATA1 0x0A18 |
| #define | R_IO_INTERRUPT_DATA2 0x0A20 |
| #define | R_IO_INTERRUPT_DATA3 0x0A28 |
| #define | R_IO_INTERRUPT_ADDR0 0x0A30 |
| #define | R_IO_INTERRUPT_ADDR1 0x0A40 |
| #define | R_IO_INTERRUPT_PARITY 0x0A50 |
| #define | R_IO_PCMCIA_CFG 0x0A60 |
| #define | R_IO_PCMCIA_STATUS 0x0A70 |
| #define | A_GPIO_CLR_EDGE 0x0010061A80 |
| #define | A_GPIO_INT_TYPE 0x0010061A88 |
| #define | A_GPIO_INPUT_INVERT 0x0010061A90 |
| #define | A_GPIO_GLITCH 0x0010061A98 |
| #define | A_GPIO_READ 0x0010061AA0 |
| #define | A_GPIO_DIRECTION 0x0010061AA8 |
| #define | A_GPIO_PIN_CLR 0x0010061AB0 |
| #define | A_GPIO_PIN_SET 0x0010061AB8 |
| #define | A_GPIO_BASE 0x0010061A80 |
| #define | R_GPIO_CLR_EDGE 0x00 |
| #define | R_GPIO_INT_TYPE 0x08 |
| #define | R_GPIO_INPUT_INVERT 0x10 |
| #define | R_GPIO_GLITCH 0x18 |
| #define | R_GPIO_READ 0x20 |
| #define | R_GPIO_DIRECTION 0x28 |
| #define | R_GPIO_PIN_CLR 0x30 |
| #define | R_GPIO_PIN_SET 0x38 |
| #define | A_SMB_XTRA_0 0x0010060000 |
| #define | A_SMB_XTRA_1 0x0010060008 |
| #define | A_SMB_FREQ_0 0x0010060010 |
| #define | A_SMB_FREQ_1 0x0010060018 |
| #define | A_SMB_STATUS_0 0x0010060020 |
| #define | A_SMB_STATUS_1 0x0010060028 |
| #define | A_SMB_CMD_0 0x0010060030 |
| #define | A_SMB_CMD_1 0x0010060038 |
| #define | A_SMB_START_0 0x0010060040 |
| #define | A_SMB_START_1 0x0010060048 |
| #define | A_SMB_DATA_0 0x0010060050 |
| #define | A_SMB_DATA_1 0x0010060058 |
| #define | A_SMB_CONTROL_0 0x0010060060 |
| #define | A_SMB_CONTROL_1 0x0010060068 |
| #define | A_SMB_PEC_0 0x0010060070 |
| #define | A_SMB_PEC_1 0x0010060078 |
| #define | A_SMB_0 0x0010060000 |
| #define | A_SMB_1 0x0010060008 |
| #define | SMB_REGISTER_SPACING 0x8 |
| #define | A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) |
| #define | A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) |
| #define | R_SMB_XTRA 0x0000000000 |
| #define | R_SMB_FREQ 0x0000000010 |
| #define | R_SMB_STATUS 0x0000000020 |
| #define | R_SMB_CMD 0x0000000030 |
| #define | R_SMB_START 0x0000000040 |
| #define | R_SMB_DATA 0x0000000050 |
| #define | R_SMB_CONTROL 0x0000000060 |
| #define | R_SMB_PEC 0x0000000070 |
| #define | A_SCD_WDOG_0 0x0010020050 |
| #define | A_SCD_WDOG_1 0x0010020150 |
| #define | SCD_WDOG_SPACING 0x100 |
| #define | SCD_NUM_WDOGS 2 |
| #define | A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) |
| #define | A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r)) |
| #define | R_SCD_WDOG_INIT 0x0000000000 |
| #define | R_SCD_WDOG_CNT 0x0000000008 |
| #define | R_SCD_WDOG_CFG 0x0000000010 |
| #define | A_SCD_WDOG_INIT_0 0x0010020050 |
| #define | A_SCD_WDOG_CNT_0 0x0010020058 |
| #define | A_SCD_WDOG_CFG_0 0x0010020060 |
| #define | A_SCD_WDOG_INIT_1 0x0010020150 |
| #define | A_SCD_WDOG_CNT_1 0x0010020158 |
| #define | A_SCD_WDOG_CFG_1 0x0010020160 |
| #define | A_SCD_TIMER_0 0x0010020070 |
| #define | A_SCD_TIMER_1 0x0010020078 |
| #define | A_SCD_TIMER_2 0x0010020170 |
| #define | A_SCD_TIMER_3 0x0010020178 |
| #define | SCD_NUM_TIMERS 4 |
| #define | A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) |
| #define | A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r)) |
| #define | R_SCD_TIMER_INIT 0x0000000000 |
| #define | R_SCD_TIMER_CNT 0x0000000010 |
| #define | R_SCD_TIMER_CFG 0x0000000020 |
| #define | A_SCD_TIMER_INIT_0 0x0010020070 |
| #define | A_SCD_TIMER_CNT_0 0x0010020080 |
| #define | A_SCD_TIMER_CFG_0 0x0010020090 |
| #define | A_SCD_TIMER_INIT_1 0x0010020078 |
| #define | A_SCD_TIMER_CNT_1 0x0010020088 |
| #define | A_SCD_TIMER_CFG_1 0x0010020098 |
| #define | A_SCD_TIMER_INIT_2 0x0010020170 |
| #define | A_SCD_TIMER_CNT_2 0x0010020180 |
| #define | A_SCD_TIMER_CFG_2 0x0010020190 |
| #define | A_SCD_TIMER_INIT_3 0x0010020178 |
| #define | A_SCD_TIMER_CNT_3 0x0010020188 |
| #define | A_SCD_TIMER_CFG_3 0x0010020198 |
| #define | A_SCD_SYSTEM_REVISION 0x0010020000 |
| #define | A_SCD_SYSTEM_CFG 0x0010020008 |
| #define | A_SCD_SYSTEM_MANUF 0x0010038000 |
| #define | A_ADDR_TRAP_INDEX 0x00100200B0 |
| #define | A_ADDR_TRAP_REG 0x00100200B8 |
| #define | A_ADDR_TRAP_UP_0 0x0010020400 |
| #define | A_ADDR_TRAP_UP_1 0x0010020408 |
| #define | A_ADDR_TRAP_UP_2 0x0010020410 |
| #define | A_ADDR_TRAP_UP_3 0x0010020418 |
| #define | A_ADDR_TRAP_DOWN_0 0x0010020420 |
| #define | A_ADDR_TRAP_DOWN_1 0x0010020428 |
| #define | A_ADDR_TRAP_DOWN_2 0x0010020430 |
| #define | A_ADDR_TRAP_DOWN_3 0x0010020438 |
| #define | A_ADDR_TRAP_CFG_0 0x0010020440 |
| #define | A_ADDR_TRAP_CFG_1 0x0010020448 |
| #define | A_ADDR_TRAP_CFG_2 0x0010020450 |
| #define | A_ADDR_TRAP_CFG_3 0x0010020458 |
| #define | ADDR_TRAP_SPACING 8 |
| #define | NUM_ADDR_TRAP 4 |
| #define | A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING)) |
| #define | A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING)) |
| #define | A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING)) |
| #define | A_IMR_CPU0_BASE 0x0010020000 |
| #define | A_IMR_CPU1_BASE 0x0010022000 |
| #define | IMR_REGISTER_SPACING 0x2000 |
| #define | IMR_REGISTER_SPACING_SHIFT 13 |
| #define | A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) |
| #define | A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) |
| #define | R_IMR_INTERRUPT_DIAG 0x0010 |
| #define | R_IMR_INTERRUPT_LDT 0x0018 |
| #define | R_IMR_INTERRUPT_MASK 0x0028 |
| #define | R_IMR_INTERRUPT_TRACE 0x0038 |
| #define | R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 |
| #define | R_IMR_LDT_INTERRUPT_SET 0x0048 |
| #define | R_IMR_LDT_INTERRUPT 0x0018 |
| #define | R_IMR_LDT_INTERRUPT_CLR 0x0020 |
| #define | R_IMR_MAILBOX_CPU 0x00c0 |
| #define | R_IMR_ALIAS_MAILBOX_CPU 0x1000 |
| #define | R_IMR_MAILBOX_SET_CPU 0x00C8 |
| #define | R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 |
| #define | R_IMR_MAILBOX_CLR_CPU 0x00D0 |
| #define | R_IMR_INTERRUPT_STATUS_BASE 0x0100 |
| #define | R_IMR_INTERRUPT_STATUS_COUNT 7 |
| #define | R_IMR_INTERRUPT_MAP_BASE 0x0200 |
| #define | R_IMR_INTERRUPT_MAP_COUNT 64 |
| #define | A_MAILBOX_REGISTER(reg, cpu) (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg) |
| #define | A_SCD_PERF_CNT_CFG 0x00100204C0 |
| #define | A_SCD_PERF_CNT_0 0x00100204D0 |
| #define | A_SCD_PERF_CNT_1 0x00100204D8 |
| #define | A_SCD_PERF_CNT_2 0x00100204E0 |
| #define | A_SCD_PERF_CNT_3 0x00100204E8 |
| #define | SCD_NUM_PERF_CNT 4 |
| #define | SCD_PERF_CNT_SPACING 8 |
| #define | A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING)) |
| #define | A_SCD_BUS_ERR_STATUS 0x0010020880 |
| #define | A_BUS_ERR_DATA_0 0x00100208A0 |
| #define | A_BUS_ERR_DATA_1 0x00100208A8 |
| #define | A_BUS_ERR_DATA_2 0x00100208B0 |
| #define | A_BUS_ERR_DATA_3 0x00100208B8 |
| #define | A_BUS_L2_ERRORS 0x00100208C0 |
| #define | A_BUS_MEM_IO_ERRORS 0x00100208C8 |
| #define | A_SCD_JTAG_BASE 0x0010000000 |
| #define | A_SCD_TRACE_CFG 0x0010020A00 |
| #define | A_SCD_TRACE_READ 0x0010020A08 |
| #define | A_SCD_TRACE_EVENT_0 0x0010020A20 |
| #define | A_SCD_TRACE_EVENT_1 0x0010020A28 |
| #define | A_SCD_TRACE_EVENT_2 0x0010020A30 |
| #define | A_SCD_TRACE_EVENT_3 0x0010020A38 |
| #define | A_SCD_TRACE_SEQUENCE_0 0x0010020A40 |
| #define | A_SCD_TRACE_SEQUENCE_1 0x0010020A48 |
| #define | A_SCD_TRACE_SEQUENCE_2 0x0010020A50 |
| #define | A_SCD_TRACE_SEQUENCE_3 0x0010020A58 |
| #define | A_SCD_TRACE_EVENT_4 0x0010020A60 |
| #define | A_SCD_TRACE_EVENT_5 0x0010020A68 |
| #define | A_SCD_TRACE_EVENT_6 0x0010020A70 |
| #define | A_SCD_TRACE_EVENT_7 0x0010020A78 |
| #define | A_SCD_TRACE_SEQUENCE_4 0x0010020A80 |
| #define | A_SCD_TRACE_SEQUENCE_5 0x0010020A88 |
| #define | A_SCD_TRACE_SEQUENCE_6 0x0010020A90 |
| #define | A_SCD_TRACE_SEQUENCE_7 0x0010020A98 |
| #define | TRACE_REGISTER_SPACING 8 |
| #define | TRACE_NUM_REGISTERS 8 |
| #define | A_SCD_TRACE_EVENT(n) |
| #define | A_SCD_TRACE_SEQUENCE(n) |
| #define | A_DM_0 0x0010020B00 |
| #define | A_DM_1 0x0010020B20 |
| #define | A_DM_2 0x0010020B40 |
| #define | A_DM_3 0x0010020B60 |
| #define | DM_REGISTER_SPACING 0x20 |
| #define | DM_NUM_CHANNELS 4 |
| #define | A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) |
| #define | A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) |
| #define | R_DM_DSCR_BASE 0x0000000000 |
| #define | R_DM_DSCR_COUNT 0x0000000008 |
| #define | R_DM_CUR_DSCR_ADDR 0x0000000010 |
| #define | R_DM_DSCR_BASE_DEBUG 0x0000000018 |
| #define A_ADDR_TRAP_CFG | ( | n | ) | (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING)) |
Definition at line 704 of file sb1250_regs.h.
| #define A_ADDR_TRAP_CFG_0 0x0010020440 |
Definition at line 692 of file sb1250_regs.h.
| #define A_ADDR_TRAP_CFG_1 0x0010020448 |
Definition at line 693 of file sb1250_regs.h.
| #define A_ADDR_TRAP_CFG_2 0x0010020450 |
Definition at line 694 of file sb1250_regs.h.
| #define A_ADDR_TRAP_CFG_3 0x0010020458 |
Definition at line 695 of file sb1250_regs.h.
| #define A_ADDR_TRAP_DOWN | ( | n | ) | (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING)) |
Definition at line 703 of file sb1250_regs.h.
| #define A_ADDR_TRAP_DOWN_0 0x0010020420 |
Definition at line 688 of file sb1250_regs.h.
| #define A_ADDR_TRAP_DOWN_1 0x0010020428 |
Definition at line 689 of file sb1250_regs.h.
| #define A_ADDR_TRAP_DOWN_2 0x0010020430 |
Definition at line 690 of file sb1250_regs.h.
| #define A_ADDR_TRAP_DOWN_3 0x0010020438 |
Definition at line 691 of file sb1250_regs.h.
| #define A_ADDR_TRAP_INDEX 0x00100200B0 |
Definition at line 682 of file sb1250_regs.h.
| #define A_ADDR_TRAP_REG 0x00100200B8 |
Definition at line 683 of file sb1250_regs.h.
| #define A_ADDR_TRAP_UP | ( | n | ) | (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING)) |
Definition at line 702 of file sb1250_regs.h.
| #define A_ADDR_TRAP_UP_0 0x0010020400 |
Definition at line 684 of file sb1250_regs.h.
| #define A_ADDR_TRAP_UP_1 0x0010020408 |
Definition at line 685 of file sb1250_regs.h.
| #define A_ADDR_TRAP_UP_2 0x0010020410 |
Definition at line 686 of file sb1250_regs.h.
| #define A_ADDR_TRAP_UP_3 0x0010020418 |
Definition at line 687 of file sb1250_regs.h.
| #define A_BUS_ERR_DATA_0 0x00100208A0 |
Definition at line 768 of file sb1250_regs.h.
| #define A_BUS_ERR_DATA_1 0x00100208A8 |
Definition at line 769 of file sb1250_regs.h.
| #define A_BUS_ERR_DATA_2 0x00100208B0 |
Definition at line 770 of file sb1250_regs.h.
| #define A_BUS_ERR_DATA_3 0x00100208B8 |
Definition at line 771 of file sb1250_regs.h.
| #define A_BUS_L2_ERRORS 0x00100208C0 |
Definition at line 772 of file sb1250_regs.h.
| #define A_BUS_MEM_IO_ERRORS 0x00100208C8 |
Definition at line 773 of file sb1250_regs.h.
| #define A_DM_0 0x0010020B00 |
Definition at line 817 of file sb1250_regs.h.
| #define A_DM_1 0x0010020B20 |
Definition at line 818 of file sb1250_regs.h.
| #define A_DM_2 0x0010020B40 |
Definition at line 819 of file sb1250_regs.h.
| #define A_DM_3 0x0010020B60 |
Definition at line 820 of file sb1250_regs.h.
| #define A_DM_BASE | ( | idx | ) | (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) |
Definition at line 823 of file sb1250_regs.h.
Definition at line 824 of file sb1250_regs.h.
| #define A_DUART_AUX_CTRL 0x0010060310 |
Definition at line 361 of file sb1250_regs.h.
| #define A_DUART_CLEAR_OPR 0x00100603C0 |
Definition at line 372 of file sb1250_regs.h.
| #define A_DUART_CLK_SEL_A 0x0010060130 |
Definition at line 347 of file sb1250_regs.h.
| #define A_DUART_CLK_SEL_B 0x0010060230 |
Definition at line 355 of file sb1250_regs.h.
| #define A_DUART_CMD_A 0x0010060150 |
Definition at line 348 of file sb1250_regs.h.
| #define A_DUART_CMD_B 0x0010060250 |
Definition at line 356 of file sb1250_regs.h.
| #define A_DUART_IMR 0x00100603A0 |
Definition at line 370 of file sb1250_regs.h.
| #define A_DUART_IMR_A 0x0010060330 |
Definition at line 363 of file sb1250_regs.h.
| #define A_DUART_IMR_B 0x0010060350 |
Definition at line 365 of file sb1250_regs.h.
| #define A_DUART_IN_PORT 0x0010060380 |
Definition at line 368 of file sb1250_regs.h.
| #define A_DUART_INPORT_CHNG 0x0010060300 |
Definition at line 360 of file sb1250_regs.h.
| #define A_DUART_INPORT_CHNG_A 0x00100603D0 |
Definition at line 373 of file sb1250_regs.h.
| #define A_DUART_INPORT_CHNG_B 0x00100603E0 |
Definition at line 374 of file sb1250_regs.h.
| #define A_DUART_ISR 0x0010060390 |
Definition at line 369 of file sb1250_regs.h.
| #define A_DUART_ISR_A 0x0010060320 |
Definition at line 362 of file sb1250_regs.h.
| #define A_DUART_ISR_B 0x0010060340 |
Definition at line 364 of file sb1250_regs.h.
| #define A_DUART_MODE_REG_1_A 0x0010060100 |
Definition at line 344 of file sb1250_regs.h.
| #define A_DUART_MODE_REG_1_B 0x0010060200 |
Definition at line 352 of file sb1250_regs.h.
| #define A_DUART_MODE_REG_2_A 0x0010060110 |
Definition at line 345 of file sb1250_regs.h.
| #define A_DUART_MODE_REG_2_B 0x0010060210 |
Definition at line 353 of file sb1250_regs.h.
| #define A_DUART_OPCR 0x0010060370 |
Definition at line 367 of file sb1250_regs.h.
| #define A_DUART_OUT_PORT 0x0010060360 |
Definition at line 366 of file sb1250_regs.h.
| #define A_DUART_RX_HOLD_A 0x0010060160 |
Definition at line 349 of file sb1250_regs.h.
| #define A_DUART_RX_HOLD_B 0x0010060260 |
Definition at line 357 of file sb1250_regs.h.
| #define A_DUART_SET_OPR 0x00100603B0 |
Definition at line 371 of file sb1250_regs.h.
| #define A_DUART_STATUS_A 0x0010060120 |
Definition at line 346 of file sb1250_regs.h.
| #define A_DUART_STATUS_B 0x0010060220 |
Definition at line 354 of file sb1250_regs.h.
| #define A_DUART_TX_HOLD_A 0x0010060170 |
Definition at line 350 of file sb1250_regs.h.
| #define A_DUART_TX_HOLD_B 0x0010060270 |
Definition at line 358 of file sb1250_regs.h.
| #define A_GPIO_BASE 0x0010061A80 |
Definition at line 554 of file sb1250_regs.h.
| #define A_GPIO_CLR_EDGE 0x0010061A80 |
Definition at line 545 of file sb1250_regs.h.
| #define A_GPIO_DIRECTION 0x0010061AA8 |
Definition at line 550 of file sb1250_regs.h.
| #define A_GPIO_GLITCH 0x0010061A98 |
Definition at line 548 of file sb1250_regs.h.
| #define A_GPIO_INPUT_INVERT 0x0010061A90 |
Definition at line 547 of file sb1250_regs.h.
| #define A_GPIO_INT_TYPE 0x0010061A88 |
Definition at line 546 of file sb1250_regs.h.
| #define A_GPIO_PIN_CLR 0x0010061AB0 |
Definition at line 551 of file sb1250_regs.h.
| #define A_GPIO_PIN_SET 0x0010061AB8 |
Definition at line 552 of file sb1250_regs.h.
| #define A_GPIO_READ 0x0010061AA0 |
Definition at line 549 of file sb1250_regs.h.
| #define A_IMR_CPU0_BASE 0x0010020000 |
Definition at line 711 of file sb1250_regs.h.
| #define A_IMR_CPU1_BASE 0x0010022000 |
Definition at line 712 of file sb1250_regs.h.
| #define A_IMR_MAPPER | ( | cpu | ) | (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) |
Definition at line 716 of file sb1250_regs.h.
| #define A_IMR_REGISTER | ( | cpu, | |
| reg | |||
| ) | (A_IMR_MAPPER(cpu)+(reg)) |
Definition at line 717 of file sb1250_regs.h.
| #define A_IO_DRIVE | ( | x | ) | (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) |
Definition at line 528 of file sb1250_regs.h.
| #define A_IO_DRIVE_0 0x0010061300 |
Definition at line 521 of file sb1250_regs.h.
| #define A_IO_DRIVE_1 0x0010061308 |
Definition at line 522 of file sb1250_regs.h.
| #define A_IO_DRIVE_2 0x0010061310 |
Definition at line 523 of file sb1250_regs.h.
| #define A_IO_DRIVE_3 0x0010061318 |
Definition at line 524 of file sb1250_regs.h.
| #define A_IO_DRIVE_BASE A_IO_DRIVE_0 |
Definition at line 525 of file sb1250_regs.h.
| #define A_IO_EXT_BASE 0x0010061000 |
Definition at line 491 of file sb1250_regs.h.
| #define A_IO_EXT_CFG_BASE 0x0010061000 |
Definition at line 494 of file sb1250_regs.h.
| #define A_IO_EXT_CS_BASE | ( | cs | ) | (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) |
Definition at line 501 of file sb1250_regs.h.
| #define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 |
Definition at line 495 of file sb1250_regs.h.
| #define A_IO_EXT_REG | ( | r | ) | (A_IO_EXT_BASE + (r)) |
Definition at line 492 of file sb1250_regs.h.
| #define A_IO_EXT_START_ADDR_BASE 0x0010061200 |
Definition at line 496 of file sb1250_regs.h.
| #define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 |
Definition at line 497 of file sb1250_regs.h.
| #define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 |
Definition at line 498 of file sb1250_regs.h.
| #define A_IO_INTERRUPT_ADDR0 0x0010061A30 |
Definition at line 516 of file sb1250_regs.h.
| #define A_IO_INTERRUPT_ADDR1 0x0010061A40 |
Definition at line 517 of file sb1250_regs.h.
| #define A_IO_INTERRUPT_DATA0 0x0010061A10 |
Definition at line 512 of file sb1250_regs.h.
| #define A_IO_INTERRUPT_DATA1 0x0010061A18 |
Definition at line 513 of file sb1250_regs.h.
| #define A_IO_INTERRUPT_DATA2 0x0010061A20 |
Definition at line 514 of file sb1250_regs.h.
| #define A_IO_INTERRUPT_DATA3 0x0010061A28 |
Definition at line 515 of file sb1250_regs.h.
| #define A_IO_INTERRUPT_PARITY 0x0010061A50 |
Definition at line 518 of file sb1250_regs.h.
| #define A_IO_INTERRUPT_STATUS 0x0010061A00 |
Definition at line 511 of file sb1250_regs.h.
| #define A_IO_PCMCIA_CFG 0x0010061A60 |
Definition at line 519 of file sb1250_regs.h.
| #define A_IO_PCMCIA_STATUS 0x0010061A70 |
Definition at line 520 of file sb1250_regs.h.
| #define A_MAC_BASE_0 0x0010064000 |
Definition at line 149 of file sb1250_regs.h.
| #define A_MAC_BASE_1 0x0010065000 |
Definition at line 150 of file sb1250_regs.h.
| #define A_MAC_CHANNEL_BASE | ( | macnum | ) |
Definition at line 165 of file sb1250_regs.h.
| #define A_MAC_DMA_CHANNEL_BASE | ( | macnum, | |
| txrx, | |||
| chan | |||
| ) |
Definition at line 176 of file sb1250_regs.h.
Definition at line 187 of file sb1250_regs.h.
| #define A_MAC_REGISTER | ( | macnum, | |
| reg | |||
| ) |
Definition at line 169 of file sb1250_regs.h.
| #define A_MAILBOX_REGISTER | ( | reg, | |
| cpu | |||
| ) | (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg) |
Definition at line 742 of file sb1250_regs.h.
| #define A_SCD_BUS_ERR_STATUS 0x0010020880 |
Definition at line 763 of file sb1250_regs.h.
| #define A_SCD_JTAG_BASE 0x0010000000 |
Definition at line 779 of file sb1250_regs.h.
| #define A_SCD_PERF_CNT | ( | n | ) | (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING)) |
Definition at line 757 of file sb1250_regs.h.
| #define A_SCD_PERF_CNT_0 0x00100204D0 |
Definition at line 750 of file sb1250_regs.h.
| #define A_SCD_PERF_CNT_1 0x00100204D8 |
Definition at line 751 of file sb1250_regs.h.
| #define A_SCD_PERF_CNT_2 0x00100204E0 |
Definition at line 752 of file sb1250_regs.h.
| #define A_SCD_PERF_CNT_3 0x00100204E8 |
Definition at line 753 of file sb1250_regs.h.
| #define A_SCD_PERF_CNT_CFG 0x00100204C0 |
Definition at line 749 of file sb1250_regs.h.
| #define A_SCD_SYSTEM_CFG 0x0010020008 |
Definition at line 675 of file sb1250_regs.h.
| #define A_SCD_SYSTEM_MANUF 0x0010038000 |
Definition at line 676 of file sb1250_regs.h.
| #define A_SCD_SYSTEM_REVISION 0x0010020000 |
Definition at line 674 of file sb1250_regs.h.
| #define A_SCD_TIMER_0 0x0010020070 |
Definition at line 632 of file sb1250_regs.h.
| #define A_SCD_TIMER_1 0x0010020078 |
Definition at line 633 of file sb1250_regs.h.
| #define A_SCD_TIMER_2 0x0010020170 |
Definition at line 634 of file sb1250_regs.h.
| #define A_SCD_TIMER_3 0x0010020178 |
Definition at line 635 of file sb1250_regs.h.
| #define A_SCD_TIMER_BASE | ( | w | ) | (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) |
Definition at line 637 of file sb1250_regs.h.
| #define A_SCD_TIMER_CFG_0 0x0010020090 |
Definition at line 646 of file sb1250_regs.h.
| #define A_SCD_TIMER_CFG_1 0x0010020098 |
Definition at line 650 of file sb1250_regs.h.
| #define A_SCD_TIMER_CFG_2 0x0010020190 |
Definition at line 654 of file sb1250_regs.h.
| #define A_SCD_TIMER_CFG_3 0x0010020198 |
Definition at line 658 of file sb1250_regs.h.
| #define A_SCD_TIMER_CNT_0 0x0010020080 |
Definition at line 645 of file sb1250_regs.h.
| #define A_SCD_TIMER_CNT_1 0x0010020088 |
Definition at line 649 of file sb1250_regs.h.
| #define A_SCD_TIMER_CNT_2 0x0010020180 |
Definition at line 653 of file sb1250_regs.h.
| #define A_SCD_TIMER_CNT_3 0x0010020188 |
Definition at line 657 of file sb1250_regs.h.
| #define A_SCD_TIMER_INIT_0 0x0010020070 |
Definition at line 644 of file sb1250_regs.h.
| #define A_SCD_TIMER_INIT_1 0x0010020078 |
Definition at line 648 of file sb1250_regs.h.
| #define A_SCD_TIMER_INIT_2 0x0010020170 |
Definition at line 652 of file sb1250_regs.h.
| #define A_SCD_TIMER_INIT_3 0x0010020178 |
Definition at line 656 of file sb1250_regs.h.
| #define A_SCD_TIMER_REGISTER | ( | w, | |
| r | |||
| ) | (A_SCD_TIMER_BASE(w) + (r)) |
Definition at line 638 of file sb1250_regs.h.
| #define A_SCD_TRACE_CFG 0x0010020A00 |
Definition at line 785 of file sb1250_regs.h.
| #define A_SCD_TRACE_EVENT | ( | n | ) |
Definition at line 806 of file sb1250_regs.h.
| #define A_SCD_TRACE_EVENT_0 0x0010020A20 |
Definition at line 787 of file sb1250_regs.h.
| #define A_SCD_TRACE_EVENT_1 0x0010020A28 |
Definition at line 788 of file sb1250_regs.h.
| #define A_SCD_TRACE_EVENT_2 0x0010020A30 |
Definition at line 789 of file sb1250_regs.h.
| #define A_SCD_TRACE_EVENT_3 0x0010020A38 |
Definition at line 790 of file sb1250_regs.h.
| #define A_SCD_TRACE_EVENT_4 0x0010020A60 |
Definition at line 795 of file sb1250_regs.h.
| #define A_SCD_TRACE_EVENT_5 0x0010020A68 |
Definition at line 796 of file sb1250_regs.h.
| #define A_SCD_TRACE_EVENT_6 0x0010020A70 |
Definition at line 797 of file sb1250_regs.h.
| #define A_SCD_TRACE_EVENT_7 0x0010020A78 |
Definition at line 798 of file sb1250_regs.h.
| #define A_SCD_TRACE_READ 0x0010020A08 |
Definition at line 786 of file sb1250_regs.h.
| #define A_SCD_TRACE_SEQUENCE | ( | n | ) |
Definition at line 809 of file sb1250_regs.h.
| #define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 |
Definition at line 791 of file sb1250_regs.h.
| #define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 |
Definition at line 792 of file sb1250_regs.h.
| #define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 |
Definition at line 793 of file sb1250_regs.h.
| #define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 |
Definition at line 794 of file sb1250_regs.h.
| #define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 |
Definition at line 799 of file sb1250_regs.h.
| #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 |
Definition at line 800 of file sb1250_regs.h.
| #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 |
Definition at line 801 of file sb1250_regs.h.
| #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 |
Definition at line 802 of file sb1250_regs.h.
| #define A_SCD_WDOG_0 0x0010020050 |
Definition at line 609 of file sb1250_regs.h.
| #define A_SCD_WDOG_1 0x0010020150 |
Definition at line 610 of file sb1250_regs.h.
| #define A_SCD_WDOG_BASE | ( | w | ) | (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) |
Definition at line 613 of file sb1250_regs.h.
| #define A_SCD_WDOG_CFG_0 0x0010020060 |
Definition at line 622 of file sb1250_regs.h.
| #define A_SCD_WDOG_CFG_1 0x0010020160 |
Definition at line 626 of file sb1250_regs.h.
| #define A_SCD_WDOG_CNT_0 0x0010020058 |
Definition at line 621 of file sb1250_regs.h.
| #define A_SCD_WDOG_CNT_1 0x0010020158 |
Definition at line 625 of file sb1250_regs.h.
| #define A_SCD_WDOG_INIT_0 0x0010020050 |
Definition at line 620 of file sb1250_regs.h.
| #define A_SCD_WDOG_INIT_1 0x0010020150 |
Definition at line 624 of file sb1250_regs.h.
| #define A_SCD_WDOG_REGISTER | ( | w, | |
| r | |||
| ) | (A_SCD_WDOG_BASE(w) + (r)) |
Definition at line 614 of file sb1250_regs.h.
| #define A_SMB_0 0x0010060000 |
Definition at line 586 of file sb1250_regs.h.
| #define A_SMB_1 0x0010060008 |
Definition at line 587 of file sb1250_regs.h.
| #define A_SMB_BASE | ( | idx | ) | (A_SMB_0+(idx)*SMB_REGISTER_SPACING) |
Definition at line 589 of file sb1250_regs.h.
| #define A_SMB_CMD_0 0x0010060030 |
Definition at line 575 of file sb1250_regs.h.
| #define A_SMB_CMD_1 0x0010060038 |
Definition at line 576 of file sb1250_regs.h.
| #define A_SMB_CONTROL_0 0x0010060060 |
Definition at line 581 of file sb1250_regs.h.
| #define A_SMB_CONTROL_1 0x0010060068 |
Definition at line 582 of file sb1250_regs.h.
| #define A_SMB_DATA_0 0x0010060050 |
Definition at line 579 of file sb1250_regs.h.
| #define A_SMB_DATA_1 0x0010060058 |
Definition at line 580 of file sb1250_regs.h.
| #define A_SMB_FREQ_0 0x0010060010 |
Definition at line 571 of file sb1250_regs.h.
| #define A_SMB_FREQ_1 0x0010060018 |
Definition at line 572 of file sb1250_regs.h.
| #define A_SMB_PEC_0 0x0010060070 |
Definition at line 583 of file sb1250_regs.h.
| #define A_SMB_PEC_1 0x0010060078 |
Definition at line 584 of file sb1250_regs.h.
| #define A_SMB_REGISTER | ( | idx, | |
| reg | |||
| ) | (A_SMB_BASE(idx)+(reg)) |
Definition at line 590 of file sb1250_regs.h.
| #define A_SMB_START_0 0x0010060040 |
Definition at line 577 of file sb1250_regs.h.
| #define A_SMB_START_1 0x0010060048 |
Definition at line 578 of file sb1250_regs.h.
| #define A_SMB_STATUS_0 0x0010060020 |
Definition at line 573 of file sb1250_regs.h.
| #define A_SMB_STATUS_1 0x0010060028 |
Definition at line 574 of file sb1250_regs.h.
| #define A_SMB_XTRA_0 0x0010060000 |
Definition at line 569 of file sb1250_regs.h.
| #define A_SMB_XTRA_1 0x0010060008 |
Definition at line 570 of file sb1250_regs.h.
| #define ADDR_TRAP_SPACING 8 |
Definition at line 700 of file sb1250_regs.h.
| #define DM_NUM_CHANNELS 4 |
Definition at line 822 of file sb1250_regs.h.
| #define DM_REGISTER_SPACING 0x20 |
Definition at line 821 of file sb1250_regs.h.
| #define DMA_RX 0 |
Definition at line 158 of file sb1250_regs.h.
| #define DMA_TX 1 |
Definition at line 159 of file sb1250_regs.h.
| #define IMR_REGISTER_SPACING 0x2000 |
Definition at line 713 of file sb1250_regs.h.
| #define IMR_REGISTER_SPACING_SHIFT 13 |
Definition at line 714 of file sb1250_regs.h.
| #define IO_DRIVE_REGISTER_SPACING 8 |
Definition at line 526 of file sb1250_regs.h.
| #define IO_EXT_CFG_COUNT 8 |
Definition at line 489 of file sb1250_regs.h.
| #define IO_EXT_REGISTER_SPACING 8 |
Definition at line 500 of file sb1250_regs.h.
| #define MAC_ADDR_COUNT 8 |
Definition at line 266 of file sb1250_regs.h.
| #define MAC_CHMAP_COUNT 4 |
Definition at line 267 of file sb1250_regs.h.
| #define MAC_DMA_CHANNEL_SPACING 0x0100 |
Definition at line 157 of file sb1250_regs.h.
| #define MAC_DMA_TXRX_SPACING 0x0400 |
Definition at line 156 of file sb1250_regs.h.
| #define MAC_HASH_COUNT 8 |
Definition at line 265 of file sb1250_regs.h.
Definition at line 160 of file sb1250_regs.h.
| #define MAC_NUM_PORTS 3 |
Definition at line 163 of file sb1250_regs.h.
| #define MAC_SPACING 0x1000 |
Definition at line 155 of file sb1250_regs.h.
| #define NUM_ADDR_TRAP 4 |
Definition at line 701 of file sb1250_regs.h.
| #define R_DM_CUR_DSCR_ADDR 0x0000000010 |
Definition at line 828 of file sb1250_regs.h.
| #define R_DM_DSCR_BASE 0x0000000000 |
Definition at line 826 of file sb1250_regs.h.
| #define R_DM_DSCR_BASE_DEBUG 0x0000000018 |
Definition at line 829 of file sb1250_regs.h.
| #define R_DM_DSCR_COUNT 0x0000000008 |
Definition at line 827 of file sb1250_regs.h.
| #define R_DUART_AUX_CTRL 0x010 |
Definition at line 325 of file sb1250_regs.h.
| #define R_DUART_CLEAR_OPR 0x0C0 |
Definition at line 335 of file sb1250_regs.h.
| #define R_DUART_CLK_SEL 0x030 |
Definition at line 289 of file sb1250_regs.h.
| #define R_DUART_CMD 0x050 |
Definition at line 290 of file sb1250_regs.h.
| #define R_DUART_IMR_A 0x030 |
Definition at line 327 of file sb1250_regs.h.
| #define R_DUART_IMR_B 0x050 |
Definition at line 329 of file sb1250_regs.h.
| #define R_DUART_IN_CHNG_A 0x0D0 |
Definition at line 336 of file sb1250_regs.h.
| #define R_DUART_IN_CHNG_B 0x0E0 |
Definition at line 337 of file sb1250_regs.h.
| #define R_DUART_IN_PORT 0x080 |
Definition at line 332 of file sb1250_regs.h.
| #define R_DUART_ISR_A 0x020 |
Definition at line 326 of file sb1250_regs.h.
| #define R_DUART_ISR_B 0x040 |
Definition at line 328 of file sb1250_regs.h.
| #define R_DUART_MODE_REG_1 0x000 |
Definition at line 286 of file sb1250_regs.h.
| #define R_DUART_MODE_REG_2 0x010 |
Definition at line 287 of file sb1250_regs.h.
| #define R_DUART_OPCR 0x070 |
Definition at line 331 of file sb1250_regs.h.
| #define R_DUART_OUT_PORT 0x060 |
Definition at line 330 of file sb1250_regs.h.
| #define R_DUART_RX_HOLD 0x060 |
Definition at line 291 of file sb1250_regs.h.
| #define R_DUART_SET_OPR 0x0B0 |
Definition at line 334 of file sb1250_regs.h.
| #define R_DUART_STATUS 0x020 |
Definition at line 288 of file sb1250_regs.h.
| #define R_DUART_TX_HOLD 0x070 |
Definition at line 292 of file sb1250_regs.h.
| #define R_GPIO_CLR_EDGE 0x00 |
Definition at line 556 of file sb1250_regs.h.
| #define R_GPIO_DIRECTION 0x28 |
Definition at line 561 of file sb1250_regs.h.
| #define R_GPIO_GLITCH 0x18 |
Definition at line 559 of file sb1250_regs.h.
| #define R_GPIO_INPUT_INVERT 0x10 |
Definition at line 558 of file sb1250_regs.h.
| #define R_GPIO_INT_TYPE 0x08 |
Definition at line 557 of file sb1250_regs.h.
| #define R_GPIO_PIN_CLR 0x30 |
Definition at line 562 of file sb1250_regs.h.
| #define R_GPIO_PIN_SET 0x38 |
Definition at line 563 of file sb1250_regs.h.
| #define R_GPIO_READ 0x20 |
Definition at line 560 of file sb1250_regs.h.
| #define R_IMR_ALIAS_MAILBOX_CPU 0x1000 |
Definition at line 728 of file sb1250_regs.h.
| #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 |
Definition at line 730 of file sb1250_regs.h.
| #define R_IMR_INTERRUPT_DIAG 0x0010 |
Definition at line 719 of file sb1250_regs.h.
| #define R_IMR_INTERRUPT_LDT 0x0018 |
Definition at line 720 of file sb1250_regs.h.
| #define R_IMR_INTERRUPT_MAP_BASE 0x0200 |
Definition at line 734 of file sb1250_regs.h.
| #define R_IMR_INTERRUPT_MAP_COUNT 64 |
Definition at line 735 of file sb1250_regs.h.
| #define R_IMR_INTERRUPT_MASK 0x0028 |
Definition at line 721 of file sb1250_regs.h.
| #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 |
Definition at line 723 of file sb1250_regs.h.
| #define R_IMR_INTERRUPT_STATUS_BASE 0x0100 |
Definition at line 732 of file sb1250_regs.h.
| #define R_IMR_INTERRUPT_STATUS_COUNT 7 |
Definition at line 733 of file sb1250_regs.h.
| #define R_IMR_INTERRUPT_TRACE 0x0038 |
Definition at line 722 of file sb1250_regs.h.
| #define R_IMR_LDT_INTERRUPT 0x0018 |
Definition at line 725 of file sb1250_regs.h.
| #define R_IMR_LDT_INTERRUPT_CLR 0x0020 |
Definition at line 726 of file sb1250_regs.h.
| #define R_IMR_LDT_INTERRUPT_SET 0x0048 |
Definition at line 724 of file sb1250_regs.h.
| #define R_IMR_MAILBOX_CLR_CPU 0x00D0 |
Definition at line 731 of file sb1250_regs.h.
| #define R_IMR_MAILBOX_CPU 0x00c0 |
Definition at line 727 of file sb1250_regs.h.
| #define R_IMR_MAILBOX_SET_CPU 0x00C8 |
Definition at line 729 of file sb1250_regs.h.
| #define R_IO_DRIVE | ( | x | ) | ((x)*IO_DRIVE_REGISTER_SPACING) |
Definition at line 527 of file sb1250_regs.h.
| #define R_IO_EXT_CFG 0x0000 |
Definition at line 504 of file sb1250_regs.h.
| #define R_IO_EXT_MULT_SIZE 0x0100 |
Definition at line 505 of file sb1250_regs.h.
| #define R_IO_EXT_REG | ( | reg, | |
| cs | |||
| ) | ((cs)*IO_EXT_REGISTER_SPACING + (reg)) |
Definition at line 502 of file sb1250_regs.h.
| #define R_IO_EXT_START_ADDR 0x0200 |
Definition at line 506 of file sb1250_regs.h.
| #define R_IO_EXT_TIME_CFG0 0x0600 |
Definition at line 507 of file sb1250_regs.h.
| #define R_IO_EXT_TIME_CFG1 0x0700 |
Definition at line 508 of file sb1250_regs.h.
| #define R_IO_INTERRUPT_ADDR0 0x0A30 |
Definition at line 535 of file sb1250_regs.h.
| #define R_IO_INTERRUPT_ADDR1 0x0A40 |
Definition at line 536 of file sb1250_regs.h.
| #define R_IO_INTERRUPT_DATA0 0x0A10 |
Definition at line 531 of file sb1250_regs.h.
| #define R_IO_INTERRUPT_DATA1 0x0A18 |
Definition at line 532 of file sb1250_regs.h.
| #define R_IO_INTERRUPT_DATA2 0x0A20 |
Definition at line 533 of file sb1250_regs.h.
| #define R_IO_INTERRUPT_DATA3 0x0A28 |
Definition at line 534 of file sb1250_regs.h.
| #define R_IO_INTERRUPT_PARITY 0x0A50 |
Definition at line 537 of file sb1250_regs.h.
| #define R_IO_INTERRUPT_STATUS 0x0A00 |
Definition at line 530 of file sb1250_regs.h.
| #define R_IO_PCMCIA_CFG 0x0A60 |
Definition at line 538 of file sb1250_regs.h.
| #define R_IO_PCMCIA_STATUS 0x0A70 |
Definition at line 539 of file sb1250_regs.h.
| #define R_MAC_ADDR_BASE 0x00000280 |
Definition at line 252 of file sb1250_regs.h.
| #define R_MAC_ADFILTER_CFG 0x00000200 |
Definition at line 244 of file sb1250_regs.h.
| #define R_MAC_CFG 0x00000100 |
Definition at line 238 of file sb1250_regs.h.
| #define R_MAC_CHLO0_BASE 0x00000300 |
Definition at line 253 of file sb1250_regs.h.
| #define R_MAC_CHUP0_BASE 0x00000320 |
Definition at line 254 of file sb1250_regs.h.
| #define R_MAC_DEBUG_STATUS 0x00000448 |
Definition at line 263 of file sb1250_regs.h.
| #define R_MAC_DMA_CHANNEL_BASE | ( | txrx, | |
| chan | |||
| ) |
Definition at line 182 of file sb1250_regs.h.
| #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ |
Definition at line 174 of file sb1250_regs.h.
| #define R_MAC_DMA_CONFIG0 0x00000000 |
Definition at line 199 of file sb1250_regs.h.
| #define R_MAC_DMA_CONFIG1 0x00000008 |
Definition at line 200 of file sb1250_regs.h.
| #define R_MAC_DMA_CUR_DSCRA 0x00000020 |
Definition at line 203 of file sb1250_regs.h.
| #define R_MAC_DMA_CUR_DSCRADDR 0x00000030 |
Definition at line 205 of file sb1250_regs.h.
| #define R_MAC_DMA_CUR_DSCRB 0x00000028 |
Definition at line 204 of file sb1250_regs.h.
| #define R_MAC_DMA_DSCR_BASE 0x00000010 |
Definition at line 201 of file sb1250_regs.h.
| #define R_MAC_DMA_DSCR_CNT 0x00000018 |
Definition at line 202 of file sb1250_regs.h.
Definition at line 191 of file sb1250_regs.h.
| #define R_MAC_ENABLE 0x00000400 |
Definition at line 255 of file sb1250_regs.h.
| #define R_MAC_EOPCNT 0x00000120 |
Definition at line 242 of file sb1250_regs.h.
| #define R_MAC_ETHERNET_ADDR 0x00000208 |
Definition at line 245 of file sb1250_regs.h.
| #define R_MAC_FIFO_PTRS 0x00000128 |
Definition at line 243 of file sb1250_regs.h.
| #define R_MAC_FRAMECFG 0x00000118 |
Definition at line 241 of file sb1250_regs.h.
| #define R_MAC_HASH_BASE 0x00000240 |
Definition at line 251 of file sb1250_regs.h.
| #define R_MAC_INT_MASK 0x00000410 |
Definition at line 257 of file sb1250_regs.h.
| #define R_MAC_MDIO 0x00000428 |
Definition at line 259 of file sb1250_regs.h.
| #define R_MAC_PKT_TYPE 0x00000210 |
Definition at line 246 of file sb1250_regs.h.
| #define R_MAC_RMON_COLLISIONS 0x00000008 |
Definition at line 215 of file sb1250_regs.h.
| #define R_MAC_RMON_EX_COL 0x00000018 |
Definition at line 217 of file sb1250_regs.h.
| #define R_MAC_RMON_FCS_ERROR 0x00000020 |
Definition at line 218 of file sb1250_regs.h.
| #define R_MAC_RMON_LATE_COL 0x00000010 |
Definition at line 216 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 |
Definition at line 235 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_BAD 0x00000098 |
Definition at line 228 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_BCAST 0x00000090 |
Definition at line 227 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_BYTES 0x00000080 |
Definition at line 225 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 |
Definition at line 234 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 |
Definition at line 232 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_GOOD 0x000000A0 |
Definition at line 229 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 |
Definition at line 233 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_MCAST 0x00000088 |
Definition at line 226 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_OVERSIZE 0x000000B0 |
Definition at line 231 of file sb1250_regs.h.
| #define R_MAC_RMON_RX_RUNT 0x000000A8 |
Definition at line 230 of file sb1250_regs.h.
| #define R_MAC_RMON_TX_ABORT 0x00000028 |
Definition at line 219 of file sb1250_regs.h.
| #define R_MAC_RMON_TX_BAD 0x00000038 |
Definition at line 221 of file sb1250_regs.h.
| #define R_MAC_RMON_TX_BYTES 0x00000000 |
Definition at line 214 of file sb1250_regs.h.
| #define R_MAC_RMON_TX_GOOD 0x00000040 |
Definition at line 222 of file sb1250_regs.h.
| #define R_MAC_RMON_TX_OVERSIZE 0x00000050 |
Definition at line 224 of file sb1250_regs.h.
| #define R_MAC_RMON_TX_RUNT 0x00000048 |
Definition at line 223 of file sb1250_regs.h.
| #define R_MAC_STATUS 0x00000408 |
Definition at line 256 of file sb1250_regs.h.
| #define R_MAC_THRSH_CFG 0x00000108 |
Definition at line 239 of file sb1250_regs.h.
| #define R_MAC_TXD_CTL 0x00000420 |
Definition at line 258 of file sb1250_regs.h.
| #define R_MAC_VLANTAG 0x00000110 |
Definition at line 240 of file sb1250_regs.h.
| #define R_SCD_TIMER_CFG 0x0000000020 |
Definition at line 642 of file sb1250_regs.h.
| #define R_SCD_TIMER_CNT 0x0000000010 |
Definition at line 641 of file sb1250_regs.h.
| #define R_SCD_TIMER_INIT 0x0000000000 |
Definition at line 640 of file sb1250_regs.h.
| #define R_SCD_WDOG_CFG 0x0000000010 |
Definition at line 618 of file sb1250_regs.h.
| #define R_SCD_WDOG_CNT 0x0000000008 |
Definition at line 617 of file sb1250_regs.h.
| #define R_SCD_WDOG_INIT 0x0000000000 |
Definition at line 616 of file sb1250_regs.h.
| #define R_SMB_CMD 0x0000000030 |
Definition at line 595 of file sb1250_regs.h.
| #define R_SMB_CONTROL 0x0000000060 |
Definition at line 598 of file sb1250_regs.h.
| #define R_SMB_DATA 0x0000000050 |
Definition at line 597 of file sb1250_regs.h.
| #define R_SMB_FREQ 0x0000000010 |
Definition at line 593 of file sb1250_regs.h.
| #define R_SMB_PEC 0x0000000070 |
Definition at line 599 of file sb1250_regs.h.
| #define R_SMB_START 0x0000000040 |
Definition at line 596 of file sb1250_regs.h.
| #define R_SMB_STATUS 0x0000000020 |
Definition at line 594 of file sb1250_regs.h.
| #define R_SMB_XTRA 0x0000000000 |
Definition at line 592 of file sb1250_regs.h.
| #define SCD_NUM_PERF_CNT 4 |
Definition at line 755 of file sb1250_regs.h.
| #define SCD_NUM_TIMERS 4 |
Definition at line 636 of file sb1250_regs.h.
| #define SCD_NUM_WDOGS 2 |
Definition at line 612 of file sb1250_regs.h.
| #define SCD_PERF_CNT_SPACING 8 |
Definition at line 756 of file sb1250_regs.h.
| #define SCD_WDOG_SPACING 0x100 |
Definition at line 611 of file sb1250_regs.h.
| #define SMB_REGISTER_SPACING 0x8 |
Definition at line 588 of file sb1250_regs.h.
| #define TRACE_NUM_REGISTERS 8 |
Definition at line 805 of file sb1250_regs.h.
| #define TRACE_REGISTER_SPACING 8 |
Definition at line 804 of file sb1250_regs.h.
1.8.2