#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/circ_buf.h>
#include <linux/serial.h>
#include <linux/sysrq.h>
#include <linux/console.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/serial_core.h>
Go to the source code of this file.
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| #define | SC26XX_MAJOR 204 |
| |
| #define | SC26XX_MINOR_START 205 |
| |
| #define | SC26XX_NR 2 |
| |
| #define | RD_ISR 0x14 |
| |
| #define | RD_IPR 0x34 |
| |
| #define | WR_ACR 0x10 |
| |
| #define | WR_IMR 0x14 |
| |
| #define | WR_OPCR 0x34 |
| |
| #define | WR_OPR_SET 0x38 |
| |
| #define | WR_OPR_CLR 0x3C |
| |
| #define | READ_SC(p, r) readb((p)->membase + RD_##r) |
| |
| #define | WRITE_SC(p, r, v) writeb((v), (p)->membase + WR_##r) |
| |
| #define | RD_PORT_MRx 0x00 |
| |
| #define | RD_PORT_SR 0x04 |
| |
| #define | RD_PORT_RHR 0x0c |
| |
| #define | WR_PORT_MRx 0x00 |
| |
| #define | WR_PORT_CSR 0x04 |
| |
| #define | WR_PORT_CR 0x08 |
| |
| #define | WR_PORT_THR 0x0c |
| |
| #define | SR_BREAK (1 << 7) |
| |
| #define | SR_FRAME (1 << 6) |
| |
| #define | SR_PARITY (1 << 5) |
| |
| #define | SR_OVERRUN (1 << 4) |
| |
| #define | SR_TXRDY (1 << 2) |
| |
| #define | SR_RXRDY (1 << 0) |
| |
| #define | CR_RES_MR (1 << 4) |
| |
| #define | CR_RES_RX (2 << 4) |
| |
| #define | CR_RES_TX (3 << 4) |
| |
| #define | CR_STRT_BRK (6 << 4) |
| |
| #define | CR_STOP_BRK (7 << 4) |
| |
| #define | CR_DIS_TX (1 << 3) |
| |
| #define | CR_ENA_TX (1 << 2) |
| |
| #define | CR_DIS_RX (1 << 1) |
| |
| #define | CR_ENA_RX (1 << 0) |
| |
| #define | ISR_RXRDYB (1 << 5) |
| |
| #define | ISR_TXRDYB (1 << 4) |
| |
| #define | ISR_RXRDYA (1 << 1) |
| |
| #define | ISR_TXRDYA (1 << 0) |
| |
| #define | IMR_RXRDY (1 << 1) |
| |
| #define | IMR_TXRDY (1 << 0) |
| |
| #define | READ_SC_PORT(p, r) read_sc_port(p, RD_PORT_##r) |
| |
| #define | WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v) |
| |
| #define | SC26XX_CONSOLE NULL |
| |
| #define CR_DIS_RX (1 << 1) |
| #define CR_DIS_TX (1 << 3) |
| #define CR_ENA_RX (1 << 0) |
| #define CR_ENA_TX (1 << 2) |
| #define CR_RES_MR (1 << 4) |
| #define CR_RES_RX (2 << 4) |
| #define CR_RES_TX (3 << 4) |
| #define CR_STOP_BRK (7 << 4) |
| #define CR_STRT_BRK (6 << 4) |
| #define IMR_RXRDY (1 << 1) |
| #define IMR_TXRDY (1 << 0) |
| #define ISR_RXRDYA (1 << 1) |
| #define ISR_RXRDYB (1 << 5) |
| #define ISR_TXRDYA (1 << 0) |
| #define ISR_TXRDYB (1 << 4) |
| #define READ_SC |
( |
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p, |
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r |
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) |
| readb((p)->membase + RD_##r) |
| #define READ_SC_PORT |
( |
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p, |
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r |
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) |
| read_sc_port(p, RD_PORT_##r) |
| #define SC26XX_CONSOLE NULL |
| #define SC26XX_MINOR_START 205 |
| #define SR_BREAK (1 << 7) |
| #define SR_FRAME (1 << 6) |
| #define SR_OVERRUN (1 << 4) |
| #define SR_PARITY (1 << 5) |
| #define SR_RXRDY (1 << 0) |
| #define SR_TXRDY (1 << 2) |
| #define WRITE_SC |
( |
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p, |
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r, |
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v |
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) |
| writeb((v), (p)->membase + WR_##r) |
| #define WRITE_SC_PORT |
( |
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p, |
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r, |
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v |
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) |
| write_sc_port(p, WR_PORT_##r, v) |
| MODULE_ALIAS |
( |
"platform:SC26xx" |
| ) |
|
| MODULE_AUTHOR |
( |
"Thomas Bogendörfer" |
| ) |
|
| module_platform_driver |
( |
sc26xx_driver |
| ) |
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1.8.2