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#define SDRAMC_CR_CAS |
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((x) << 5) |
#define SDRAMC_CR_DBW_16_BITS ( 1 << 7) |
#define SDRAMC_CR_DBW_32_BITS ( 0 << 7) |
#define SDRAMC_CR_NB_2_BANKS ( 0 << 4) |
#define SDRAMC_CR_NB_4_BANKS ( 1 << 4) |
#define SDRAMC_CR_NC_10_BITS ( 2 << 0) |
#define SDRAMC_CR_NC_11_BITS ( 3 << 0) |
#define SDRAMC_CR_NC_8_BITS ( 0 << 0) |
#define SDRAMC_CR_NC_9_BITS ( 1 << 0) |
#define SDRAMC_CR_NR_11_BITS ( 0 << 2) |
#define SDRAMC_CR_NR_12_BITS ( 1 << 2) |
#define SDRAMC_CR_NR_13_BITS ( 2 << 2) |
#define SDRAMC_CR_TRAS |
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((x) << 24) |
#define SDRAMC_CR_TRC |
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((x) << 12) |
#define SDRAMC_CR_TRCD |
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((x) << 20) |
#define SDRAMC_CR_TRP |
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((x) << 16) |
#define SDRAMC_CR_TWR |
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((x) << 8) |
#define SDRAMC_CR_TXSR |
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((x) << 28) |
#define SDRAMC_HSR 0x000c |
#define SDRAMC_HSR_DA ( 1 << 0) |
#define SDRAMC_IDR 0x0018 |
#define SDRAMC_IER 0x0014 |
#define SDRAMC_IMR 0x001c |
#define SDRAMC_ISR 0x0020 |
#define SDRAMC_ISR_RES ( 1 << 0) |
#define SDRAMC_LPR 0x0010 |
#define SDRAMC_LPR_DS |
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((x) << 10) |
#define SDRAMC_LPR_LPCB_DEEP_PDOWN ( 3 << 0) |
#define SDRAMC_LPR_LPCB_INHIBIT ( 0 << 0) |
#define SDRAMC_LPR_LPCB_PDOWN ( 2 << 0) |
#define SDRAMC_LPR_LPCB_SELF_RFR ( 1 << 0) |
#define SDRAMC_LPR_PASR |
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((x) << 4) |
#define SDRAMC_LPR_TCSR |
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((x) << 8) |
#define SDRAMC_LPR_TIMEOUT |
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((x) << 12) |
#define SDRAMC_MDR 0x0024 |
#define SDRAMC_MDR_MD_LOW_PWR_SDRAM ( 1 << 0) |
#define SDRAMC_MDR_MD_SDRAM ( 0 << 0) |
#define SDRAMC_MR_MODE_AUTO_REFRESH ( 4 << 0) |
#define SDRAMC_MR_MODE_BANKS_PRECHARGE ( 2 << 0) |
#define SDRAMC_MR_MODE_EXT_LOAD_MODE ( 5 << 0) |
#define SDRAMC_MR_MODE_LOAD_MODE ( 3 << 0) |
#define SDRAMC_MR_MODE_NOP ( 1 << 0) |
#define SDRAMC_MR_MODE_NORMAL ( 0 << 0) |
#define SDRAMC_MR_MODE_POWER_DOWN ( 6 << 0) |