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setup-sh7760.c
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1 /*
2  * SH7760 Setup
3  *
4  * Copyright (C) 2006 Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License. See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/sh_timer.h>
14 #include <linux/sh_intc.h>
15 #include <linux/serial_sci.h>
16 #include <linux/io.h>
17 
18 enum {
19  UNUSED = 0,
20 
21  /* interrupt sources */
22  IRL0, IRL1, IRL2, IRL3,
23  HUDI, GPIOI, DMAC,
24  IRQ4, IRQ5, IRQ6, IRQ7,
25  HCAN20, HCAN21,
26  SSI0, SSI1,
27  HAC0, HAC1,
28  I2C0, I2C1,
29  USB, LCDC,
30  DMABRG0, DMABRG1, DMABRG2,
31  SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
32  SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
33  SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
34  SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
35  HSPI,
36  MMCIF0, MMCIF1, MMCIF2, MMCIF3,
37  MFI, ADC, CMT,
38  TMU0, TMU1, TMU2,
39  WDT, REF,
40 
41  /* interrupt groups */
42  DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
43 };
44 
45 static struct intc_vect vectors[] __initdata = {
46  INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
47  INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
48  INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
49  INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
50  INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
51  INTC_VECT(DMAC, 0x6c0),
52  INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
53  INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
54  INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
55  INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
56  INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
57  INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
58  INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
59  INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
60  INTC_VECT(DMABRG2, 0xac0),
61  INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
62  INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
63  INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
64  INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
65  INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
66  INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
67  INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
68  INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
69  INTC_VECT(HSPI, 0xc80),
70  INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
71  INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
72  INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
73  INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
74  INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
75  INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
76  INTC_VECT(WDT, 0x560),
77  INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
78 };
79 
80 static struct intc_group groups[] __initdata = {
81  INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
82  INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
83  INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
84  INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
85  INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
86  INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
87 };
88 
89 static struct intc_mask_reg mask_registers[] __initdata = {
90  { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
91  { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
92  SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
93  0, DMABRG0, DMABRG1, DMABRG2,
94  SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
95  SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
96  SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
97  { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
98  { 0, 0, 0, 0, 0, 0, 0, 0,
99  SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
100  HSPI, MMCIF0, MMCIF1, MMCIF2,
101  MMCIF3, 0, 0, 0, 0, 0, 0, 0,
102  0, MFI, 0, 0, 0, 0, ADC, CMT, } },
103 };
104 
105 static struct intc_prio_reg prio_registers[] __initdata = {
106  { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
107  { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
108  { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
109  { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
110  { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
111  { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
112  HAC0, HAC1, I2C0, I2C1 } },
113  { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
114  SCIF1, SCIF2, SIM, HSPI } },
115  { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
116  MFI, 0, ADC, CMT } },
117 };
118 
119 static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
120  mask_registers, prio_registers, NULL);
121 
122 static struct intc_vect vectors_irq[] __initdata = {
123  INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
124  INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
125 };
126 
127 static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
128  mask_registers, prio_registers, NULL);
129 
130 static struct plat_sci_port scif0_platform_data = {
131  .mapbase = 0xfe600000,
132  .flags = UPF_BOOT_AUTOCONF,
133  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
134  .scbrr_algo_id = SCBRR_ALGO_2,
135  .type = PORT_SCIF,
136  .irqs = { evt2irq(0x880),
137  evt2irq(0x8a0),
138  evt2irq(0x8e0),
139  evt2irq(0x8c0) },
140  .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
141 };
142 
143 static struct platform_device scif0_device = {
144  .name = "sh-sci",
145  .id = 0,
146  .dev = {
147  .platform_data = &scif0_platform_data,
148  },
149 };
150 
151 static struct plat_sci_port scif1_platform_data = {
152  .mapbase = 0xfe610000,
153  .flags = UPF_BOOT_AUTOCONF,
154  .type = PORT_SCIF,
155  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
156  .scbrr_algo_id = SCBRR_ALGO_2,
157  .irqs = { evt2irq(0xb00),
158  evt2irq(0xb20),
159  evt2irq(0xb60),
160  evt2irq(0xb40) },
161  .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
162 };
163 
164 static struct platform_device scif1_device = {
165  .name = "sh-sci",
166  .id = 1,
167  .dev = {
168  .platform_data = &scif1_platform_data,
169  },
170 };
171 
172 static struct plat_sci_port scif2_platform_data = {
173  .mapbase = 0xfe620000,
174  .flags = UPF_BOOT_AUTOCONF,
175  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
176  .scbrr_algo_id = SCBRR_ALGO_2,
177  .type = PORT_SCIF,
178  .irqs = { evt2irq(0xb80),
179  evt2irq(0xba0),
180  evt2irq(0xbe0),
181  evt2irq(0xbc0) },
182  .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
183 };
184 
185 static struct platform_device scif2_device = {
186  .name = "sh-sci",
187  .id = 2,
188  .dev = {
189  .platform_data = &scif2_platform_data,
190  },
191 };
192 
193 static struct plat_sci_port scif3_platform_data = {
194  .mapbase = 0xfe480000,
195  .flags = UPF_BOOT_AUTOCONF,
196  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
197  .scbrr_algo_id = SCBRR_ALGO_2,
198  .type = PORT_SCI,
199  .irqs = { evt2irq(0xc00),
200  evt2irq(0xc20),
201  evt2irq(0xc40), },
202  .regshift = 2,
203 };
204 
205 static struct platform_device scif3_device = {
206  .name = "sh-sci",
207  .id = 3,
208  .dev = {
209  .platform_data = &scif3_platform_data,
210  },
211 };
212 
213 static struct sh_timer_config tmu0_platform_data = {
214  .channel_offset = 0x04,
215  .timer_bit = 0,
216  .clockevent_rating = 200,
217 };
218 
219 static struct resource tmu0_resources[] = {
220  [0] = {
221  .start = 0xffd80008,
222  .end = 0xffd80013,
223  .flags = IORESOURCE_MEM,
224  },
225  [1] = {
226  .start = evt2irq(0x400),
227  .flags = IORESOURCE_IRQ,
228  },
229 };
230 
231 static struct platform_device tmu0_device = {
232  .name = "sh_tmu",
233  .id = 0,
234  .dev = {
235  .platform_data = &tmu0_platform_data,
236  },
237  .resource = tmu0_resources,
238  .num_resources = ARRAY_SIZE(tmu0_resources),
239 };
240 
241 static struct sh_timer_config tmu1_platform_data = {
242  .channel_offset = 0x10,
243  .timer_bit = 1,
244  .clocksource_rating = 200,
245 };
246 
247 static struct resource tmu1_resources[] = {
248  [0] = {
249  .start = 0xffd80014,
250  .end = 0xffd8001f,
251  .flags = IORESOURCE_MEM,
252  },
253  [1] = {
254  .start = evt2irq(0x420),
255  .flags = IORESOURCE_IRQ,
256  },
257 };
258 
259 static struct platform_device tmu1_device = {
260  .name = "sh_tmu",
261  .id = 1,
262  .dev = {
263  .platform_data = &tmu1_platform_data,
264  },
265  .resource = tmu1_resources,
266  .num_resources = ARRAY_SIZE(tmu1_resources),
267 };
268 
269 static struct sh_timer_config tmu2_platform_data = {
270  .channel_offset = 0x1c,
271  .timer_bit = 2,
272 };
273 
274 static struct resource tmu2_resources[] = {
275  [0] = {
276  .start = 0xffd80020,
277  .end = 0xffd8002f,
278  .flags = IORESOURCE_MEM,
279  },
280  [1] = {
281  .start = evt2irq(0x440),
282  .flags = IORESOURCE_IRQ,
283  },
284 };
285 
286 static struct platform_device tmu2_device = {
287  .name = "sh_tmu",
288  .id = 2,
289  .dev = {
290  .platform_data = &tmu2_platform_data,
291  },
292  .resource = tmu2_resources,
293  .num_resources = ARRAY_SIZE(tmu2_resources),
294 };
295 
296 
297 static struct platform_device *sh7760_devices[] __initdata = {
298  &scif0_device,
299  &scif1_device,
300  &scif2_device,
301  &scif3_device,
302  &tmu0_device,
303  &tmu1_device,
304  &tmu2_device,
305 };
306 
307 static int __init sh7760_devices_setup(void)
308 {
309  return platform_add_devices(sh7760_devices,
310  ARRAY_SIZE(sh7760_devices));
311 }
312 arch_initcall(sh7760_devices_setup);
313 
314 static struct platform_device *sh7760_early_devices[] __initdata = {
315  &scif0_device,
316  &scif1_device,
317  &scif2_device,
318  &scif3_device,
319  &tmu0_device,
320  &tmu1_device,
321  &tmu2_device,
322 };
323 
324 void __init plat_early_device_setup(void)
325 {
326  early_platform_add_devices(sh7760_early_devices,
327  ARRAY_SIZE(sh7760_early_devices));
328 }
329 
330 #define INTC_ICR 0xffd00000UL
331 #define INTC_ICR_IRLM (1 << 7)
332 
333 void __init plat_irq_setup_pins(int mode)
334 {
335  switch (mode) {
336  case IRQ_MODE_IRQ:
337  __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
338  register_intc_controller(&intc_desc_irq);
339  break;
340  default:
341  BUG();
342  }
343 }
344 
345 void __init plat_irq_setup(void)
346 {
347  register_intc_controller(&intc_desc);
348 }
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