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setup-shx3.c
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1 /*
2  * SH-X3 Prototype Setup
3  *
4  * Copyright (C) 2007 - 2010 Paul Mundt
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License. See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/io.h>
15 #include <linux/gpio.h>
16 #include <linux/sh_timer.h>
17 #include <linux/sh_intc.h>
18 #include <cpu/shx3.h>
19 #include <asm/mmzone.h>
20 
21 /*
22  * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
23  * INTEVT values overlap with the FPU EXPEVT ones, requiring special
24  * demuxing in the exception dispatch path.
25  *
26  * As this overlap is something that never should have made it in to
27  * silicon in the first place, we just refuse to deal with the port at
28  * all rather than adding infrastructure to hack around it.
29  */
30 static struct plat_sci_port scif0_platform_data = {
31  .mapbase = 0xffc30000,
32  .flags = UPF_BOOT_AUTOCONF,
33  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
34  .scbrr_algo_id = SCBRR_ALGO_2,
35  .type = PORT_SCIF,
36  .irqs = { evt2irq(0x700),
37  evt2irq(0x720),
38  evt2irq(0x760),
39  evt2irq(0x740) },
40 };
41 
42 static struct platform_device scif0_device = {
43  .name = "sh-sci",
44  .id = 0,
45  .dev = {
46  .platform_data = &scif0_platform_data,
47  },
48 };
49 
50 static struct plat_sci_port scif1_platform_data = {
51  .mapbase = 0xffc40000,
52  .flags = UPF_BOOT_AUTOCONF,
53  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
54  .scbrr_algo_id = SCBRR_ALGO_2,
55  .type = PORT_SCIF,
56  .irqs = { evt2irq(0x780),
57  evt2irq(0x7a0),
58  evt2irq(0x7e0),
59  evt2irq(0x7c0) },
60 };
61 
62 static struct platform_device scif1_device = {
63  .name = "sh-sci",
64  .id = 1,
65  .dev = {
66  .platform_data = &scif1_platform_data,
67  },
68 };
69 
70 static struct plat_sci_port scif2_platform_data = {
71  .mapbase = 0xffc60000,
72  .flags = UPF_BOOT_AUTOCONF,
73  .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
74  .scbrr_algo_id = SCBRR_ALGO_2,
75  .type = PORT_SCIF,
76  .irqs = { evt2irq(0x880),
77  evt2irq(0x8a0),
78  evt2irq(0x8e0),
79  evt2irq(0x8c0) },
80 };
81 
82 static struct platform_device scif2_device = {
83  .name = "sh-sci",
84  .id = 2,
85  .dev = {
86  .platform_data = &scif2_platform_data,
87  },
88 };
89 
90 static struct sh_timer_config tmu0_platform_data = {
91  .channel_offset = 0x04,
92  .timer_bit = 0,
93  .clockevent_rating = 200,
94 };
95 
96 static struct resource tmu0_resources[] = {
97  [0] = {
98  .start = 0xffc10008,
99  .end = 0xffc10013,
100  .flags = IORESOURCE_MEM,
101  },
102  [1] = {
103  .start = evt2irq(0x400),
104  .flags = IORESOURCE_IRQ,
105  },
106 };
107 
108 static struct platform_device tmu0_device = {
109  .name = "sh_tmu",
110  .id = 0,
111  .dev = {
112  .platform_data = &tmu0_platform_data,
113  },
114  .resource = tmu0_resources,
115  .num_resources = ARRAY_SIZE(tmu0_resources),
116 };
117 
118 static struct sh_timer_config tmu1_platform_data = {
119  .channel_offset = 0x10,
120  .timer_bit = 1,
121  .clocksource_rating = 200,
122 };
123 
124 static struct resource tmu1_resources[] = {
125  [0] = {
126  .start = 0xffc10014,
127  .end = 0xffc1001f,
128  .flags = IORESOURCE_MEM,
129  },
130  [1] = {
131  .start = evt2irq(0x420),
132  .flags = IORESOURCE_IRQ,
133  },
134 };
135 
136 static struct platform_device tmu1_device = {
137  .name = "sh_tmu",
138  .id = 1,
139  .dev = {
140  .platform_data = &tmu1_platform_data,
141  },
142  .resource = tmu1_resources,
143  .num_resources = ARRAY_SIZE(tmu1_resources),
144 };
145 
146 static struct sh_timer_config tmu2_platform_data = {
147  .channel_offset = 0x1c,
148  .timer_bit = 2,
149 };
150 
151 static struct resource tmu2_resources[] = {
152  [0] = {
153  .start = 0xffc10020,
154  .end = 0xffc1002f,
155  .flags = IORESOURCE_MEM,
156  },
157  [1] = {
158  .start = evt2irq(0x440),
159  .flags = IORESOURCE_IRQ,
160  },
161 };
162 
163 static struct platform_device tmu2_device = {
164  .name = "sh_tmu",
165  .id = 2,
166  .dev = {
167  .platform_data = &tmu2_platform_data,
168  },
169  .resource = tmu2_resources,
170  .num_resources = ARRAY_SIZE(tmu2_resources),
171 };
172 
173 static struct sh_timer_config tmu3_platform_data = {
174  .channel_offset = 0x04,
175  .timer_bit = 0,
176 };
177 
178 static struct resource tmu3_resources[] = {
179  [0] = {
180  .start = 0xffc20008,
181  .end = 0xffc20013,
182  .flags = IORESOURCE_MEM,
183  },
184  [1] = {
185  .start = evt2irq(0x460),
186  .flags = IORESOURCE_IRQ,
187  },
188 };
189 
190 static struct platform_device tmu3_device = {
191  .name = "sh_tmu",
192  .id = 3,
193  .dev = {
194  .platform_data = &tmu3_platform_data,
195  },
196  .resource = tmu3_resources,
197  .num_resources = ARRAY_SIZE(tmu3_resources),
198 };
199 
200 static struct sh_timer_config tmu4_platform_data = {
201  .channel_offset = 0x10,
202  .timer_bit = 1,
203 };
204 
205 static struct resource tmu4_resources[] = {
206  [0] = {
207  .start = 0xffc20014,
208  .end = 0xffc2001f,
209  .flags = IORESOURCE_MEM,
210  },
211  [1] = {
212  .start = evt2irq(0x480),
213  .flags = IORESOURCE_IRQ,
214  },
215 };
216 
217 static struct platform_device tmu4_device = {
218  .name = "sh_tmu",
219  .id = 4,
220  .dev = {
221  .platform_data = &tmu4_platform_data,
222  },
223  .resource = tmu4_resources,
224  .num_resources = ARRAY_SIZE(tmu4_resources),
225 };
226 
227 static struct sh_timer_config tmu5_platform_data = {
228  .channel_offset = 0x1c,
229  .timer_bit = 2,
230 };
231 
232 static struct resource tmu5_resources[] = {
233  [0] = {
234  .start = 0xffc20020,
235  .end = 0xffc2002b,
236  .flags = IORESOURCE_MEM,
237  },
238  [1] = {
239  .start = evt2irq(0x4a0),
240  .flags = IORESOURCE_IRQ,
241  },
242 };
243 
244 static struct platform_device tmu5_device = {
245  .name = "sh_tmu",
246  .id = 5,
247  .dev = {
248  .platform_data = &tmu5_platform_data,
249  },
250  .resource = tmu5_resources,
251  .num_resources = ARRAY_SIZE(tmu5_resources),
252 };
253 
254 static struct platform_device *shx3_early_devices[] __initdata = {
255  &scif0_device,
256  &scif1_device,
257  &scif2_device,
258  &tmu0_device,
259  &tmu1_device,
260  &tmu2_device,
261  &tmu3_device,
262  &tmu4_device,
263  &tmu5_device,
264 };
265 
266 static int __init shx3_devices_setup(void)
267 {
268  return platform_add_devices(shx3_early_devices,
269  ARRAY_SIZE(shx3_early_devices));
270 }
271 arch_initcall(shx3_devices_setup);
272 
274 {
275  early_platform_add_devices(shx3_early_devices,
276  ARRAY_SIZE(shx3_early_devices));
277 }
278 
279 enum {
280  UNUSED = 0,
281 
282  /* interrupt sources */
298  DU,
308 
309  /* interrupt groups */
312 };
313 
314 static struct intc_vect vectors[] __initdata = {
315  INTC_VECT(HUDII, 0x3e0),
316  INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
317  INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
318  INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
319  INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
320  INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
321  INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
322  INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
323  INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
324  INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
325  INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
326  INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
327  INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
328  INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
329  INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
330  INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
331  INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
332  INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
333  INTC_VECT(DMAC0_DMAE, 0x9c0),
334  INTC_VECT(DU, 0x9e0),
335  INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
336  INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
338  INTC_VECT(DMAC1_DMAE, 0xac0),
339  INTC_VECT(IIC, 0xae0),
340  INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
341  INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
342  INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20),
343  INTC_VECT(DTU0, 0xc40),
344  INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80),
345  INTC_VECT(DTU1, 0xca0),
346  INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0),
347  INTC_VECT(DTU2, 0xd00),
348  INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40),
349  INTC_VECT(DTU3, 0xd60),
350  INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
351  INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
352  INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
353  INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
354  INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
355  INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
356  INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
357  INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
358 };
359 
360 static struct intc_group groups[] __initdata = {
373 };
374 
375 #define INT2DISTCR0 0xfe4108a0
376 #define INT2DISTCR1 0xfe4108a4
377 #define INT2DISTCR2 0xfe4108a8
378 
379 static struct intc_mask_reg mask_registers[] __initdata = {
380  { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
381  { IRQ0, IRQ1, IRQ2, IRQ3 } },
382  { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
383  { IRL } },
384  { 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
385  { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
386  DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
387  0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
388  0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
390  { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
391  { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
398  { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
399  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
405 };
406 
407 static struct intc_prio_reg prio_registers[] __initdata = {
408  { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
409 
410  { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
411  TMU3, TMU2, TMU1, TMU0 } },
412  { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
413  SCIF3, SCIF2,
414  SCIF1, SCIF0 } },
415  { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
416  PCII56789, PCII4,
417  PCII3, PCII2,
418  PCII1, PCII0 } },
419  { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
420  VIN1, VIN0, IIC, DU} },
421  { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
422  GPIO2, GPIO1, GPIO0, IRM } },
423  { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
425  INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 4) },
426 };
427 
428 static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups,
429  mask_registers, prio_registers, NULL);
430 
431 /* Support for external interrupt pins in IRQ mode */
432 static struct intc_vect vectors_irq[] __initdata = {
433  INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
434  INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
435 };
436 
437 static struct intc_sense_reg sense_registers[] __initdata = {
438  { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
439 };
440 
441 static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
442  mask_registers, prio_registers, sense_registers);
443 
444 /* External interrupt pins in IRL mode */
445 static struct intc_vect vectors_irl[] __initdata = {
446  INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
447  INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
448  INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
449  INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
450  INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
451  INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
452  INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
453  INTC_VECT(IRL_HHHL, 0x3c0),
454 };
455 
456 static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
457  mask_registers, prio_registers, NULL);
458 
460 {
461  int ret = 0;
462 
463  switch (mode) {
464  case IRQ_MODE_IRQ:
465  ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name);
466  ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name);
467  ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name);
468  ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name);
469 
470  if (unlikely(ret)) {
471  pr_err("Failed to set IRQ mode\n");
472  return;
473  }
474 
475  register_intc_controller(&intc_desc_irq);
476  break;
477  case IRQ_MODE_IRL3210:
478  ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name);
479  ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name);
480  ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name);
481  ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name);
482 
483  if (unlikely(ret)) {
484  pr_err("Failed to set IRL mode\n");
485  return;
486  }
487 
488  register_intc_controller(&intc_desc_irl);
489  break;
490  default:
491  BUG();
492  }
493 }
494 
496 {
498 }
499 
501 {
502  unsigned int nid = 1;
503 
504  /* Register CPU#0 URAM space as Node 1 */
505  setup_bootmem_node(nid++, 0x145f0000, 0x14610000); /* CPU0 */
506 
507 #if 0
508  /* XXX: Not yet.. */
509  setup_bootmem_node(nid++, 0x14df0000, 0x14e10000); /* CPU1 */
510  setup_bootmem_node(nid++, 0x155f0000, 0x15610000); /* CPU2 */
511  setup_bootmem_node(nid++, 0x15df0000, 0x15e10000); /* CPU3 */
512 #endif
513 
514  setup_bootmem_node(nid++, 0x16000000, 0x16020000); /* CSM */
515 }