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32 #define SH_FSI_INVERSION_MASK 0x0000000F
33 #define SH_FSI_LRM_INV (1 << 0)
34 #define SH_FSI_BRM_INV (1 << 1)
35 #define SH_FSI_LRS_INV (1 << 2)
36 #define SH_FSI_BRS_INV (1 << 3)
39 #define SH_FSI_FMT_MASK 0x000000F0
40 #define SH_FSI_FMT_DAI (0 << 4)
41 #define SH_FSI_FMT_SPDIF (1 << 4)
44 #define SH_FSI_OPTION_MASK 0x00000F00
45 #define SH_FSI_ENABLE_STREAM_MODE (1 << 8)
64 #define SH_FSI_ACKMD_MASK (0xF << 0)
65 #define SH_FSI_ACKMD_512 (1 << 0)
66 #define SH_FSI_ACKMD_256 (2 << 0)
67 #define SH_FSI_ACKMD_128 (3 << 0)
68 #define SH_FSI_ACKMD_64 (4 << 0)
69 #define SH_FSI_ACKMD_32 (5 << 0)
71 #define SH_FSI_BPFMD_MASK (0xF << 4)
72 #define SH_FSI_BPFMD_512 (1 << 4)
73 #define SH_FSI_BPFMD_256 (2 << 4)
74 #define SH_FSI_BPFMD_128 (3 << 4)
75 #define SH_FSI_BPFMD_64 (4 << 4)
76 #define SH_FSI_BPFMD_32 (5 << 4)
77 #define SH_FSI_BPFMD_16 (6 << 4)