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smsc-ircc2.h
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1 /*********************************************************************
2  *
3  * Description: Definitions for the SMC IrCC chipset
4  * Status: Experimental.
5  * Author: Daniele Peri ([email protected])
6  *
7  * Copyright (c) 2002 Daniele Peri
8  * All Rights Reserved.
9  *
10  * Based on smc-ircc.h:
11  *
12  * Copyright (c) 1999-2000, Dag Brattli <[email protected]>
13  * Copyright (c) 1998-1999, Thomas Davis ([email protected]>
14  * All Rights Reserved
15  *
16  *
17  * This program is free software; you can redistribute it and/or
18  * modify it under the terms of the GNU General Public License as
19  * published by the Free Software Foundation; either version 2 of
20  * the License, or (at your option) any later version.
21  *
22  * This program is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25  * GNU General Public License for more details.
26  *
27  * You should have received a copy of the GNU General Public License
28  * along with this program; if not, write to the Free Software
29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30  * MA 02111-1307 USA
31  *
32  ********************************************************************/
33 
34 #ifndef SMSC_IRCC2_H
35 #define SMSC_IRCC2_H
36 
37 /* DMA modes needed */
38 #define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
39 #define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
40 
41 /* Master Control Register */
42 #define IRCC_MASTER 0x07
43 #define IRCC_MASTER_POWERDOWN 0x80
44 #define IRCC_MASTER_RESET 0x40
45 #define IRCC_MASTER_INT_EN 0x20
46 #define IRCC_MASTER_ERROR_RESET 0x10
47 
48 /* Register block 0 */
49 
50 /* Interrupt Identification */
51 #define IRCC_IIR 0x01
52 #define IRCC_IIR_ACTIVE_FRAME 0x80
53 #define IRCC_IIR_EOM 0x40
54 #define IRCC_IIR_RAW_MODE 0x20
55 #define IRCC_IIR_FIFO 0x10
56 
57 /* Interrupt Enable */
58 #define IRCC_IER 0x02
59 #define IRCC_IER_ACTIVE_FRAME 0x80
60 #define IRCC_IER_EOM 0x40
61 #define IRCC_IER_RAW_MODE 0x20
62 #define IRCC_IER_FIFO 0x10
63 
64 /* Line Status Register */
65 #define IRCC_LSR 0x03
66 #define IRCC_LSR_UNDERRUN 0x80
67 #define IRCC_LSR_OVERRUN 0x40
68 #define IRCC_LSR_FRAME_ERROR 0x20
69 #define IRCC_LSR_SIZE_ERROR 0x10
70 #define IRCC_LSR_CRC_ERROR 0x80
71 #define IRCC_LSR_FRAME_ABORT 0x40
72 
73 /* Line Status Address Register */
74 #define IRCC_LSAR 0x03
75 #define IRCC_LSAR_ADDRESS_MASK 0x07
76 
77 /* Line Control Register A */
78 #define IRCC_LCR_A 0x04
79 #define IRCC_LCR_A_FIFO_RESET 0x80
80 #define IRCC_LCR_A_FAST 0x40
81 #define IRCC_LCR_A_GP_DATA 0x20
82 #define IRCC_LCR_A_RAW_TX 0x10
83 #define IRCC_LCR_A_RAW_RX 0x08
84 #define IRCC_LCR_A_ABORT 0x04
85 #define IRCC_LCR_A_DATA_DONE 0x02
86 
87 /* Line Control Register B */
88 #define IRCC_LCR_B 0x05
89 #define IRCC_LCR_B_SCE_DISABLED 0x00
90 #define IRCC_LCR_B_SCE_TRANSMIT 0x40
91 #define IRCC_LCR_B_SCE_RECEIVE 0x80
92 #define IRCC_LCR_B_SCE_UNDEFINED 0xc0
93 #define IRCC_LCR_B_SIP_ENABLE 0x20
94 #define IRCC_LCR_B_BRICK_WALL 0x10
95 
96 /* Bus Status Register */
97 #define IRCC_BSR 0x06
98 #define IRCC_BSR_NOT_EMPTY 0x80
99 #define IRCC_BSR_FIFO_FULL 0x40
100 #define IRCC_BSR_TIMEOUT 0x20
101 
102 /* Register block 1 */
103 
104 #define IRCC_FIFO_THRESHOLD 0x02
105 
106 #define IRCC_SCE_CFGA 0x00
107 #define IRCC_CFGA_AUX_IR 0x80
108 #define IRCC_CFGA_HALF_DUPLEX 0x04
109 #define IRCC_CFGA_TX_POLARITY 0x02
110 #define IRCC_CFGA_RX_POLARITY 0x01
111 
112 #define IRCC_CFGA_COM 0x00
113 #define IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK 0x87
114 #define IRCC_CFGA_IRDA_SIR_A 0x08
115 #define IRCC_CFGA_ASK_SIR 0x10
116 #define IRCC_CFGA_IRDA_SIR_B 0x18
117 #define IRCC_CFGA_IRDA_HDLC 0x20
118 #define IRCC_CFGA_IRDA_4PPM 0x28
119 #define IRCC_CFGA_CONSUMER 0x30
120 #define IRCC_CFGA_RAW_IR 0x38
121 #define IRCC_CFGA_OTHER 0x40
122 
123 #define IRCC_IR_HDLC 0x04
124 #define IRCC_IR_4PPM 0x01
125 #define IRCC_IR_CONSUMER 0x02
126 
127 #define IRCC_SCE_CFGB 0x01
128 #define IRCC_CFGB_LOOPBACK 0x20
129 #define IRCC_CFGB_LPBCK_TX_CRC 0x10
130 #define IRCC_CFGB_NOWAIT 0x08
131 #define IRCC_CFGB_STRING_MOVE 0x04
132 #define IRCC_CFGB_DMA_BURST 0x02
133 #define IRCC_CFGB_DMA_ENABLE 0x01
134 
135 #define IRCC_CFGB_MUX_COM 0x00
136 #define IRCC_CFGB_MUX_IR 0x40
137 #define IRCC_CFGB_MUX_AUX 0x80
138 #define IRCC_CFGB_MUX_INACTIVE 0xc0
139 
140 /* Register block 3 - Identification Registers! */
141 #define IRCC_ID_HIGH 0x00 /* 0x10 */
142 #define IRCC_ID_LOW 0x01 /* 0xB8 */
143 #define IRCC_CHIP_ID 0x02 /* 0xF1 */
144 #define IRCC_VERSION 0x03 /* 0x01 */
145 #define IRCC_INTERFACE 0x04 /* low 4 = DMA, high 4 = IRQ */
146 #define IRCC_INTERFACE_DMA_MASK 0x0F /* low 4 = DMA, high 4 = IRQ */
147 #define IRCC_INTERFACE_IRQ_MASK 0xF0 /* low 4 = DMA, high 4 = IRQ */
148 
149 /* Register block 4 - IrDA */
150 #define IRCC_CONTROL 0x00
151 #define IRCC_BOF_COUNT_LO 0x01 /* Low byte */
152 #define IRCC_BOF_COUNT_HI 0x00 /* High nibble (bit 0-3) */
153 #define IRCC_BRICKWALL_CNT_LO 0x02 /* Low byte */
154 #define IRCC_BRICKWALL_CNT_HI 0x03 /* High nibble (bit 4-7) */
155 #define IRCC_TX_SIZE_LO 0x04 /* Low byte */
156 #define IRCC_TX_SIZE_HI 0x03 /* High nibble (bit 0-3) */
157 #define IRCC_RX_SIZE_HI 0x05 /* High nibble (bit 0-3) */
158 #define IRCC_RX_SIZE_LO 0x06 /* Low byte */
159 
160 #define IRCC_1152 0x80
161 #define IRCC_CRC 0x40
162 
163 /* Register block 5 - IrDA */
164 #define IRCC_ATC 0x00
165 #define IRCC_ATC_nPROGREADY 0x80
166 #define IRCC_ATC_SPEED 0x40
167 #define IRCC_ATC_ENABLE 0x20
168 #define IRCC_ATC_MASK 0xE0
169 
170 
171 #define IRCC_IRHALFDUPLEX_TIMEOUT 0x01
172 
173 #define IRCC_SCE_TX_DELAY_TIMER 0x02
174 
175 /*
176  * Other definitions
177  */
178 
179 #define SMSC_IRCC2_MAX_SIR_SPEED 115200
180 #define SMSC_IRCC2_FIR_CHIP_IO_EXTENT 8
181 #define SMSC_IRCC2_SIR_CHIP_IO_EXTENT 8
182 #define SMSC_IRCC2_FIFO_SIZE 16
183 #define SMSC_IRCC2_FIFO_THRESHOLD 64
184 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
185 #define SMSC_IRCC2_RX_BUFF_TRUESIZE 14384
186 #define SMSC_IRCC2_TX_BUFF_TRUESIZE 14384
187 #define SMSC_IRCC2_MIN_TURN_TIME 0x07
188 #define SMSC_IRCC2_WINDOW_SIZE 0x07
189 /* Maximum wait for hw transmitter to finish */
190 #define SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US 1000 /* 1 ms */
191 /* Maximum wait for ATC transceiver programming to finish */
192 #define SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES 1
193 #endif /* SMSC_IRCC2_H */