|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
Go to the source code of this file.
Macros | |
| #define | TX_CMD_A_DATA_OFFSET_ (0x001F0000) |
| #define | TX_CMD_A_FIRST_SEG_ (0x00002000) |
| #define | TX_CMD_A_LAST_SEG_ (0x00001000) |
| #define | TX_CMD_A_BUF_SIZE_ (0x000007FF) |
| #define | TX_CMD_B_CSUM_ENABLE (0x00004000) |
| #define | TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000) |
| #define | TX_CMD_B_DISABLE_PADDING_ (0x00001000) |
| #define | TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF) |
| #define | RX_STS_FF_ (0x40000000) /* Filter Fail */ |
| #define | RX_STS_FL_ (0x3FFF0000) /* Frame Length */ |
| #define | RX_STS_ES_ (0x00008000) /* Error Summary */ |
| #define | RX_STS_BF_ (0x00002000) /* Broadcast Frame */ |
| #define | RX_STS_LE_ (0x00001000) /* Length Error */ |
| #define | RX_STS_RF_ (0x00000800) /* Runt Frame */ |
| #define | RX_STS_MF_ (0x00000400) /* Multicast Frame */ |
| #define | RX_STS_TL_ (0x00000080) /* Frame too long */ |
| #define | RX_STS_CS_ (0x00000040) /* Collision Seen */ |
| #define | RX_STS_FT_ (0x00000020) /* Frame Type */ |
| #define | RX_STS_RW_ (0x00000010) /* Receive Watchdog */ |
| #define | RX_STS_ME_ (0x00000008) /* Mii Error */ |
| #define | RX_STS_DB_ (0x00000004) /* Dribbling */ |
| #define | RX_STS_CRC_ (0x00000002) /* CRC Error */ |
| #define | ID_REV (0x00) |
| #define | ID_REV_CHIP_ID_MASK_ (0xFFFF0000) |
| #define | ID_REV_CHIP_REV_MASK_ (0x0000FFFF) |
| #define | ID_REV_CHIP_ID_9500_ (0x9500) |
| #define | INT_STS (0x08) |
| #define | INT_STS_TX_STOP_ (0x00020000) |
| #define | INT_STS_RX_STOP_ (0x00010000) |
| #define | INT_STS_PHY_INT_ (0x00008000) |
| #define | INT_STS_TXE_ (0x00004000) |
| #define | INT_STS_TDFU_ (0x00002000) |
| #define | INT_STS_TDFO_ (0x00001000) |
| #define | INT_STS_RXDF_ (0x00000800) |
| #define | INT_STS_GPIOS_ (0x000007FF) |
| #define | INT_STS_CLEAR_ALL_ (0xFFFFFFFF) |
| #define | RX_CFG (0x0C) |
| #define | RX_FIFO_FLUSH_ (0x00000001) |
| #define | TX_CFG (0x10) |
| #define | TX_CFG_ON_ (0x00000004) |
| #define | TX_CFG_STOP_ (0x00000002) |
| #define | TX_CFG_FIFO_FLUSH_ (0x00000001) |
| #define | HW_CFG (0x14) |
| #define | HW_CFG_BIR_ (0x00001000) |
| #define | HW_CFG_LEDB_ (0x00000800) |
| #define | HW_CFG_RXDOFF_ (0x00000600) |
| #define | HW_CFG_DRP_ (0x00000040) |
| #define | HW_CFG_MEF_ (0x00000020) |
| #define | HW_CFG_LRST_ (0x00000008) |
| #define | HW_CFG_PSEL_ (0x00000004) |
| #define | HW_CFG_BCE_ (0x00000002) |
| #define | HW_CFG_SRST_ (0x00000001) |
| #define | RX_FIFO_INF (0x18) |
| #define | PM_CTRL (0x20) |
| #define | PM_CTL_RES_CLR_WKP_STS (0x00000200) |
| #define | PM_CTL_DEV_RDY_ (0x00000080) |
| #define | PM_CTL_SUS_MODE_ (0x00000060) |
| #define | PM_CTL_SUS_MODE_0 (0x00000000) |
| #define | PM_CTL_SUS_MODE_1 (0x00000020) |
| #define | PM_CTL_SUS_MODE_2 (0x00000040) |
| #define | PM_CTL_SUS_MODE_3 (0x00000060) |
| #define | PM_CTL_PHY_RST_ (0x00000010) |
| #define | PM_CTL_WOL_EN_ (0x00000008) |
| #define | PM_CTL_ED_EN_ (0x00000004) |
| #define | PM_CTL_WUPS_ (0x00000003) |
| #define | PM_CTL_WUPS_NO_ (0x00000000) |
| #define | PM_CTL_WUPS_ED_ (0x00000001) |
| #define | PM_CTL_WUPS_WOL_ (0x00000002) |
| #define | PM_CTL_WUPS_MULTI_ (0x00000003) |
| #define | LED_GPIO_CFG (0x24) |
| #define | LED_GPIO_CFG_SPD_LED (0x01000000) |
| #define | LED_GPIO_CFG_LNK_LED (0x00100000) |
| #define | LED_GPIO_CFG_FDX_LED (0x00010000) |
| #define | GPIO_CFG (0x28) |
| #define | AFC_CFG (0x2C) |
| #define | AFC_CFG_DEFAULT (0x00F830A1) |
| #define | E2P_CMD (0x30) |
| #define | E2P_CMD_BUSY_ (0x80000000) |
| #define | E2P_CMD_MASK_ (0x70000000) |
| #define | E2P_CMD_READ_ (0x00000000) |
| #define | E2P_CMD_EWDS_ (0x10000000) |
| #define | E2P_CMD_EWEN_ (0x20000000) |
| #define | E2P_CMD_WRITE_ (0x30000000) |
| #define | E2P_CMD_WRAL_ (0x40000000) |
| #define | E2P_CMD_ERASE_ (0x50000000) |
| #define | E2P_CMD_ERAL_ (0x60000000) |
| #define | E2P_CMD_RELOAD_ (0x70000000) |
| #define | E2P_CMD_TIMEOUT_ (0x00000400) |
| #define | E2P_CMD_LOADED_ (0x00000200) |
| #define | E2P_CMD_ADDR_ (0x000001FF) |
| #define | MAX_EEPROM_SIZE (512) |
| #define | E2P_DATA (0x34) |
| #define | E2P_DATA_MASK_ (0x000000FF) |
| #define | BURST_CAP (0x38) |
| #define | GPIO_WAKE (0x64) |
| #define | INT_EP_CTL (0x68) |
| #define | INT_EP_CTL_INTEP_ (0x80000000) |
| #define | INT_EP_CTL_MACRTO_ (0x00080000) |
| #define | INT_EP_CTL_TX_STOP_ (0x00020000) |
| #define | INT_EP_CTL_RX_STOP_ (0x00010000) |
| #define | INT_EP_CTL_PHY_INT_ (0x00008000) |
| #define | INT_EP_CTL_TXE_ (0x00004000) |
| #define | INT_EP_CTL_TDFU_ (0x00002000) |
| #define | INT_EP_CTL_TDFO_ (0x00001000) |
| #define | INT_EP_CTL_RXDF_ (0x00000800) |
| #define | INT_EP_CTL_GPIOS_ (0x000007FF) |
| #define | BULK_IN_DLY (0x6C) |
| #define | MAC_CR (0x100) |
| #define | MAC_CR_RXALL_ (0x80000000) |
| #define | MAC_CR_RCVOWN_ (0x00800000) |
| #define | MAC_CR_LOOPBK_ (0x00200000) |
| #define | MAC_CR_FDPX_ (0x00100000) |
| #define | MAC_CR_MCPAS_ (0x00080000) |
| #define | MAC_CR_PRMS_ (0x00040000) |
| #define | MAC_CR_INVFILT_ (0x00020000) |
| #define | MAC_CR_PASSBAD_ (0x00010000) |
| #define | MAC_CR_HFILT_ (0x00008000) |
| #define | MAC_CR_HPFILT_ (0x00002000) |
| #define | MAC_CR_LCOLL_ (0x00001000) |
| #define | MAC_CR_BCAST_ (0x00000800) |
| #define | MAC_CR_DISRTY_ (0x00000400) |
| #define | MAC_CR_PADSTR_ (0x00000100) |
| #define | MAC_CR_BOLMT_MASK (0x000000C0) |
| #define | MAC_CR_DFCHK_ (0x00000020) |
| #define | MAC_CR_TXEN_ (0x00000008) |
| #define | MAC_CR_RXEN_ (0x00000004) |
| #define | ADDRH (0x104) |
| #define | ADDRL (0x108) |
| #define | HASHH (0x10C) |
| #define | HASHL (0x110) |
| #define | MII_ADDR (0x114) |
| #define | MII_WRITE_ (0x02) |
| #define | MII_BUSY_ (0x01) |
| #define | MII_READ_ (0x00) /* ~of MII Write bit */ |
| #define | MII_DATA (0x118) |
| #define | FLOW (0x11C) |
| #define | FLOW_FCPT_ (0xFFFF0000) |
| #define | FLOW_FCPASS_ (0x00000004) |
| #define | FLOW_FCEN_ (0x00000002) |
| #define | FLOW_FCBSY_ (0x00000001) |
| #define | VLAN1 (0x120) |
| #define | VLAN2 (0x124) |
| #define | WUFF (0x128) |
| #define | WUCSR (0x12C) |
| #define | WUCSR_GUE_ (0x00000200) |
| #define | WUCSR_WUFR_ (0x00000040) |
| #define | WUCSR_MPR_ (0x00000020) |
| #define | WUCSR_WAKE_EN_ (0x00000004) |
| #define | WUCSR_MPEN_ (0x00000002) |
| #define | COE_CR (0x130) |
| #define | Tx_COE_EN_ (0x00010000) |
| #define | Rx_COE_MODE_ (0x00000002) |
| #define | Rx_COE_EN_ (0x00000001) |
| #define | PHY_MODE_CTRL_STS (17) |
| #define | MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000) |
| #define | MODE_CTRL_STS_ENERGYON_ ((u16)0x0002) |
| #define | SPECIAL_CTRL_STS (27) |
| #define | SPECIAL_CTRL_STS_OVRRD_AMDIX_ ((u16)0x8000) |
| #define | SPECIAL_CTRL_STS_AMDIX_ENABLE_ ((u16)0x4000) |
| #define | SPECIAL_CTRL_STS_AMDIX_STATE_ ((u16)0x2000) |
| #define | PHY_INT_SRC (29) |
| #define | PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080) |
| #define | PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040) |
| #define | PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020) |
| #define | PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010) |
| #define | PHY_INT_MASK (30) |
| #define | PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080) |
| #define | PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) |
| #define | PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020) |
| #define | PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) |
| #define | PHY_INT_MASK_DEFAULT_ |
| #define | PHY_SPECIAL (31) |
| #define | PHY_SPECIAL_SPD_ ((u16)0x001C) |
| #define | PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004) |
| #define | PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014) |
| #define | PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008) |
| #define | PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018) |
| #define | USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 |
| #define | USB_VENDOR_REQUEST_READ_REGISTER 0xA1 |
| #define | USB_VENDOR_REQUEST_GET_STATS 0xA2 |
| #define | INT_ENP_TX_STOP_ ((u32)BIT(17)) |
| #define | INT_ENP_RX_STOP_ ((u32)BIT(16)) |
| #define | INT_ENP_PHY_INT_ ((u32)BIT(15)) |
| #define | INT_ENP_TXE_ ((u32)BIT(14)) |
| #define | INT_ENP_TDFU_ ((u32)BIT(13)) |
| #define | INT_ENP_TDFO_ ((u32)BIT(12)) |
| #define | INT_ENP_RXDF_ ((u32)BIT(11)) |
| #define ADDRH (0x104) |
Definition at line 180 of file smsc95xx.h.
| #define ADDRL (0x108) |
Definition at line 182 of file smsc95xx.h.
| #define AFC_CFG (0x2C) |
Definition at line 113 of file smsc95xx.h.
| #define AFC_CFG_DEFAULT (0x00F830A1) |
Definition at line 119 of file smsc95xx.h.
| #define BULK_IN_DLY (0x6C) |
Definition at line 157 of file smsc95xx.h.
| #define BURST_CAP (0x38) |
Definition at line 141 of file smsc95xx.h.
| #define COE_CR (0x130) |
Definition at line 214 of file smsc95xx.h.
| #define E2P_CMD (0x30) |
Definition at line 121 of file smsc95xx.h.
| #define E2P_CMD_ADDR_ (0x000001FF) |
Definition at line 134 of file smsc95xx.h.
| #define E2P_CMD_BUSY_ (0x80000000) |
Definition at line 122 of file smsc95xx.h.
| #define E2P_CMD_ERAL_ (0x60000000) |
Definition at line 130 of file smsc95xx.h.
| #define E2P_CMD_ERASE_ (0x50000000) |
Definition at line 129 of file smsc95xx.h.
| #define E2P_CMD_EWDS_ (0x10000000) |
Definition at line 125 of file smsc95xx.h.
| #define E2P_CMD_EWEN_ (0x20000000) |
Definition at line 126 of file smsc95xx.h.
| #define E2P_CMD_LOADED_ (0x00000200) |
Definition at line 133 of file smsc95xx.h.
| #define E2P_CMD_MASK_ (0x70000000) |
Definition at line 123 of file smsc95xx.h.
| #define E2P_CMD_READ_ (0x00000000) |
Definition at line 124 of file smsc95xx.h.
| #define E2P_CMD_RELOAD_ (0x70000000) |
Definition at line 131 of file smsc95xx.h.
| #define E2P_CMD_TIMEOUT_ (0x00000400) |
Definition at line 132 of file smsc95xx.h.
| #define E2P_CMD_WRAL_ (0x40000000) |
Definition at line 128 of file smsc95xx.h.
| #define E2P_CMD_WRITE_ (0x30000000) |
Definition at line 127 of file smsc95xx.h.
| #define E2P_DATA (0x34) |
Definition at line 138 of file smsc95xx.h.
| #define E2P_DATA_MASK_ (0x000000FF) |
Definition at line 139 of file smsc95xx.h.
| #define FLOW (0x11C) |
Definition at line 195 of file smsc95xx.h.
| #define FLOW_FCBSY_ (0x00000001) |
Definition at line 199 of file smsc95xx.h.
| #define FLOW_FCEN_ (0x00000002) |
Definition at line 198 of file smsc95xx.h.
| #define FLOW_FCPASS_ (0x00000004) |
Definition at line 197 of file smsc95xx.h.
| #define FLOW_FCPT_ (0xFFFF0000) |
Definition at line 196 of file smsc95xx.h.
| #define GPIO_CFG (0x28) |
Definition at line 111 of file smsc95xx.h.
| #define GPIO_WAKE (0x64) |
Definition at line 143 of file smsc95xx.h.
| #define HASHH (0x10C) |
Definition at line 184 of file smsc95xx.h.
| #define HASHL (0x110) |
Definition at line 186 of file smsc95xx.h.
| #define HW_CFG (0x14) |
Definition at line 76 of file smsc95xx.h.
| #define HW_CFG_BCE_ (0x00000002) |
Definition at line 84 of file smsc95xx.h.
| #define HW_CFG_BIR_ (0x00001000) |
Definition at line 77 of file smsc95xx.h.
| #define HW_CFG_DRP_ (0x00000040) |
Definition at line 80 of file smsc95xx.h.
| #define HW_CFG_LEDB_ (0x00000800) |
Definition at line 78 of file smsc95xx.h.
| #define HW_CFG_LRST_ (0x00000008) |
Definition at line 82 of file smsc95xx.h.
| #define HW_CFG_MEF_ (0x00000020) |
Definition at line 81 of file smsc95xx.h.
| #define HW_CFG_PSEL_ (0x00000004) |
Definition at line 83 of file smsc95xx.h.
| #define HW_CFG_RXDOFF_ (0x00000600) |
Definition at line 79 of file smsc95xx.h.
| #define HW_CFG_SRST_ (0x00000001) |
Definition at line 85 of file smsc95xx.h.
| #define ID_REV (0x00) |
Definition at line 52 of file smsc95xx.h.
| #define ID_REV_CHIP_ID_9500_ (0x9500) |
Definition at line 55 of file smsc95xx.h.
| #define ID_REV_CHIP_ID_MASK_ (0xFFFF0000) |
Definition at line 53 of file smsc95xx.h.
| #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) |
Definition at line 54 of file smsc95xx.h.
Definition at line 260 of file smsc95xx.h.
Definition at line 259 of file smsc95xx.h.
Definition at line 264 of file smsc95xx.h.
Definition at line 263 of file smsc95xx.h.
Definition at line 262 of file smsc95xx.h.
Definition at line 258 of file smsc95xx.h.
Definition at line 261 of file smsc95xx.h.
| #define INT_EP_CTL (0x68) |
Definition at line 145 of file smsc95xx.h.
| #define INT_EP_CTL_GPIOS_ (0x000007FF) |
Definition at line 155 of file smsc95xx.h.
| #define INT_EP_CTL_INTEP_ (0x80000000) |
Definition at line 146 of file smsc95xx.h.
| #define INT_EP_CTL_MACRTO_ (0x00080000) |
Definition at line 147 of file smsc95xx.h.
| #define INT_EP_CTL_PHY_INT_ (0x00008000) |
Definition at line 150 of file smsc95xx.h.
| #define INT_EP_CTL_RX_STOP_ (0x00010000) |
Definition at line 149 of file smsc95xx.h.
| #define INT_EP_CTL_RXDF_ (0x00000800) |
Definition at line 154 of file smsc95xx.h.
| #define INT_EP_CTL_TDFO_ (0x00001000) |
Definition at line 153 of file smsc95xx.h.
| #define INT_EP_CTL_TDFU_ (0x00002000) |
Definition at line 152 of file smsc95xx.h.
| #define INT_EP_CTL_TX_STOP_ (0x00020000) |
Definition at line 148 of file smsc95xx.h.
| #define INT_EP_CTL_TXE_ (0x00004000) |
Definition at line 151 of file smsc95xx.h.
| #define INT_STS (0x08) |
Definition at line 57 of file smsc95xx.h.
| #define INT_STS_CLEAR_ALL_ (0xFFFFFFFF) |
Definition at line 66 of file smsc95xx.h.
| #define INT_STS_GPIOS_ (0x000007FF) |
Definition at line 65 of file smsc95xx.h.
| #define INT_STS_PHY_INT_ (0x00008000) |
Definition at line 60 of file smsc95xx.h.
| #define INT_STS_RX_STOP_ (0x00010000) |
Definition at line 59 of file smsc95xx.h.
| #define INT_STS_RXDF_ (0x00000800) |
Definition at line 64 of file smsc95xx.h.
| #define INT_STS_TDFO_ (0x00001000) |
Definition at line 63 of file smsc95xx.h.
| #define INT_STS_TDFU_ (0x00002000) |
Definition at line 62 of file smsc95xx.h.
| #define INT_STS_TX_STOP_ (0x00020000) |
Definition at line 58 of file smsc95xx.h.
| #define INT_STS_TXE_ (0x00004000) |
Definition at line 61 of file smsc95xx.h.
| #define LED_GPIO_CFG (0x24) |
Definition at line 106 of file smsc95xx.h.
| #define LED_GPIO_CFG_FDX_LED (0x00010000) |
Definition at line 109 of file smsc95xx.h.
| #define LED_GPIO_CFG_LNK_LED (0x00100000) |
Definition at line 108 of file smsc95xx.h.
| #define LED_GPIO_CFG_SPD_LED (0x01000000) |
Definition at line 107 of file smsc95xx.h.
| #define MAC_CR (0x100) |
Definition at line 160 of file smsc95xx.h.
| #define MAC_CR_BCAST_ (0x00000800) |
Definition at line 172 of file smsc95xx.h.
| #define MAC_CR_BOLMT_MASK (0x000000C0) |
Definition at line 175 of file smsc95xx.h.
| #define MAC_CR_DFCHK_ (0x00000020) |
Definition at line 176 of file smsc95xx.h.
| #define MAC_CR_DISRTY_ (0x00000400) |
Definition at line 173 of file smsc95xx.h.
| #define MAC_CR_FDPX_ (0x00100000) |
Definition at line 164 of file smsc95xx.h.
| #define MAC_CR_HFILT_ (0x00008000) |
Definition at line 169 of file smsc95xx.h.
| #define MAC_CR_HPFILT_ (0x00002000) |
Definition at line 170 of file smsc95xx.h.
| #define MAC_CR_INVFILT_ (0x00020000) |
Definition at line 167 of file smsc95xx.h.
| #define MAC_CR_LCOLL_ (0x00001000) |
Definition at line 171 of file smsc95xx.h.
| #define MAC_CR_LOOPBK_ (0x00200000) |
Definition at line 163 of file smsc95xx.h.
| #define MAC_CR_MCPAS_ (0x00080000) |
Definition at line 165 of file smsc95xx.h.
| #define MAC_CR_PADSTR_ (0x00000100) |
Definition at line 174 of file smsc95xx.h.
| #define MAC_CR_PASSBAD_ (0x00010000) |
Definition at line 168 of file smsc95xx.h.
| #define MAC_CR_PRMS_ (0x00040000) |
Definition at line 166 of file smsc95xx.h.
| #define MAC_CR_RCVOWN_ (0x00800000) |
Definition at line 162 of file smsc95xx.h.
| #define MAC_CR_RXALL_ (0x80000000) |
Definition at line 161 of file smsc95xx.h.
| #define MAC_CR_RXEN_ (0x00000004) |
Definition at line 178 of file smsc95xx.h.
| #define MAC_CR_TXEN_ (0x00000008) |
Definition at line 177 of file smsc95xx.h.
| #define MAX_EEPROM_SIZE (512) |
Definition at line 136 of file smsc95xx.h.
| #define MII_ADDR (0x114) |
Definition at line 188 of file smsc95xx.h.
| #define MII_BUSY_ (0x01) |
Definition at line 190 of file smsc95xx.h.
| #define MII_DATA (0x118) |
Definition at line 193 of file smsc95xx.h.
| #define MII_READ_ (0x00) /* ~of MII Write bit */ |
Definition at line 191 of file smsc95xx.h.
| #define MII_WRITE_ (0x02) |
Definition at line 189 of file smsc95xx.h.
| #define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000) |
Definition at line 223 of file smsc95xx.h.
| #define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002) |
Definition at line 224 of file smsc95xx.h.
| #define PHY_INT_MASK (30) |
Definition at line 237 of file smsc95xx.h.
| #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) |
Definition at line 239 of file smsc95xx.h.
| #define PHY_INT_MASK_DEFAULT_ |
Definition at line 242 of file smsc95xx.h.
| #define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080) |
Definition at line 238 of file smsc95xx.h.
| #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) |
Definition at line 241 of file smsc95xx.h.
| #define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020) |
Definition at line 240 of file smsc95xx.h.
| #define PHY_INT_SRC (29) |
Definition at line 231 of file smsc95xx.h.
| #define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040) |
Definition at line 233 of file smsc95xx.h.
| #define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080) |
Definition at line 232 of file smsc95xx.h.
| #define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010) |
Definition at line 235 of file smsc95xx.h.
| #define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020) |
Definition at line 234 of file smsc95xx.h.
| #define PHY_MODE_CTRL_STS (17) |
Definition at line 222 of file smsc95xx.h.
| #define PHY_SPECIAL (31) |
Definition at line 245 of file smsc95xx.h.
| #define PHY_SPECIAL_SPD_ ((u16)0x001C) |
Definition at line 246 of file smsc95xx.h.
| #define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018) |
Definition at line 250 of file smsc95xx.h.
| #define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008) |
Definition at line 249 of file smsc95xx.h.
| #define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014) |
Definition at line 248 of file smsc95xx.h.
| #define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004) |
Definition at line 247 of file smsc95xx.h.
| #define PM_CTL_DEV_RDY_ (0x00000080) |
Definition at line 91 of file smsc95xx.h.
| #define PM_CTL_ED_EN_ (0x00000004) |
Definition at line 99 of file smsc95xx.h.
| #define PM_CTL_PHY_RST_ (0x00000010) |
Definition at line 97 of file smsc95xx.h.
| #define PM_CTL_RES_CLR_WKP_STS (0x00000200) |
Definition at line 90 of file smsc95xx.h.
| #define PM_CTL_SUS_MODE_ (0x00000060) |
Definition at line 92 of file smsc95xx.h.
| #define PM_CTL_SUS_MODE_0 (0x00000000) |
Definition at line 93 of file smsc95xx.h.
| #define PM_CTL_SUS_MODE_1 (0x00000020) |
Definition at line 94 of file smsc95xx.h.
| #define PM_CTL_SUS_MODE_2 (0x00000040) |
Definition at line 95 of file smsc95xx.h.
| #define PM_CTL_SUS_MODE_3 (0x00000060) |
Definition at line 96 of file smsc95xx.h.
| #define PM_CTL_WOL_EN_ (0x00000008) |
Definition at line 98 of file smsc95xx.h.
| #define PM_CTL_WUPS_ (0x00000003) |
Definition at line 100 of file smsc95xx.h.
| #define PM_CTL_WUPS_ED_ (0x00000001) |
Definition at line 102 of file smsc95xx.h.
| #define PM_CTL_WUPS_MULTI_ (0x00000003) |
Definition at line 104 of file smsc95xx.h.
| #define PM_CTL_WUPS_NO_ (0x00000000) |
Definition at line 101 of file smsc95xx.h.
| #define PM_CTL_WUPS_WOL_ (0x00000002) |
Definition at line 103 of file smsc95xx.h.
| #define PM_CTRL (0x20) |
Definition at line 89 of file smsc95xx.h.
| #define RX_CFG (0x0C) |
Definition at line 68 of file smsc95xx.h.
| #define Rx_COE_EN_ (0x00000001) |
Definition at line 217 of file smsc95xx.h.
| #define Rx_COE_MODE_ (0x00000002) |
Definition at line 216 of file smsc95xx.h.
| #define RX_FIFO_FLUSH_ (0x00000001) |
Definition at line 69 of file smsc95xx.h.
| #define RX_FIFO_INF (0x18) |
Definition at line 87 of file smsc95xx.h.
| #define RX_STS_BF_ (0x00002000) /* Broadcast Frame */ |
Definition at line 39 of file smsc95xx.h.
| #define RX_STS_CRC_ (0x00000002) /* CRC Error */ |
Definition at line 49 of file smsc95xx.h.
| #define RX_STS_CS_ (0x00000040) /* Collision Seen */ |
Definition at line 44 of file smsc95xx.h.
| #define RX_STS_DB_ (0x00000004) /* Dribbling */ |
Definition at line 48 of file smsc95xx.h.
| #define RX_STS_ES_ (0x00008000) /* Error Summary */ |
Definition at line 38 of file smsc95xx.h.
| #define RX_STS_FF_ (0x40000000) /* Filter Fail */ |
Definition at line 36 of file smsc95xx.h.
| #define RX_STS_FL_ (0x3FFF0000) /* Frame Length */ |
Definition at line 37 of file smsc95xx.h.
| #define RX_STS_FT_ (0x00000020) /* Frame Type */ |
Definition at line 45 of file smsc95xx.h.
| #define RX_STS_LE_ (0x00001000) /* Length Error */ |
Definition at line 40 of file smsc95xx.h.
| #define RX_STS_ME_ (0x00000008) /* Mii Error */ |
Definition at line 47 of file smsc95xx.h.
| #define RX_STS_MF_ (0x00000400) /* Multicast Frame */ |
Definition at line 42 of file smsc95xx.h.
| #define RX_STS_RF_ (0x00000800) /* Runt Frame */ |
Definition at line 41 of file smsc95xx.h.
| #define RX_STS_RW_ (0x00000010) /* Receive Watchdog */ |
Definition at line 46 of file smsc95xx.h.
| #define RX_STS_TL_ (0x00000080) /* Frame too long */ |
Definition at line 43 of file smsc95xx.h.
| #define SPECIAL_CTRL_STS (27) |
Definition at line 226 of file smsc95xx.h.
| #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ ((u16)0x4000) |
Definition at line 228 of file smsc95xx.h.
| #define SPECIAL_CTRL_STS_AMDIX_STATE_ ((u16)0x2000) |
Definition at line 229 of file smsc95xx.h.
| #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ ((u16)0x8000) |
Definition at line 227 of file smsc95xx.h.
| #define TX_CFG (0x10) |
Definition at line 71 of file smsc95xx.h.
| #define TX_CFG_FIFO_FLUSH_ (0x00000001) |
Definition at line 74 of file smsc95xx.h.
| #define TX_CFG_ON_ (0x00000004) |
Definition at line 72 of file smsc95xx.h.
| #define TX_CFG_STOP_ (0x00000002) |
Definition at line 73 of file smsc95xx.h.
| #define TX_CMD_A_BUF_SIZE_ (0x000007FF) |
Definition at line 28 of file smsc95xx.h.
| #define TX_CMD_A_DATA_OFFSET_ (0x001F0000) |
Definition at line 25 of file smsc95xx.h.
| #define TX_CMD_A_FIRST_SEG_ (0x00002000) |
Definition at line 26 of file smsc95xx.h.
| #define TX_CMD_A_LAST_SEG_ (0x00001000) |
Definition at line 27 of file smsc95xx.h.
| #define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000) |
Definition at line 31 of file smsc95xx.h.
| #define TX_CMD_B_CSUM_ENABLE (0x00004000) |
Definition at line 30 of file smsc95xx.h.
| #define TX_CMD_B_DISABLE_PADDING_ (0x00001000) |
Definition at line 32 of file smsc95xx.h.
| #define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF) |
Definition at line 33 of file smsc95xx.h.
| #define Tx_COE_EN_ (0x00010000) |
Definition at line 215 of file smsc95xx.h.
| #define USB_VENDOR_REQUEST_GET_STATS 0xA2 |
Definition at line 255 of file smsc95xx.h.
| #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 |
Definition at line 254 of file smsc95xx.h.
| #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 |
Definition at line 253 of file smsc95xx.h.
| #define VLAN1 (0x120) |
Definition at line 201 of file smsc95xx.h.
| #define VLAN2 (0x124) |
Definition at line 203 of file smsc95xx.h.
| #define WUCSR (0x12C) |
Definition at line 207 of file smsc95xx.h.
| #define WUCSR_GUE_ (0x00000200) |
Definition at line 208 of file smsc95xx.h.
| #define WUCSR_MPEN_ (0x00000002) |
Definition at line 212 of file smsc95xx.h.
| #define WUCSR_MPR_ (0x00000020) |
Definition at line 210 of file smsc95xx.h.
| #define WUCSR_WAKE_EN_ (0x00000004) |
Definition at line 211 of file smsc95xx.h.
| #define WUCSR_WUFR_ (0x00000040) |
Definition at line 209 of file smsc95xx.h.
| #define WUFF (0x128) |
Definition at line 205 of file smsc95xx.h.
1.8.2