cs42l52.h File Reference

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Macros
#define	CS42L52_NAME   "CS42L52"
#define	CS42L52_DEFAULT_CLK   12000000
#define	CS42L52_MIN_CLK   11000000
#define	CS42L52_MAX_CLK   27000000
#define	CS42L52_DEFAULT_FORMAT   SNDRV_PCM_FMTBIT_S16_LE
#define	CS42L52_DEFAULT_MAX_CHANS   2
#define	CS42L52_SYSCLK   1
#define	CS42L52_CHIP_SWICTH   (1 << 17)
#define	CS42L52_ALL_IN_ONE   (1 << 16)
#define	CS42L52_CHIP_ONE   0x00
#define	CS42L52_CHIP_TWO   0x01
#define	CS42L52_CHIP_THR   0x02
#define	CS42L52_CHIP_MASK   0x0f
#define	CS42L52_FIX_BITS_CTL   0x00
#define	CS42L52_CHIP   0x01
#define	CS42L52_CHIP_ID   0xE0
#define	CS42L52_CHIP_ID_MASK   0xF8
#define	CS42L52_CHIP_REV_A0   0x00
#define	CS42L52_CHIP_REV_A1   0x01
#define	CS42L52_CHIP_REV_B0   0x02
#define	CS42L52_CHIP_REV_MASK   0x03
#define	CS42L52_PWRCTL1   0x02
#define	CS42L52_PWRCTL1_PDN_ALL   0x9F
#define	CS42L52_PWRCTL1_PDN_CHRG   0x80
#define	CS42L52_PWRCTL1_PDN_PGAB   0x10
#define	CS42L52_PWRCTL1_PDN_PGAA   0x08
#define	CS42L52_PWRCTL1_PDN_ADCB   0x04
#define	CS42L52_PWRCTL1_PDN_ADCA   0x02
#define	CS42L52_PWRCTL1_PDN_CODEC   0x01
#define	CS42L52_PWRCTL2   0x03
#define	CS42L52_PWRCTL2_OVRDB   (1 << 4)
#define	CS42L52_PWRCTL2_OVRDA   (1 << 3)
#define	CS42L52_PWRCTL2_PDN_MICB   (1 << 2)
#define	CS42L52_PWRCTL2_PDN_MICB_SHIFT   2
#define	CS42L52_PWRCTL2_PDN_MICA   (1 << 1)
#define	CS42L52_PWRCTL2_PDN_MICA_SHIFT   1
#define	CS42L52_PWRCTL2_PDN_MICBIAS   (1 << 0)
#define	CS42L52_PWRCTL2_PDN_MICBIAS_SHIFT   0
#define	CS42L52_PWRCTL3   0x04
#define	CS42L52_PWRCTL3_HPB_PDN_SHIFT   6
#define	CS42L52_PWRCTL3_HPB_ON_LOW   0x00
#define	CS42L52_PWRCTL3_HPB_ON_HIGH   0x01
#define	CS42L52_PWRCTL3_HPB_ALWAYS_ON   0x02
#define	CS42L52_PWRCTL3_HPB_ALWAYS_OFF   0x03
#define	CS42L52_PWRCTL3_HPA_PDN_SHIFT   4
#define	CS42L52_PWRCTL3_HPA_ON_LOW   0x00
#define	CS42L52_PWRCTL3_HPA_ON_HIGH   0x01
#define	CS42L52_PWRCTL3_HPA_ALWAYS_ON   0x02
#define	CS42L52_PWRCTL3_HPA_ALWAYS_OFF   0x03
#define	CS42L52_PWRCTL3_SPKB_PDN_SHIFT   2
#define	CS42L52_PWRCTL3_SPKB_ON_LOW   0x00
#define	CS42L52_PWRCTL3_SPKB_ON_HIGH   0x01
#define	CS42L52_PWRCTL3_SPKB_ALWAYS_ON   0x02
#define	CS42L52_PWRCTL3_PDN_SPKB   (1 << 2)
#define	CS42L52_PWRCTL3_PDN_SPKA   (1 << 0)
#define	CS42L52_PWRCTL3_SPKA_PDN_SHIFT   0
#define	CS42L52_PWRCTL3_SPKA_ON_LOW   0x00
#define	CS42L52_PWRCTL3_SPKA_ON_HIGH   0x01
#define	CS42L52_PWRCTL3_SPKA_ALWAYS_ON   0x02
#define	CS42L52_DEFAULT_OUTPUT_STATE   0x05
#define	CS42L52_PWRCTL3_CONF_MASK   0x03
#define	CS42L52_CLK_CTL   0x05
#define	CLK_AUTODECT_ENABLE   (1 << 7)
#define	CLK_SPEED_SHIFT   5
#define	CLK_DS_MODE   0x00
#define	CLK_SS_MODE   0x01
#define	CLK_HS_MODE   0x02
#define	CLK_QS_MODE   0x03
#define	CLK_32K_SR_SHIFT   4
#define	CLK_32K   0x01
#define	CLK_NO_32K   0x00
#define	CLK_27M_MCLK_SHIFT   3
#define	CLK_27M_MCLK   0x01
#define	CLK_NO_27M   0x00
#define	CLK_RATIO_SHIFT   1
#define	CLK_R_128   0x00
#define	CLK_R_125   0x01
#define	CLK_R_132   0x02
#define	CLK_R_136   0x03
#define	CS42L52_IFACE_CTL1   0x06
#define	CS42L52_IFACE_CTL1_MASTER   (1 << 7)
#define	CS42L52_IFACE_CTL1_SLAVE   (0 << 7)
#define	CS42L52_IFACE_CTL1_INV_SCLK   (1 << 6)
#define	CS42L52_IFACE_CTL1_ADC_FMT_I2S   (1 << 5)
#define	CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J   (0 << 5)
#define	CS42L52_IFACE_CTL1_DSP_MODE_EN   (1 << 4)
#define	CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J   (0 << 2)
#define	CS42L52_IFACE_CTL1_DAC_FMT_I2S   (1 << 2)
#define	CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J   (2 << 2)
#define	CS42L52_IFACE_CTL1_WL_32BIT   (0x00)
#define	CS42L52_IFACE_CTL1_WL_24BIT   (0x01)
#define	CS42L52_IFACE_CTL1_WL_20BIT   (0x02)
#define	CS42L52_IFACE_CTL1_WL_16BIT   (0x03)
#define	CS42L52_IFACE_CTL1_WL_MASK   0xFFFF
#define	CS42L52_IFACE_CTL2   0x07
#define	CS42L52_IFACE_CTL2_SC_MC_EQ   (1 << 6)
#define	CS42L52_IFACE_CTL2_LOOPBACK   (1 << 5)
#define	CS42L52_IFACE_CTL2_S_MODE_OUTPUT_EN   (0 << 4)
#define	CS42L52_IFACE_CTL2_S_MODE_OUTPUT_HIZ   (1 << 4)
#define	CS42L52_IFACE_CTL2_HP_SW_INV   (1 << 3)
#define	CS42L52_IFACE_CTL2_BIAS_LVL   0x07
#define	CS42L52_ADC_PGA_A   0x08
#define	CS42L52_ADC_PGA_B   0x09
#define	CS42L52_ADC_SEL_SHIFT   5
#define	CS42L52_ADC_SEL_AIN1   0x00
#define	CS42L52_ADC_SEL_AIN2   0x01
#define	CS42L52_ADC_SEL_AIN3   0x02
#define	CS42L52_ADC_SEL_AIN4   0x03
#define	CS42L52_ADC_SEL_PGA   0x04
#define	CS42L52_ANALOG_HPF_CTL   0x0A
#define	CS42L52_HPF_CTL_ANLGSFTB   (1 << 3)
#define	CS42L52_HPF_CTL_ANLGSFTA   (1 << 0)
#define	CS42L52_ADC_HPF_FREQ   0x0B
#define	CS42L52_ADC_MISC_CTL   0x0C
#define	CS42L52_ADC_MISC_CTL_SOURCE_DSP   (1 << 6)
#define	CS42L52_PB_CTL1   0x0D
#define	CS42L52_PB_CTL1_HP_GAIN_SHIFT   5
#define	CS42L52_PB_CTL1_HP_GAIN_03959   0x00
#define	CS42L52_PB_CTL1_HP_GAIN_04571   0x01
#define	CS42L52_PB_CTL1_HP_GAIN_05111   0x02
#define	CS42L52_PB_CTL1_HP_GAIN_06047   0x03
#define	CS42L52_PB_CTL1_HP_GAIN_07099   0x04
#define	CS42L52_PB_CTL1_HP_GAIN_08399   0x05
#define	CS42L52_PB_CTL1_HP_GAIN_10000   0x06
#define	CS42L52_PB_CTL1_HP_GAIN_11430   0x07
#define	CS42L52_PB_CTL1_INV_PCMB   (1 << 3)
#define	CS42L52_PB_CTL1_INV_PCMA   (1 << 2)
#define	CS42L52_PB_CTL1_MSTB_MUTE   (1 << 1)
#define	CS42L52_PB_CTL1_MSTA_MUTE   (1 << 0)
#define	CS42L52_PB_CTL1_MUTE_MASK   0xFFFD
#define	CS42L52_PB_CTL1_MUTE   3
#define	CS42L52_PB_CTL1_UNMUTE   0
#define	CS42L52_MISC_CTL   0x0E
#define	CS42L52_MISC_CTL_DEEMPH   (1 << 2)
#define	CS42L52_MISC_CTL_DIGSFT   (1 << 1)
#define	CS42L52_MISC_CTL_DIGZC   (1 << 0)
#define	CS42L52_PB_CTL2   0x0F
#define	CS42L52_PB_CTL2_HPB_MUTE   (1 << 7)
#define	CS42L52_PB_CTL2_HPA_MUTE   (1 << 6)
#define	CS42L52_PB_CTL2_SPKB_MUTE   (1 << 5)
#define	CS42L52_PB_CTL2_SPKA_MUTE   (1 << 4)
#define	CS42L52_PB_CTL2_SPK_SWAP   (1 << 2)
#define	CS42L52_PB_CTL2_SPK_MONO   (1 << 1)
#define	CS42L52_PB_CTL2_SPK_MUTE50   (1 << 0)
#define	CS42L52_MICA_CTL   0x10
#define	CS42L52_MICB_CTL   0x11
#define	CS42L52_MIC_CTL_MIC_SEL_MASK   0xBF
#define	CS42L52_MIC_CTL_MIC_SEL_SHIFT   6
#define	CS42L52_MIC_CTL_TYPE_MASK   0xDF
#define	CS42L52_MIC_CTL_TYPE_SHIFT   5
#define	CS42L52_PGAA_CTL   0x12
#define	CS42L52_PGAB_CTL   0x13
#define	CS42L52_PGAX_CTL_VOL_12DB   24
#define	CS42L52_PGAX_CTL_VOL_6DB   12 /*step size 0.5db*/
#define	CS42L52_PASSTHRUA_VOL   0x14
#define	CS42L52_PASSTHRUB_VOL   0x15
#define	CS42L52_ADCA_VOL   0x16
#define	CS42L52_ADCB_VOL   0x17
#define	CS42L52_ADCX_VOL_24DB   24 /*step size 1db*/
#define	CS42L52_ADCX_VOL_12DB   12
#define	CS42L52_ADCX_VOL_6DB   6
#define	CS42L52_ADCA_MIXER_VOL   0x18
#define	CS42L52_ADCB_MIXER_VOL   0x19
#define	CS42L52_ADC_MIXER_VOL_12DB   0x18
#define	CS42L52_PCMA_MIXER_VOL   0x1A
#define	CS42L52_PCMB_MIXER_VOL   0x1B
#define	CS42L52_BEEP_FREQ   0x1C
#define	CS42L52_BEEP_VOL   0x1D
#define	CS42L52_BEEP_TONE_CTL   0x1E
#define	CS42L52_BEEP_RATE_SHIFT   4
#define	CS42L52_BEEP_RATE_MASK   0x0F
#define	CS42L52_TONE_CTL   0x1F
#define	CS42L52_BEEP_EN_MASK   0x3F
#define	CS42L52_MASTERA_VOL   0x20
#define	CS42L52_MASTERB_VOL   0x21
#define	CS42L52_HPA_VOL   0x22
#define	CS42L52_HPB_VOL   0x23
#define	CS42L52_DEFAULT_HP_VOL   0xF0
#define	CS42L52_SPKA_VOL   0x24
#define	CS42L52_SPKB_VOL   0x25
#define	CS42L52_DEFAULT_SPK_VOL   0xF0
#define	CS42L52_ADC_PCM_MIXER   0x26
#define	CS42L52_LIMITER_CTL1   0x27
#define	CS42L52_LIMITER_CTL2   0x28
#define	CS42L52_LIMITER_AT_RATE   0x29
#define	CS42L52_ALC_CTL   0x2A
#define	CS42L52_ALC_CTL_ALCB_ENABLE_SHIFT   7
#define	CS42L52_ALC_CTL_ALCA_ENABLE_SHIFT   6
#define	CS42L52_ALC_CTL_FASTEST_ATTACK   0
#define	CS42L52_ALC_RATE   0x2B
#define	CS42L52_ALC_SLOWEST_RELEASE   0x3F
#define	CS42L52_ALC_THRESHOLD   0x2C
#define	CS42L52_ALC_MAX_RATE_SHIFT   5
#define	CS42L52_ALC_MIN_RATE_SHIFT   2
#define	CS42L52_ALC_RATE_0DB   0
#define	CS42L52_ALC_RATE_3DB   1
#define	CS42L52_ALC_RATE_6DB   2
#define	CS42L52_NOISE_GATE_CTL   0x2D
#define	CS42L52_NG_ENABLE_SHIFT   6
#define	CS42L52_NG_THRESHOLD_SHIFT   2
#define	CS42L52_NG_MIN_70DB   2
#define	CS42L52_NG_DELAY_SHIFT   0
#define	CS42L52_NG_DELAY_100MS   1
#define	CS42L52_CLK_STATUS   0x2E
#define	CS42L52_BATT_COMPEN   0x2F
#define	CS42L52_BATT_LEVEL   0x30
#define	CS42L52_SPK_STATUS   0x31
#define	CS42L52_SPK_STATUS_PIN_SHIFT   3
#define	CS42L52_SPK_STATUS_PIN_HIGH   1
#define	CS42L52_TEM_CTL   0x32
#define	CS42L52_TEM_CTL_SET   0x80
#define	CS42L52_THE_FOLDBACK   0x33
#define	CS42L52_CHARGE_PUMP   0x34
#define	CS42L52_CHARGE_PUMP_MASK   0xF0
#define	CS42L52_CHARGE_PUMP_SHIFT   4
#define	CS42L52_FIX_BITS1   0x3E
#define	CS42L52_FIX_BITS2   0x47
#define	CS42L52_MAX_REGISTER   0x34

Macro Definition Documentation

#define CLK_27M_MCLK   0x01

Definition at line 97 of file cs42l52.h.

#define CLK_27M_MCLK_SHIFT   3

Definition at line 96 of file cs42l52.h.

#define CLK_32K   0x01

Definition at line 94 of file cs42l52.h.

#define CLK_32K_SR_SHIFT   4

Definition at line 93 of file cs42l52.h.

#define CLK_AUTODECT_ENABLE   (1 << 7)

Definition at line 87 of file cs42l52.h.

#define CLK_DS_MODE   0x00

Definition at line 89 of file cs42l52.h.

#define CLK_HS_MODE   0x02

Definition at line 91 of file cs42l52.h.

#define CLK_NO_27M   0x00

Definition at line 98 of file cs42l52.h.

#define CLK_NO_32K   0x00

Definition at line 95 of file cs42l52.h.

#define CLK_QS_MODE   0x03

Definition at line 92 of file cs42l52.h.

#define CLK_R_125   0x01

Definition at line 101 of file cs42l52.h.

#define CLK_R_128   0x00

Definition at line 100 of file cs42l52.h.

#define CLK_R_132   0x02

Definition at line 102 of file cs42l52.h.

#define CLK_R_136   0x03

Definition at line 103 of file cs42l52.h.

#define CLK_RATIO_SHIFT   1

Definition at line 99 of file cs42l52.h.

#define CLK_SPEED_SHIFT   5

Definition at line 88 of file cs42l52.h.

#define CLK_SS_MODE   0x01

Definition at line 90 of file cs42l52.h.

#define CS42L52_ADC_HPF_FREQ   0x0B

Definition at line 142 of file cs42l52.h.

#define CS42L52_ADC_MISC_CTL   0x0C

Definition at line 143 of file cs42l52.h.

#define CS42L52_ADC_MISC_CTL_SOURCE_DSP   (1 << 6)

Definition at line 144 of file cs42l52.h.

#define CS42L52_ADC_MIXER_VOL_12DB   0x18

Definition at line 202 of file cs42l52.h.

#define CS42L52_ADC_PCM_MIXER   0x26

Definition at line 227 of file cs42l52.h.

#define CS42L52_ADC_PGA_A   0x08

Definition at line 129 of file cs42l52.h.

#define CS42L52_ADC_PGA_B   0x09

Definition at line 130 of file cs42l52.h.

#define CS42L52_ADC_SEL_AIN1   0x00

Definition at line 132 of file cs42l52.h.

#define CS42L52_ADC_SEL_AIN2   0x01

Definition at line 133 of file cs42l52.h.

#define CS42L52_ADC_SEL_AIN3   0x02

Definition at line 134 of file cs42l52.h.

#define CS42L52_ADC_SEL_AIN4   0x03

Definition at line 135 of file cs42l52.h.

#define CS42L52_ADC_SEL_PGA   0x04

Definition at line 136 of file cs42l52.h.

#define CS42L52_ADC_SEL_SHIFT   5

Definition at line 131 of file cs42l52.h.

#define CS42L52_ADCA_MIXER_VOL   0x18

Definition at line 200 of file cs42l52.h.

#define CS42L52_ADCA_VOL   0x16

Definition at line 194 of file cs42l52.h.

#define CS42L52_ADCB_MIXER_VOL   0x19

Definition at line 201 of file cs42l52.h.

#define CS42L52_ADCB_VOL   0x17

Definition at line 195 of file cs42l52.h.

#define CS42L52_ADCX_VOL_12DB   12

Definition at line 197 of file cs42l52.h.

#define CS42L52_ADCX_VOL_24DB   24 /*step size 1db*/

Definition at line 196 of file cs42l52.h.

#define CS42L52_ADCX_VOL_6DB   6

Definition at line 198 of file cs42l52.h.

#define CS42L52_ALC_CTL   0x2A

Definition at line 233 of file cs42l52.h.

#define CS42L52_ALC_CTL_ALCA_ENABLE_SHIFT   6

Definition at line 235 of file cs42l52.h.

#define CS42L52_ALC_CTL_ALCB_ENABLE_SHIFT   7

Definition at line 234 of file cs42l52.h.

#define CS42L52_ALC_CTL_FASTEST_ATTACK   0

Definition at line 236 of file cs42l52.h.

#define CS42L52_ALC_MAX_RATE_SHIFT   5

Definition at line 242 of file cs42l52.h.

#define CS42L52_ALC_MIN_RATE_SHIFT   2

Definition at line 243 of file cs42l52.h.

#define CS42L52_ALC_RATE   0x2B

Definition at line 238 of file cs42l52.h.

#define CS42L52_ALC_RATE_0DB   0

Definition at line 244 of file cs42l52.h.

#define CS42L52_ALC_RATE_3DB   1

Definition at line 245 of file cs42l52.h.

#define CS42L52_ALC_RATE_6DB   2

Definition at line 246 of file cs42l52.h.

#define CS42L52_ALC_SLOWEST_RELEASE   0x3F

Definition at line 239 of file cs42l52.h.

#define CS42L52_ALC_THRESHOLD   0x2C

Definition at line 241 of file cs42l52.h.

#define CS42L52_ALL_IN_ONE   (1 << 16)

Definition at line 27 of file cs42l52.h.

#define CS42L52_ANALOG_HPF_CTL   0x0A

Definition at line 138 of file cs42l52.h.

#define CS42L52_BATT_COMPEN   0x2F

Definition at line 256 of file cs42l52.h.

#define CS42L52_BATT_LEVEL   0x30

Definition at line 258 of file cs42l52.h.

#define CS42L52_BEEP_EN_MASK   0x3F

Definition at line 214 of file cs42l52.h.

#define CS42L52_BEEP_FREQ   0x1C

Definition at line 207 of file cs42l52.h.

#define CS42L52_BEEP_RATE_MASK   0x0F

Definition at line 211 of file cs42l52.h.

#define CS42L52_BEEP_RATE_SHIFT   4

Definition at line 210 of file cs42l52.h.

#define CS42L52_BEEP_TONE_CTL   0x1E

Definition at line 209 of file cs42l52.h.

#define CS42L52_BEEP_VOL   0x1D

Definition at line 208 of file cs42l52.h.

#define CS42L52_CHARGE_PUMP   0x34

Definition at line 266 of file cs42l52.h.

#define CS42L52_CHARGE_PUMP_MASK   0xF0

Definition at line 267 of file cs42l52.h.

#define CS42L52_CHARGE_PUMP_SHIFT   4

Definition at line 268 of file cs42l52.h.

#define CS42L52_CHIP   0x01

Definition at line 34 of file cs42l52.h.

#define CS42L52_CHIP_ID   0xE0

Definition at line 35 of file cs42l52.h.

#define CS42L52_CHIP_ID_MASK   0xF8

Definition at line 36 of file cs42l52.h.

#define CS42L52_CHIP_MASK   0x0f

Definition at line 31 of file cs42l52.h.

#define CS42L52_CHIP_ONE   0x00

Definition at line 28 of file cs42l52.h.

#define CS42L52_CHIP_REV_A0   0x00

Definition at line 37 of file cs42l52.h.

#define CS42L52_CHIP_REV_A1   0x01

Definition at line 38 of file cs42l52.h.

#define CS42L52_CHIP_REV_B0   0x02

Definition at line 39 of file cs42l52.h.

#define CS42L52_CHIP_REV_MASK   0x03

Definition at line 40 of file cs42l52.h.

#define CS42L52_CHIP_SWICTH   (1 << 17)

Definition at line 26 of file cs42l52.h.

#define CS42L52_CHIP_THR   0x02

Definition at line 30 of file cs42l52.h.

#define CS42L52_CHIP_TWO   0x01

Definition at line 29 of file cs42l52.h.

#define CS42L52_CLK_CTL   0x05

Definition at line 86 of file cs42l52.h.

#define CS42L52_CLK_STATUS   0x2E

Definition at line 255 of file cs42l52.h.

#define CS42L52_DEFAULT_CLK   12000000

Definition at line 19 of file cs42l52.h.

#define CS42L52_DEFAULT_FORMAT   SNDRV_PCM_FMTBIT_S16_LE

Definition at line 22 of file cs42l52.h.

#define CS42L52_DEFAULT_HP_VOL   0xF0

Definition at line 221 of file cs42l52.h.

#define CS42L52_DEFAULT_MAX_CHANS   2

Definition at line 23 of file cs42l52.h.

#define CS42L52_DEFAULT_OUTPUT_STATE   0x05

Definition at line 83 of file cs42l52.h.

#define CS42L52_DEFAULT_SPK_VOL   0xF0

Definition at line 225 of file cs42l52.h.

#define CS42L52_FIX_BITS1   0x3E

Definition at line 269 of file cs42l52.h.

#define CS42L52_FIX_BITS2   0x47

Definition at line 270 of file cs42l52.h.

#define CS42L52_FIX_BITS_CTL   0x00

Definition at line 33 of file cs42l52.h.

#define CS42L52_HPA_VOL   0x22

Definition at line 219 of file cs42l52.h.

#define CS42L52_HPB_VOL   0x23

Definition at line 220 of file cs42l52.h.

#define CS42L52_HPF_CTL_ANLGSFTA   (1 << 0)

Definition at line 140 of file cs42l52.h.

#define CS42L52_HPF_CTL_ANLGSFTB   (1 << 3)

Definition at line 139 of file cs42l52.h.

#define CS42L52_IFACE_CTL1   0x06

Definition at line 105 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_ADC_FMT_I2S   (1 << 5)

Definition at line 109 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J   (0 << 5)

Definition at line 110 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_DAC_FMT_I2S   (1 << 2)

Definition at line 113 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J   (0 << 2)

Definition at line 112 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J   (2 << 2)

Definition at line 114 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_DSP_MODE_EN   (1 << 4)

Definition at line 111 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_INV_SCLK   (1 << 6)

Definition at line 108 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_MASTER   (1 << 7)

Definition at line 106 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_SLAVE   (0 << 7)

Definition at line 107 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_WL_16BIT   (0x03)

Definition at line 118 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_WL_20BIT   (0x02)

Definition at line 117 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_WL_24BIT   (0x01)

Definition at line 116 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_WL_32BIT   (0x00)

Definition at line 115 of file cs42l52.h.

#define CS42L52_IFACE_CTL1_WL_MASK   0xFFFF

Definition at line 119 of file cs42l52.h.

#define CS42L52_IFACE_CTL2   0x07

Definition at line 121 of file cs42l52.h.

#define CS42L52_IFACE_CTL2_BIAS_LVL   0x07

Definition at line 127 of file cs42l52.h.

#define CS42L52_IFACE_CTL2_HP_SW_INV   (1 << 3)

Definition at line 126 of file cs42l52.h.

#define CS42L52_IFACE_CTL2_LOOPBACK   (1 << 5)

Definition at line 123 of file cs42l52.h.

#define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_EN   (0 << 4)

Definition at line 124 of file cs42l52.h.

#define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_HIZ   (1 << 4)

Definition at line 125 of file cs42l52.h.

#define CS42L52_IFACE_CTL2_SC_MC_EQ   (1 << 6)

Definition at line 122 of file cs42l52.h.

#define CS42L52_LIMITER_AT_RATE   0x29

Definition at line 231 of file cs42l52.h.

#define CS42L52_LIMITER_CTL1   0x27

Definition at line 229 of file cs42l52.h.

#define CS42L52_LIMITER_CTL2   0x28

Definition at line 230 of file cs42l52.h.

#define CS42L52_MASTERA_VOL   0x20

Definition at line 216 of file cs42l52.h.

#define CS42L52_MASTERB_VOL   0x21

Definition at line 217 of file cs42l52.h.

#define CS42L52_MAX_CLK   27000000

Definition at line 21 of file cs42l52.h.

#define CS42L52_MAX_REGISTER   0x34

Definition at line 272 of file cs42l52.h.

#define CS42L52_MIC_CTL_MIC_SEL_MASK   0xBF

Definition at line 180 of file cs42l52.h.

#define CS42L52_MIC_CTL_MIC_SEL_SHIFT   6

Definition at line 181 of file cs42l52.h.

#define CS42L52_MIC_CTL_TYPE_MASK   0xDF

Definition at line 182 of file cs42l52.h.

#define CS42L52_MIC_CTL_TYPE_SHIFT   5

Definition at line 183 of file cs42l52.h.

#define CS42L52_MICA_CTL   0x10

Definition at line 178 of file cs42l52.h.

#define CS42L52_MICB_CTL   0x11

Definition at line 179 of file cs42l52.h.

#define CS42L52_MIN_CLK   11000000

Definition at line 20 of file cs42l52.h.

#define CS42L52_MISC_CTL   0x0E

Definition at line 164 of file cs42l52.h.

#define CS42L52_MISC_CTL_DEEMPH   (1 << 2)

Definition at line 165 of file cs42l52.h.

#define CS42L52_MISC_CTL_DIGSFT   (1 << 1)

Definition at line 166 of file cs42l52.h.

#define CS42L52_MISC_CTL_DIGZC   (1 << 0)

Definition at line 167 of file cs42l52.h.

#define CS42L52_NAME   "CS42L52"

Definition at line 18 of file cs42l52.h.

#define CS42L52_NG_DELAY_100MS   1

Definition at line 253 of file cs42l52.h.

#define CS42L52_NG_DELAY_SHIFT   0

Definition at line 252 of file cs42l52.h.

#define CS42L52_NG_ENABLE_SHIFT   6

Definition at line 249 of file cs42l52.h.

#define CS42L52_NG_MIN_70DB   2

Definition at line 251 of file cs42l52.h.

#define CS42L52_NG_THRESHOLD_SHIFT   2

Definition at line 250 of file cs42l52.h.

#define CS42L52_NOISE_GATE_CTL   0x2D

Definition at line 248 of file cs42l52.h.

#define CS42L52_PASSTHRUA_VOL   0x14

Definition at line 191 of file cs42l52.h.

#define CS42L52_PASSTHRUB_VOL   0x15

Definition at line 192 of file cs42l52.h.

#define CS42L52_PB_CTL1   0x0D

Definition at line 146 of file cs42l52.h.

#define CS42L52_PB_CTL1_HP_GAIN_03959   0x00

Definition at line 148 of file cs42l52.h.

#define CS42L52_PB_CTL1_HP_GAIN_04571   0x01

Definition at line 149 of file cs42l52.h.

#define CS42L52_PB_CTL1_HP_GAIN_05111   0x02

Definition at line 150 of file cs42l52.h.

#define CS42L52_PB_CTL1_HP_GAIN_06047   0x03

Definition at line 151 of file cs42l52.h.

#define CS42L52_PB_CTL1_HP_GAIN_07099   0x04

Definition at line 152 of file cs42l52.h.

#define CS42L52_PB_CTL1_HP_GAIN_08399   0x05

Definition at line 153 of file cs42l52.h.

#define CS42L52_PB_CTL1_HP_GAIN_10000   0x06

Definition at line 154 of file cs42l52.h.

#define CS42L52_PB_CTL1_HP_GAIN_11430   0x07

Definition at line 155 of file cs42l52.h.

#define CS42L52_PB_CTL1_HP_GAIN_SHIFT   5

Definition at line 147 of file cs42l52.h.

#define CS42L52_PB_CTL1_INV_PCMA   (1 << 2)

Definition at line 157 of file cs42l52.h.

#define CS42L52_PB_CTL1_INV_PCMB   (1 << 3)

Definition at line 156 of file cs42l52.h.

#define CS42L52_PB_CTL1_MSTA_MUTE   (1 << 0)

Definition at line 159 of file cs42l52.h.

#define CS42L52_PB_CTL1_MSTB_MUTE   (1 << 1)

Definition at line 158 of file cs42l52.h.

#define CS42L52_PB_CTL1_MUTE   3

Definition at line 161 of file cs42l52.h.

#define CS42L52_PB_CTL1_MUTE_MASK   0xFFFD

Definition at line 160 of file cs42l52.h.

#define CS42L52_PB_CTL1_UNMUTE   0

Definition at line 162 of file cs42l52.h.

#define CS42L52_PB_CTL2   0x0F

Definition at line 169 of file cs42l52.h.

#define CS42L52_PB_CTL2_HPA_MUTE   (1 << 6)

Definition at line 171 of file cs42l52.h.

#define CS42L52_PB_CTL2_HPB_MUTE   (1 << 7)

Definition at line 170 of file cs42l52.h.

#define CS42L52_PB_CTL2_SPK_MONO   (1 << 1)

Definition at line 175 of file cs42l52.h.

#define CS42L52_PB_CTL2_SPK_MUTE50   (1 << 0)

Definition at line 176 of file cs42l52.h.

#define CS42L52_PB_CTL2_SPK_SWAP   (1 << 2)

Definition at line 174 of file cs42l52.h.

#define CS42L52_PB_CTL2_SPKA_MUTE   (1 << 4)

Definition at line 173 of file cs42l52.h.

#define CS42L52_PB_CTL2_SPKB_MUTE   (1 << 5)

Definition at line 172 of file cs42l52.h.

#define CS42L52_PCMA_MIXER_VOL   0x1A

Definition at line 204 of file cs42l52.h.

#define CS42L52_PCMB_MIXER_VOL   0x1B

Definition at line 205 of file cs42l52.h.

#define CS42L52_PGAA_CTL   0x12

Definition at line 186 of file cs42l52.h.

#define CS42L52_PGAB_CTL   0x13

Definition at line 187 of file cs42l52.h.

#define CS42L52_PGAX_CTL_VOL_12DB   24

Definition at line 188 of file cs42l52.h.

#define CS42L52_PGAX_CTL_VOL_6DB   12 /*step size 0.5db*/

Definition at line 189 of file cs42l52.h.

#define CS42L52_PWRCTL1   0x02

Definition at line 42 of file cs42l52.h.

#define CS42L52_PWRCTL1_PDN_ADCA   0x02

Definition at line 48 of file cs42l52.h.

#define CS42L52_PWRCTL1_PDN_ADCB   0x04

Definition at line 47 of file cs42l52.h.

#define CS42L52_PWRCTL1_PDN_ALL   0x9F

Definition at line 43 of file cs42l52.h.

#define CS42L52_PWRCTL1_PDN_CHRG   0x80

Definition at line 44 of file cs42l52.h.

#define CS42L52_PWRCTL1_PDN_CODEC   0x01

Definition at line 49 of file cs42l52.h.

#define CS42L52_PWRCTL1_PDN_PGAA   0x08

Definition at line 46 of file cs42l52.h.

#define CS42L52_PWRCTL1_PDN_PGAB   0x10

Definition at line 45 of file cs42l52.h.

#define CS42L52_PWRCTL2   0x03

Definition at line 51 of file cs42l52.h.

#define CS42L52_PWRCTL2_OVRDA   (1 << 3)

Definition at line 53 of file cs42l52.h.

#define CS42L52_PWRCTL2_OVRDB   (1 << 4)

Definition at line 52 of file cs42l52.h.

#define CS42L52_PWRCTL2_PDN_MICA   (1 << 1)

Definition at line 56 of file cs42l52.h.

#define CS42L52_PWRCTL2_PDN_MICA_SHIFT   1

Definition at line 57 of file cs42l52.h.

#define CS42L52_PWRCTL2_PDN_MICB   (1 << 2)

Definition at line 54 of file cs42l52.h.

#define CS42L52_PWRCTL2_PDN_MICB_SHIFT   2

Definition at line 55 of file cs42l52.h.

#define CS42L52_PWRCTL2_PDN_MICBIAS   (1 << 0)

Definition at line 58 of file cs42l52.h.

#define CS42L52_PWRCTL2_PDN_MICBIAS_SHIFT   0

Definition at line 59 of file cs42l52.h.

#define CS42L52_PWRCTL3   0x04

Definition at line 61 of file cs42l52.h.

#define CS42L52_PWRCTL3_CONF_MASK   0x03

Definition at line 84 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPA_ALWAYS_OFF   0x03

Definition at line 71 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPA_ALWAYS_ON   0x02

Definition at line 70 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPA_ON_HIGH   0x01

Definition at line 69 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPA_ON_LOW   0x00

Definition at line 68 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPA_PDN_SHIFT   4

Definition at line 67 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPB_ALWAYS_OFF   0x03

Definition at line 66 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPB_ALWAYS_ON   0x02

Definition at line 65 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPB_ON_HIGH   0x01

Definition at line 64 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPB_ON_LOW   0x00

Definition at line 63 of file cs42l52.h.

#define CS42L52_PWRCTL3_HPB_PDN_SHIFT   6

Definition at line 62 of file cs42l52.h.

#define CS42L52_PWRCTL3_PDN_SPKA   (1 << 0)

Definition at line 77 of file cs42l52.h.

#define CS42L52_PWRCTL3_PDN_SPKB   (1 << 2)

Definition at line 76 of file cs42l52.h.

#define CS42L52_PWRCTL3_SPKA_ALWAYS_ON   0x02

Definition at line 81 of file cs42l52.h.

#define CS42L52_PWRCTL3_SPKA_ON_HIGH   0x01

Definition at line 80 of file cs42l52.h.

#define CS42L52_PWRCTL3_SPKA_ON_LOW   0x00

Definition at line 79 of file cs42l52.h.

#define CS42L52_PWRCTL3_SPKA_PDN_SHIFT   0

Definition at line 78 of file cs42l52.h.

#define CS42L52_PWRCTL3_SPKB_ALWAYS_ON   0x02

Definition at line 75 of file cs42l52.h.

#define CS42L52_PWRCTL3_SPKB_ON_HIGH   0x01

Definition at line 74 of file cs42l52.h.

#define CS42L52_PWRCTL3_SPKB_ON_LOW   0x00

Definition at line 73 of file cs42l52.h.

#define CS42L52_PWRCTL3_SPKB_PDN_SHIFT   2

Definition at line 72 of file cs42l52.h.

#define CS42L52_SPK_STATUS   0x31

Definition at line 259 of file cs42l52.h.

#define CS42L52_SPK_STATUS_PIN_HIGH   1

Definition at line 261 of file cs42l52.h.

#define CS42L52_SPK_STATUS_PIN_SHIFT   3

Definition at line 260 of file cs42l52.h.

#define CS42L52_SPKA_VOL   0x24

Definition at line 223 of file cs42l52.h.

#define CS42L52_SPKB_VOL   0x25

Definition at line 224 of file cs42l52.h.

#define CS42L52_SYSCLK   1

Definition at line 24 of file cs42l52.h.

#define CS42L52_TEM_CTL   0x32

Definition at line 263 of file cs42l52.h.

#define CS42L52_TEM_CTL_SET   0x80

Definition at line 264 of file cs42l52.h.

#define CS42L52_THE_FOLDBACK   0x33

Definition at line 265 of file cs42l52.h.

#define CS42L52_TONE_CTL   0x1F

Definition at line 213 of file cs42l52.h.