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7 #ifndef __ASM_SPARC64_PROCESSOR_H
8 #define __ASM_SPARC64_PROCESSOR_H
14 #define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
18 #include <asm/ptrace.h>
22 #define __ARCH_WANT_UNLOCKED_CTXSW
26 #define wp_works_ok__is_a_macro
37 #define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
39 #define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
42 #define TASK_SIZE_OF(tsk) \
43 (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
44 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
46 (test_thread_flag(TIF_32BIT) ? \
47 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
50 #define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
51 #define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
53 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
54 STACK_TOP32 : STACK_TOP64)
56 #define STACK_TOP_MAX STACK_TOP64
69 #ifdef CONFIG_DEBUG_SPINLOCK
75 unsigned int smp_lock_pc;
83 #ifndef CONFIG_DEBUG_SPINLOCK
84 #define INIT_THREAD { \
88 #define INIT_THREAD { \
96 #include <linux/types.h>
104 #define TSTATE_INITIAL_MM TSTATE_TSO
106 #define TSTATE_INITIAL_MM TSTATE_RMO
110 #define start_thread(regs, pc, sp) \
112 unsigned long __asi = ASI_PNF; \
113 regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
114 regs->tpc = ((pc & (~3)) - 4); \
115 regs->tnpc = regs->tpc + 4; \
117 set_thread_wstate(1 << 3); \
118 if (current_thread_info()->utraps) { \
119 if (*(current_thread_info()->utraps) < 2) \
120 kfree(current_thread_info()->utraps); \
122 (*(current_thread_info()->utraps))--; \
123 current_thread_info()->utraps = NULL; \
125 __asm__ __volatile__( \
126 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
127 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
128 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
129 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
130 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
131 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
132 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
133 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
134 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
135 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
136 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
137 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
138 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
139 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
140 "stx %1, [%0 + %2 + 0x70]\n\t" \
141 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
142 "wrpr %%g0, (1 << 3), %%wstate\n\t" \
144 : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
145 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
148 #define start_thread32(regs, pc, sp) \
150 unsigned long __asi = ASI_PNF; \
151 pc &= 0x00000000ffffffffUL; \
152 sp &= 0x00000000ffffffffUL; \
153 regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
154 regs->tpc = ((pc & (~3)) - 4); \
155 regs->tnpc = regs->tpc + 4; \
157 set_thread_wstate(2 << 3); \
158 if (current_thread_info()->utraps) { \
159 if (*(current_thread_info()->utraps) < 2) \
160 kfree(current_thread_info()->utraps); \
162 (*(current_thread_info()->utraps))--; \
163 current_thread_info()->utraps = NULL; \
165 __asm__ __volatile__( \
166 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
167 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
168 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
169 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
170 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
171 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
172 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
173 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
174 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
175 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
176 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
177 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
178 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
179 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
180 "stx %1, [%0 + %2 + 0x70]\n\t" \
181 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
182 "wrpr %%g0, (2 << 3), %%wstate\n\t" \
184 : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
185 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
189 #define release_thread(tsk) do { } while (0)
195 #define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
196 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
197 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
204 #define cpu_relax() asm volatile("\n99:\n\t" \
205 "rd %%ccr, %%g0\n\t" \
206 "rd %%ccr, %%g0\n\t" \
207 "rd %%ccr, %%g0\n\t" \
208 ".section .pause_3insn_patch,\"ax\"\n\t"\
210 "wr %%g0, 128, %%asr27\n\t" \
220 #define ARCH_HAS_PREFETCH
221 #define ARCH_HAS_PREFETCHW
222 #define ARCH_HAS_SPINLOCK_PREFETCH
224 static inline void prefetch(
const void *
x)
232 __asm__ __volatile__(
"prefetch [%0], #one_write"
243 __asm__ __volatile__(
"prefetch [%0], #n_writes"
248 #define spin_lock_prefetch(x) prefetchw(x)
250 #define HAVE_ARCH_PICK_MMAP_LAYOUT