#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/spi/spi.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl022.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/scatterlist.h>
#include <linux/pm_runtime.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/pinctrl/consumer.h>

Data Structures
struct	vendor_data

struct	pl022

struct	chip_data

Macros
#define	SSP_WRITE_BITS(reg, val, mask, sb) ((reg) = (((reg) & ~(mask)) \| (((val)<<(sb)) & (mask))))

#define	GEN_MASK_BITS(val, mask, sb) (((val)<<(sb)) & (mask))

#define	DRIVE_TX 0

#define	DO_NOT_DRIVE_TX 1

#define	DO_NOT_QUEUE_DMA 0

#define	QUEUE_DMA 1

#define	RX_TRANSFER 1

#define	TX_TRANSFER 2

#define	SSP_CR0(r) (r + 0x000)

#define	SSP_CR1(r) (r + 0x004)

#define	SSP_DR(r) (r + 0x008)

#define	SSP_SR(r) (r + 0x00C)

#define	SSP_CPSR(r) (r + 0x010)

#define	SSP_IMSC(r) (r + 0x014)

#define	SSP_RIS(r) (r + 0x018)

#define	SSP_MIS(r) (r + 0x01C)

#define	SSP_ICR(r) (r + 0x020)

#define	SSP_DMACR(r) (r + 0x024)

#define	SSP_ITCR(r) (r + 0x080)

#define	SSP_ITIP(r) (r + 0x084)

#define	SSP_ITOP(r) (r + 0x088)

#define	SSP_TDR(r) (r + 0x08C)

#define	SSP_PID0(r) (r + 0xFE0)

#define	SSP_PID1(r) (r + 0xFE4)

#define	SSP_PID2(r) (r + 0xFE8)

#define	SSP_PID3(r) (r + 0xFEC)

#define	SSP_CID0(r) (r + 0xFF0)

#define	SSP_CID1(r) (r + 0xFF4)

#define	SSP_CID2(r) (r + 0xFF8)

#define	SSP_CID3(r) (r + 0xFFC)

#define	SSP_CR0_MASK_DSS (0x0FUL << 0)

#define	SSP_CR0_MASK_FRF (0x3UL << 4)

#define	SSP_CR0_MASK_SPO (0x1UL << 6)

#define	SSP_CR0_MASK_SPH (0x1UL << 7)

#define	SSP_CR0_MASK_SCR (0xFFUL << 8)

#define	SSP_CR0_MASK_DSS_ST (0x1FUL << 0)

#define	SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)

#define	SSP_CR0_MASK_CSS_ST (0x1FUL << 16)

#define	SSP_CR0_MASK_FRF_ST (0x3UL << 21)

#define	SSP_CR1_MASK_LBM (0x1UL << 0)

#define	SSP_CR1_MASK_SSE (0x1UL << 1)

#define	SSP_CR1_MASK_MS (0x1UL << 2)

#define	SSP_CR1_MASK_SOD (0x1UL << 3)

#define	SSP_CR1_MASK_RENDN_ST (0x1UL << 4)

#define	SSP_CR1_MASK_TENDN_ST (0x1UL << 5)

#define	SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)

#define	SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)

#define	SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)

#define	SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)

#define	SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */

#define	SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */

#define	SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */

#define	SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */

#define	SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */

#define	SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)

#define	SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */

#define	SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */

#define	SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */

#define	SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */

#define	SSP_RIS_MASK_RORRIS (0x1UL << 0)

#define	SSP_RIS_MASK_RTRIS (0x1UL << 1)

#define	SSP_RIS_MASK_RXRIS (0x1UL << 2)

#define	SSP_RIS_MASK_TXRIS (0x1UL << 3)

#define	SSP_MIS_MASK_RORMIS (0x1UL << 0)

#define	SSP_MIS_MASK_RTMIS (0x1UL << 1)

#define	SSP_MIS_MASK_RXMIS (0x1UL << 2)

#define	SSP_MIS_MASK_TXMIS (0x1UL << 3)

#define	SSP_ICR_MASK_RORIC (0x1UL << 0)

#define	SSP_ICR_MASK_RTIC (0x1UL << 1)

#define	SSP_DMACR_MASK_RXDMAE (0x1UL << 0)

#define	SSP_DMACR_MASK_TXDMAE (0x1UL << 1)

#define	SSP_ITCR_MASK_ITEN (0x1UL << 0)

#define	SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)

#define	ITIP_MASK_SSPRXD (0x1UL << 0)

#define	ITIP_MASK_SSPFSSIN (0x1UL << 1)

#define	ITIP_MASK_SSPCLKIN (0x1UL << 2)

#define	ITIP_MASK_RXDMAC (0x1UL << 3)

#define	ITIP_MASK_TXDMAC (0x1UL << 4)

#define	ITIP_MASK_SSPTXDIN (0x1UL << 5)

#define	ITOP_MASK_SSPTXD (0x1UL << 0)

#define	ITOP_MASK_SSPFSSOUT (0x1UL << 1)

#define	ITOP_MASK_SSPCLKOUT (0x1UL << 2)

#define	ITOP_MASK_SSPOEn (0x1UL << 3)

#define	ITOP_MASK_SSPCTLOEn (0x1UL << 4)

#define	ITOP_MASK_RORINTR (0x1UL << 5)

#define	ITOP_MASK_RTINTR (0x1UL << 6)

#define	ITOP_MASK_RXINTR (0x1UL << 7)

#define	ITOP_MASK_TXINTR (0x1UL << 8)

#define	ITOP_MASK_INTR (0x1UL << 9)

#define	ITOP_MASK_RXDMABREQ (0x1UL << 10)

#define	ITOP_MASK_RXDMASREQ (0x1UL << 11)

#define	ITOP_MASK_TXDMABREQ (0x1UL << 12)

#define	ITOP_MASK_TXDMASREQ (0x1UL << 13)

#define	TDR_MASK_TESTDATA (0xFFFFFFFF)

#define	STATE_START ((void *) 0)

#define	STATE_RUNNING ((void *) 1)

#define	STATE_DONE ((void *) 2)

#define	STATE_ERROR ((void *) -1)

#define	SSP_DISABLED (0)

#define	SSP_ENABLED (1)

#define	SSP_DMA_DISABLED (0)

#define	SSP_DMA_ENABLED (1)

#define	SSP_DEFAULT_CLKRATE 0x2

#define	SSP_DEFAULT_PRESCALE 0x40

#define	CPSDVR_MIN 0x02

#define	CPSDVR_MAX 0xFE

#define	SCR_MIN 0x00

#define	SCR_MAX 0xFF

#define	DEFAULT_SSP_REG_IMSC 0x0UL

#define	DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC

#define	ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)

#define	CLEAR_ALL_INTERRUPTS 0x3

#define	SPI_POLLING_TIMEOUT 1000

#define	DEFAULT_SSP_REG_CR0

#define	DEFAULT_SSP_REG_CR0_ST

#define	DEFAULT_SSP_REG_CR0_ST_PL023

#define	DEFAULT_SSP_REG_CR1

#define	DEFAULT_SSP_REG_CR1_ST

#define	DEFAULT_SSP_REG_CR1_ST_PL023

#define	DEFAULT_SSP_REG_CPSR

#define	DEFAULT_SSP_REG_DMACR

Enumerations
enum	ssp_reading { READING_NULL, READING_U8, READING_U16, READING_U32 }

enum	ssp_writing { WRITING_NULL, WRITING_U8, WRITING_U16, WRITING_U32 }

Functions
	MODULE_DEVICE_TABLE (amba, pl022_ids)

	subsys_initcall (pl022_init)

	module_exit (pl022_exit)

	MODULE_AUTHOR ("Linus Walleij <[email protected]>")

	MODULE_DESCRIPTION ("PL022 SSP Controller Driver")

	MODULE_LICENSE ("GPL")

Macro Definition Documentation

#define CLEAR_ALL_INTERRUPTS 0x3

Definition at line 283 of file spi-pl022.c.

#define CPSDVR_MAX 0xFE

Definition at line 272 of file spi-pl022.c.

#define CPSDVR_MIN 0x02

Definition at line 271 of file spi-pl022.c.

#define DEFAULT_SSP_REG_CPSR

Value:

( \
    GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
)

Definition at line 618 of file spi-pl022.c.

#define DEFAULT_SSP_REG_CR0

Value:

( \
    GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0)    | \
    GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
    GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
    GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
    GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
)

Definition at line 559 of file spi-pl022.c.

#define DEFAULT_SSP_REG_CR0_ST

Value:

( \
    GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
    GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
    GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
    GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
    GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
    GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16)  | \
    GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
)

Definition at line 568 of file spi-pl022.c.

#define DEFAULT_SSP_REG_CR0_ST_PL023

Value:

( \
    GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
    GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
    GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
    GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
)

Definition at line 579 of file spi-pl022.c.

#define DEFAULT_SSP_REG_CR1

Value:

( \
    GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
    GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
    GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
    GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
)

Definition at line 586 of file spi-pl022.c.

#define DEFAULT_SSP_REG_CR1_ST

Value:

( \
    DEFAULT_SSP_REG_CR1 | \
    GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
    GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
    GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
    GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
    GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
)

Definition at line 594 of file spi-pl022.c.

#define DEFAULT_SSP_REG_CR1_ST_PL023

Value:

( \
    GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
    GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
    GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
    GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
    GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
    GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
    GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
    GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
)

Definition at line 607 of file spi-pl022.c.

#define DEFAULT_SSP_REG_DMACR

Value:

(\
    GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
    GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
)

Definition at line 622 of file spi-pl022.c.

#define DEFAULT_SSP_REG_IMSC 0x0UL

Definition at line 279 of file spi-pl022.c.

#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC

Definition at line 280 of file spi-pl022.c.

#define DO_NOT_DRIVE_TX 1

Definition at line 64 of file spi-pl022.c.

#define DO_NOT_QUEUE_DMA 0

Definition at line 66 of file spi-pl022.c.

#define DRIVE_TX 0

Definition at line 63 of file spi-pl022.c.

#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)

Definition at line 281 of file spi-pl022.c.

#define GEN_MASK_BITS	(	val,
		mask,
		sb
	)	(((val)<<(sb)) & (mask))

Definition at line 60 of file spi-pl022.c.

#define ITIP_MASK_RXDMAC (0x1UL << 3)

Definition at line 212 of file spi-pl022.c.

#define ITIP_MASK_SSPCLKIN (0x1UL << 2)

Definition at line 211 of file spi-pl022.c.

#define ITIP_MASK_SSPFSSIN (0x1UL << 1)

Definition at line 210 of file spi-pl022.c.

#define ITIP_MASK_SSPRXD (0x1UL << 0)

Definition at line 209 of file spi-pl022.c.

#define ITIP_MASK_SSPTXDIN (0x1UL << 5)

Definition at line 214 of file spi-pl022.c.

#define ITIP_MASK_TXDMAC (0x1UL << 4)

Definition at line 213 of file spi-pl022.c.

#define ITOP_MASK_INTR (0x1UL << 9)

Definition at line 228 of file spi-pl022.c.

#define ITOP_MASK_RORINTR (0x1UL << 5)

Definition at line 224 of file spi-pl022.c.

#define ITOP_MASK_RTINTR (0x1UL << 6)

Definition at line 225 of file spi-pl022.c.

#define ITOP_MASK_RXDMABREQ (0x1UL << 10)

Definition at line 229 of file spi-pl022.c.

#define ITOP_MASK_RXDMASREQ (0x1UL << 11)

Definition at line 230 of file spi-pl022.c.

#define ITOP_MASK_RXINTR (0x1UL << 7)

Definition at line 226 of file spi-pl022.c.

#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)

Definition at line 221 of file spi-pl022.c.

#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)

Definition at line 223 of file spi-pl022.c.

#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)

Definition at line 220 of file spi-pl022.c.

#define ITOP_MASK_SSPOEn (0x1UL << 3)

Definition at line 222 of file spi-pl022.c.

#define ITOP_MASK_SSPTXD (0x1UL << 0)

Definition at line 219 of file spi-pl022.c.

#define ITOP_MASK_TXDMABREQ (0x1UL << 12)

Definition at line 231 of file spi-pl022.c.

#define ITOP_MASK_TXDMASREQ (0x1UL << 13)

Definition at line 232 of file spi-pl022.c.

#define ITOP_MASK_TXINTR (0x1UL << 8)

Definition at line 227 of file spi-pl022.c.

#define QUEUE_DMA 1

Definition at line 67 of file spi-pl022.c.

#define RX_TRANSFER 1

Definition at line 69 of file spi-pl022.c.

#define SCR_MAX 0xFF

Definition at line 274 of file spi-pl022.c.

#define SCR_MIN 0x00

Definition at line 273 of file spi-pl022.c.

#define SPI_POLLING_TIMEOUT 1000

Definition at line 285 of file spi-pl022.c.

#define SSP_CID0 ( r ) (r + 0xFF0)

Definition at line 95 of file spi-pl022.c.

#define SSP_CID1 ( r ) (r + 0xFF4)

Definition at line 96 of file spi-pl022.c.

#define SSP_CID2 ( r ) (r + 0xFF8)

Definition at line 97 of file spi-pl022.c.

#define SSP_CID3 ( r ) (r + 0xFFC)

Definition at line 98 of file spi-pl022.c.

#define SSP_CPSR ( r ) (r + 0x010)

Definition at line 79 of file spi-pl022.c.

#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)

Definition at line 150 of file spi-pl022.c.

#define SSP_CR0 ( r ) (r + 0x000)

Definition at line 75 of file spi-pl022.c.

#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)

Definition at line 115 of file spi-pl022.c.

#define SSP_CR0_MASK_DSS (0x0FUL << 0)

Definition at line 103 of file spi-pl022.c.

#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)

Definition at line 113 of file spi-pl022.c.

#define SSP_CR0_MASK_FRF (0x3UL << 4)

Definition at line 104 of file spi-pl022.c.

#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)

Definition at line 116 of file spi-pl022.c.

#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)

Definition at line 114 of file spi-pl022.c.

#define SSP_CR0_MASK_SCR (0xFFUL << 8)

Definition at line 107 of file spi-pl022.c.

#define SSP_CR0_MASK_SPH (0x1UL << 7)

Definition at line 106 of file spi-pl022.c.

#define SSP_CR0_MASK_SPO (0x1UL << 6)

Definition at line 105 of file spi-pl022.c.

#define SSP_CR1 ( r ) (r + 0x004)

Definition at line 76 of file spi-pl022.c.

#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)

Definition at line 136 of file spi-pl022.c.

#define SSP_CR1_MASK_LBM (0x1UL << 0)

Definition at line 121 of file spi-pl022.c.

#define SSP_CR1_MASK_MS (0x1UL << 2)

Definition at line 123 of file spi-pl022.c.

#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)

Definition at line 132 of file spi-pl022.c.

#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)

Definition at line 130 of file spi-pl022.c.

#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)

Definition at line 133 of file spi-pl022.c.

#define SSP_CR1_MASK_SOD (0x1UL << 3)

Definition at line 124 of file spi-pl022.c.

#define SSP_CR1_MASK_SSE (0x1UL << 1)

Definition at line 122 of file spi-pl022.c.

#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)

Definition at line 131 of file spi-pl022.c.

#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)

Definition at line 134 of file spi-pl022.c.

#define SSP_DEFAULT_CLKRATE 0x2

Definition at line 265 of file spi-pl022.c.

#define SSP_DEFAULT_PRESCALE 0x40

Definition at line 266 of file spi-pl022.c.

#define SSP_DISABLED (0)

Definition at line 253 of file spi-pl022.c.

#define SSP_DMA_DISABLED (0)

Definition at line 259 of file spi-pl022.c.

#define SSP_DMA_ENABLED (1)

Definition at line 260 of file spi-pl022.c.

#define SSP_DMACR ( r ) (r + 0x024)

Definition at line 84 of file spi-pl022.c.

#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)

Definition at line 196 of file spi-pl022.c.

#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)

Definition at line 198 of file spi-pl022.c.

#define SSP_DR ( r ) (r + 0x008)

Definition at line 77 of file spi-pl022.c.

#define SSP_ENABLED (1)

Definition at line 254 of file spi-pl022.c.

#define SSP_ICR ( r ) (r + 0x020)

Definition at line 83 of file spi-pl022.c.

#define SSP_ICR_MASK_RORIC (0x1UL << 0)

Definition at line 188 of file spi-pl022.c.

#define SSP_ICR_MASK_RTIC (0x1UL << 1)

Definition at line 190 of file spi-pl022.c.

#define SSP_IMSC ( r ) (r + 0x014)

Definition at line 80 of file spi-pl022.c.

#define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */

Definition at line 155 of file spi-pl022.c.

#define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */

Definition at line 156 of file spi-pl022.c.

#define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */

Definition at line 157 of file spi-pl022.c.

#define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */

Definition at line 158 of file spi-pl022.c.

#define SSP_ITCR ( r ) (r + 0x080)

Definition at line 85 of file spi-pl022.c.

#define SSP_ITCR_MASK_ITEN (0x1UL << 0)

Definition at line 203 of file spi-pl022.c.

#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)

Definition at line 204 of file spi-pl022.c.

#define SSP_ITIP ( r ) (r + 0x084)

Definition at line 86 of file spi-pl022.c.

#define SSP_ITOP ( r ) (r + 0x088)

Definition at line 87 of file spi-pl022.c.

#define SSP_MIS ( r ) (r + 0x01C)

Definition at line 82 of file spi-pl022.c.

#define SSP_MIS_MASK_RORMIS (0x1UL << 0)

Definition at line 176 of file spi-pl022.c.

#define SSP_MIS_MASK_RTMIS (0x1UL << 1)

Definition at line 178 of file spi-pl022.c.

#define SSP_MIS_MASK_RXMIS (0x1UL << 2)

Definition at line 180 of file spi-pl022.c.

#define SSP_MIS_MASK_TXMIS (0x1UL << 3)

Definition at line 182 of file spi-pl022.c.

#define SSP_PID0 ( r ) (r + 0xFE0)

Definition at line 90 of file spi-pl022.c.

#define SSP_PID1 ( r ) (r + 0xFE4)

Definition at line 91 of file spi-pl022.c.

#define SSP_PID2 ( r ) (r + 0xFE8)

Definition at line 92 of file spi-pl022.c.

#define SSP_PID3 ( r ) (r + 0xFEC)

Definition at line 93 of file spi-pl022.c.

#define SSP_RIS ( r ) (r + 0x018)

Definition at line 81 of file spi-pl022.c.

#define SSP_RIS_MASK_RORRIS (0x1UL << 0)

Definition at line 164 of file spi-pl022.c.

#define SSP_RIS_MASK_RTRIS (0x1UL << 1)

Definition at line 166 of file spi-pl022.c.

#define SSP_RIS_MASK_RXRIS (0x1UL << 2)

Definition at line 168 of file spi-pl022.c.

#define SSP_RIS_MASK_TXRIS (0x1UL << 3)

Definition at line 170 of file spi-pl022.c.

#define SSP_SR ( r ) (r + 0x00C)

Definition at line 78 of file spi-pl022.c.

#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */

Definition at line 145 of file spi-pl022.c.

#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */

Definition at line 144 of file spi-pl022.c.

#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */

Definition at line 143 of file spi-pl022.c.

#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */

Definition at line 141 of file spi-pl022.c.

#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */

Definition at line 142 of file spi-pl022.c.

#define SSP_TDR ( r ) (r + 0x08C)

Definition at line 88 of file spi-pl022.c.

#define SSP_WRITE_BITS	(	reg,
		val,
		mask,
		sb
	)	((reg) = (((reg) & ~(mask)) \| (((val)<<(sb)) & (mask))))

Definition at line 52 of file spi-pl022.c.

#define STATE_DONE ((void *) 2)

Definition at line 247 of file spi-pl022.c.

#define STATE_ERROR ((void *) -1)

Definition at line 248 of file spi-pl022.c.

#define STATE_RUNNING ((void *) 1)

Definition at line 246 of file spi-pl022.c.

#define STATE_START ((void *) 0)

Definition at line 245 of file spi-pl022.c.

#define TDR_MASK_TESTDATA (0xFFFFFFFF)

Definition at line 237 of file spi-pl022.c.

#define TX_TRANSFER 2

Definition at line 70 of file spi-pl022.c.

Enumeration Type Documentation

enum ssp_reading

Enumerator:

READING_NULL
READING_U8
READING_U16
READING_U32

Definition at line 290 of file spi-pl022.c.

enum ssp_writing

The type of writing going on on this chip

Enumerator:

WRITING_NULL
WRITING_U8
WRITING_U16
WRITING_U32

Definition at line 300 of file spi-pl022.c.

Function Documentation

MODULE_AUTHOR ( "Linus Walleij <[email protected]>" )

MODULE_DESCRIPTION ( "PL022 SSP Controller Driver" )

MODULE_DEVICE_TABLE	(	amba	,
		pl022_ids
	)

module_exit ( pl022_exit )

MODULE_LICENSE ( "GPL" )

subsys_initcall ( pl022_init )

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation