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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/delay.h>#include <linux/pci.h>#include <linux/wait.h>#include <linux/spi/spi.h>#include <linux/interrupt.h>#include <linux/sched.h>#include <linux/spi/spidev.h>#include <linux/module.h>#include <linux/device.h>#include <linux/platform_device.h>#include <linux/dmaengine.h>#include <linux/pch_dma.h>Go to the source code of this file.
Data Structures | |
| struct | pch_spi_dma_ctrl |
| struct | pch_spi_data |
| struct | pch_spi_board_data |
| struct | pch_pd_dev_save |
Macros | |
| #define | PCH_SPCR 0x00 /* SPI control register */ |
| #define | PCH_SPBRR 0x04 /* SPI baud rate register */ |
| #define | PCH_SPSR 0x08 /* SPI status register */ |
| #define | PCH_SPDWR 0x0C /* SPI write data register */ |
| #define | PCH_SPDRR 0x10 /* SPI read data register */ |
| #define | PCH_SSNXCR 0x18 /* SSN Expand Control Register */ |
| #define | PCH_SRST 0x1C /* SPI reset register */ |
| #define | PCH_ADDRESS_SIZE 0x20 |
| #define | PCH_SPSR_TFD 0x000007C0 |
| #define | PCH_SPSR_RFD 0x0000F800 |
| #define | PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11) |
| #define | PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6) |
| #define | PCH_RX_THOLD 7 |
| #define | PCH_RX_THOLD_MAX 15 |
| #define | PCH_TX_THOLD 2 |
| #define | PCH_MAX_BAUDRATE 5000000 |
| #define | PCH_MAX_FIFO_DEPTH 16 |
| #define | STATUS_RUNNING 1 |
| #define | STATUS_EXITING 2 |
| #define | PCH_SLEEP_TIME 10 |
| #define | SSN_LOW 0x02U |
| #define | SSN_HIGH 0x03U |
| #define | SSN_NO_CONTROL 0x00U |
| #define | PCH_MAX_CS 0xFF |
| #define | PCI_DEVICE_ID_GE_SPI 0x8816 |
| #define | SPCR_SPE_BIT (1 << 0) |
| #define | SPCR_MSTR_BIT (1 << 1) |
| #define | SPCR_LSBF_BIT (1 << 4) |
| #define | SPCR_CPHA_BIT (1 << 5) |
| #define | SPCR_CPOL_BIT (1 << 6) |
| #define | SPCR_TFIE_BIT (1 << 8) |
| #define | SPCR_RFIE_BIT (1 << 9) |
| #define | SPCR_FIE_BIT (1 << 10) |
| #define | SPCR_ORIE_BIT (1 << 11) |
| #define | SPCR_MDFIE_BIT (1 << 12) |
| #define | SPCR_FICLR_BIT (1 << 24) |
| #define | SPSR_TFI_BIT (1 << 0) |
| #define | SPSR_RFI_BIT (1 << 1) |
| #define | SPSR_FI_BIT (1 << 2) |
| #define | SPSR_ORF_BIT (1 << 3) |
| #define | SPBRR_SIZE_BIT (1 << 10) |
| #define | PCH_ALL |
| #define | SPCR_RFIC_FIELD 20 |
| #define | SPCR_TFIC_FIELD 16 |
| #define | MASK_SPBRR_SPBR_BITS ((1 << 10) - 1) |
| #define | MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD) |
| #define | MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD) |
| #define | PCH_CLOCK_HZ 50000000 |
| #define | PCH_MAX_SPBR 1023 |
| #define | PCI_VENDOR_ID_ROHM 0x10DB |
| #define | PCI_DEVICE_ID_ML7213_SPI 0x802c |
| #define | PCI_DEVICE_ID_ML7223_SPI 0x800F |
| #define | PCI_DEVICE_ID_ML7831_SPI 0x8816 |
| #define | PCH_SPI_MAX_DEV 2 |
| #define | PCH_BUF_SIZE 4096 |
| #define | PCH_DMA_TRANS_SIZE 12 |
| #define | pch_spi_pd_suspend NULL |
| #define | pch_spi_pd_resume NULL |
| #define | pch_spi_suspend NULL |
| #define | pch_spi_resume NULL |
Functions | |
| module_init (pch_spi_init) | |
| module_exit (pch_spi_exit) | |
| module_param (use_dma, int, 0644) | |
| MODULE_PARM_DESC (use_dma,"to use DMA for data transfers pass 1 else 0; default 1") | |
| MODULE_LICENSE ("GPL") | |
| MODULE_DESCRIPTION ("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver") | |
| #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD) |
Definition at line 92 of file spi-topcliff-pch.c.
| #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1) |
Definition at line 91 of file spi-topcliff-pch.c.
| #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD) |
Definition at line 93 of file spi-topcliff-pch.c.
| #define PCH_ADDRESS_SIZE 0x20 |
Definition at line 42 of file spi-topcliff-pch.c.
| #define PCH_ALL |
Definition at line 85 of file spi-topcliff-pch.c.
| #define PCH_BUF_SIZE 4096 |
Definition at line 113 of file spi-topcliff-pch.c.
| #define PCH_CLOCK_HZ 50000000 |
Definition at line 95 of file spi-topcliff-pch.c.
| #define PCH_DMA_TRANS_SIZE 12 |
Definition at line 114 of file spi-topcliff-pch.c.
| #define PCH_MAX_BAUDRATE 5000000 |
Definition at line 55 of file spi-topcliff-pch.c.
| #define PCH_MAX_CS 0xFF |
Definition at line 65 of file spi-topcliff-pch.c.
| #define PCH_MAX_FIFO_DEPTH 16 |
Definition at line 56 of file spi-topcliff-pch.c.
| #define PCH_MAX_SPBR 1023 |
Definition at line 96 of file spi-topcliff-pch.c.
| #define PCH_READABLE | ( | x | ) | (((x) & PCH_SPSR_RFD)>>11) |
Definition at line 47 of file spi-topcliff-pch.c.
| #define PCH_RX_THOLD 7 |
Definition at line 50 of file spi-topcliff-pch.c.
| #define PCH_RX_THOLD_MAX 15 |
Definition at line 51 of file spi-topcliff-pch.c.
| #define PCH_SLEEP_TIME 10 |
Definition at line 60 of file spi-topcliff-pch.c.
| #define PCH_SPBRR 0x04 /* SPI baud rate register */ |
Definition at line 36 of file spi-topcliff-pch.c.
| #define PCH_SPCR 0x00 /* SPI control register */ |
Definition at line 35 of file spi-topcliff-pch.c.
| #define PCH_SPDRR 0x10 /* SPI read data register */ |
Definition at line 39 of file spi-topcliff-pch.c.
| #define PCH_SPDWR 0x0C /* SPI write data register */ |
Definition at line 38 of file spi-topcliff-pch.c.
| #define PCH_SPI_MAX_DEV 2 |
Definition at line 111 of file spi-topcliff-pch.c.
| #define pch_spi_pd_resume NULL |
Definition at line 1613 of file spi-topcliff-pch.c.
| #define pch_spi_pd_suspend NULL |
Definition at line 1612 of file spi-topcliff-pch.c.
| #define pch_spi_resume NULL |
Definition at line 1771 of file spi-topcliff-pch.c.
| #define pch_spi_suspend NULL |
Definition at line 1770 of file spi-topcliff-pch.c.
| #define PCH_SPSR 0x08 /* SPI status register */ |
Definition at line 37 of file spi-topcliff-pch.c.
| #define PCH_SPSR_RFD 0x0000F800 |
Definition at line 45 of file spi-topcliff-pch.c.
| #define PCH_SPSR_TFD 0x000007C0 |
Definition at line 44 of file spi-topcliff-pch.c.
| #define PCH_SRST 0x1C /* SPI reset register */ |
Definition at line 41 of file spi-topcliff-pch.c.
| #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */ |
Definition at line 40 of file spi-topcliff-pch.c.
| #define PCH_TX_THOLD 2 |
Definition at line 53 of file spi-topcliff-pch.c.
| #define PCH_WRITABLE | ( | x | ) | (((x) & PCH_SPSR_TFD)>>6) |
Definition at line 48 of file spi-topcliff-pch.c.
| #define PCI_DEVICE_ID_GE_SPI 0x8816 |
Definition at line 66 of file spi-topcliff-pch.c.
| #define PCI_DEVICE_ID_ML7213_SPI 0x802c |
Definition at line 100 of file spi-topcliff-pch.c.
| #define PCI_DEVICE_ID_ML7223_SPI 0x800F |
Definition at line 101 of file spi-topcliff-pch.c.
| #define PCI_DEVICE_ID_ML7831_SPI 0x8816 |
Definition at line 102 of file spi-topcliff-pch.c.
| #define PCI_VENDOR_ID_ROHM 0x10DB |
Definition at line 99 of file spi-topcliff-pch.c.
| #define SPBRR_SIZE_BIT (1 << 10) |
Definition at line 83 of file spi-topcliff-pch.c.
| #define SPCR_CPHA_BIT (1 << 5) |
Definition at line 71 of file spi-topcliff-pch.c.
| #define SPCR_CPOL_BIT (1 << 6) |
Definition at line 72 of file spi-topcliff-pch.c.
| #define SPCR_FICLR_BIT (1 << 24) |
Definition at line 78 of file spi-topcliff-pch.c.
| #define SPCR_FIE_BIT (1 << 10) |
Definition at line 75 of file spi-topcliff-pch.c.
| #define SPCR_LSBF_BIT (1 << 4) |
Definition at line 70 of file spi-topcliff-pch.c.
| #define SPCR_MDFIE_BIT (1 << 12) |
Definition at line 77 of file spi-topcliff-pch.c.
| #define SPCR_MSTR_BIT (1 << 1) |
Definition at line 69 of file spi-topcliff-pch.c.
| #define SPCR_ORIE_BIT (1 << 11) |
Definition at line 76 of file spi-topcliff-pch.c.
| #define SPCR_RFIC_FIELD 20 |
Definition at line 88 of file spi-topcliff-pch.c.
| #define SPCR_RFIE_BIT (1 << 9) |
Definition at line 74 of file spi-topcliff-pch.c.
| #define SPCR_SPE_BIT (1 << 0) |
Definition at line 68 of file spi-topcliff-pch.c.
| #define SPCR_TFIC_FIELD 16 |
Definition at line 89 of file spi-topcliff-pch.c.
| #define SPCR_TFIE_BIT (1 << 8) |
Definition at line 73 of file spi-topcliff-pch.c.
| #define SPSR_FI_BIT (1 << 2) |
Definition at line 81 of file spi-topcliff-pch.c.
| #define SPSR_ORF_BIT (1 << 3) |
Definition at line 82 of file spi-topcliff-pch.c.
| #define SPSR_RFI_BIT (1 << 1) |
Definition at line 80 of file spi-topcliff-pch.c.
| #define SPSR_TFI_BIT (1 << 0) |
Definition at line 79 of file spi-topcliff-pch.c.
| #define SSN_HIGH 0x03U |
Definition at line 63 of file spi-topcliff-pch.c.
| #define SSN_LOW 0x02U |
Definition at line 62 of file spi-topcliff-pch.c.
| #define SSN_NO_CONTROL 0x00U |
Definition at line 64 of file spi-topcliff-pch.c.
| #define STATUS_EXITING 2 |
Definition at line 59 of file spi-topcliff-pch.c.
| #define STATUS_RUNNING 1 |
Definition at line 58 of file spi-topcliff-pch.c.
| MODULE_DESCRIPTION | ( | "Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver" | ) |
| module_exit | ( | pch_spi_exit | ) |
| module_init | ( | pch_spi_init | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
1.8.2