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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Fields | |
| unsigned int | ratio |
| u8 | speed_mode |
| u8 | mclk |
struct cs4270_mode_ratios - clock ratio tables : the ratio of MCLK to the sample rate : the Speed Mode bits to set in the Mode Control register for this ratio : the Ratio Select bits to set in the Mode Control register for this ratio
The data for this chart is taken from Table 5 of the CS4270 reference manual.
This table is used to determine how to program the Mode Control register. It is also used by cs4270_set_dai_sysclk() to tell ALSA which sampling rates the CS4270 currently supports.
is the corresponding bit pattern to be written to the MODE bits of the Mode Control Register
is the corresponding bit pattern to be wirten to the MCLK bits of the Mode Control Register.
In situations where a single ratio is represented by multiple speed modes, we favor the slowest speed. E.g, for a ratio of 128, we pick double-speed instead of quad-speed. However, the CS4270 errata states that divide-By-1.5 can cause failures, so we avoid that mode where possible.
Errata: There is an errata for the CS4270 where divide-by-1.5 does not work if Vd is 3.3V. If this effects you, select the CONFIG_SND_SOC_CS4270_VD33_ERRATA Kconfig option, and the driver will never select any sample rates that require divide-by-1.5.
1.8.2