Detailed Description

Specify port properties for a PCIe MAC.

Definition at line 40 of file drv_trio_intf.h.

Field Documentation

uint8_t allow_ep

If true, the link can be configured in PCIe endpoint mode.

Definition at line 46 of file drv_trio_intf.h.

uint8_t allow_rc

If true, the link can be configured in PCIe root complex mode.

Definition at line 43 of file drv_trio_intf.h.

uint8_t allow_sio

If true, the link can be configured in StreamIO mode.

Definition at line 49 of file drv_trio_intf.h.

uint8_t allow_x1

If true, the link is allowed to support 1-lane operation. Software will not consider it an error if the link comes up as a x1 link.

Definition at line 53 of file drv_trio_intf.h.

uint8_t allow_x2

If true, the link is allowed to support 2-lane operation. Software will not consider it an error if the link comes up as a x2 link.

Definition at line 57 of file drv_trio_intf.h.

uint8_t allow_x4

If true, the link is allowed to support 4-lane operation. Software will not consider it an error if the link comes up as a x4 link.

Definition at line 61 of file drv_trio_intf.h.

uint8_t allow_x8

If true, the link is allowed to support 8-lane operation. Software will not consider it an error if the link comes up as a x8 link.

Definition at line 65 of file drv_trio_intf.h.

uint8_t reserved

Reserved.

Definition at line 68 of file drv_trio_intf.h.

The documentation for this struct was generated from the following file: