55 nv_wr32(priv,
info.reg + 0, 0x50000610);
56 nv_mask(priv,
info.reg + 4, 0x003fffff,
57 (P << 16) | (M << 8) | N);
58 nv_wr32(priv,
info.reg + 8, fN);
61 nv_warn(priv,
"0x%08x/%dKhz unimplemented\n", type, freq);
96 *pobject = nv_object(priv);
100 priv->
base.pll_set = nva3_clock_pll_set;
109 .ctor = nva3_clock_ctor,