54 nv_wr32(pfb, 0x100244 + (i * 0x10), tile->
limit);
55 nv_wr32(pfb, 0x100248 + (i * 0x10), tile->
pitch);
56 nv_wr32(pfb, 0x100240 + (i * 0x10), tile->
addr);
69 *pobject = nv_object(priv);
79 nv_fatal(device,
"no bridge device\n");
84 pci_read_config_dword(bridge, 0x7c, &mem);
85 mib = ((mem >> 6) & 31) + 1;
87 pci_read_config_dword(bridge, 0x84, &mem);
88 mib = ((mem >> 4) & 127) + 1;
91 priv->
base.ram.type = NV_MEM_TYPE_STOLEN;
92 priv->
base.ram.size = mib * 1024 * 1024;
94 u32 cfg0 = nv_rd32(priv, 0x100200);
95 if (cfg0 & 0x00000001)
96 priv->
base.ram.type = NV_MEM_TYPE_DDR1;
98 priv->
base.ram.type = NV_MEM_TYPE_SDRAM;
100 priv->
base.ram.size = nv_rd32(priv, 0x10020c) & 0xff000000;
104 priv->
base.tile.regions = 8;
105 priv->
base.tile.init = nv10_fb_tile_init;
106 priv->
base.tile.fini = nv10_fb_tile_fini;
115 .ctor = nv10_fb_ctor,