38 int bpp = (flags & 2) ? 32 : 16;
55 tile->
zcomp |= 0x00100000;
57 tile->
zcomp |= 0x00200000;
59 tile->
zcomp |= 0x80000000;
61 tile->
zcomp |= 0x04000000;
82 nv_wr32(pfb, 0x100244 + (i * 0x10), tile->
limit);
83 nv_wr32(pfb, 0x100248 + (i * 0x10), tile->
pitch);
84 nv_wr32(pfb, 0x100240 + (i * 0x10), tile->
addr);
85 nv_wr32(pfb, 0x100300 + (i * 0x04), tile->
zcomp);
99 *pobject = nv_object(priv);
103 pbus1218 = nv_rd32(priv, 0x001218);
104 switch (pbus1218 & 0x00000300) {
105 case 0x00000000: priv->
base.ram.type = NV_MEM_TYPE_SDRAM;
break;
106 case 0x00000100: priv->
base.ram.type = NV_MEM_TYPE_DDR1;
break;
107 case 0x00000200: priv->
base.ram.type = NV_MEM_TYPE_GDDR3;
break;
108 case 0x00000300: priv->
base.ram.type = NV_MEM_TYPE_GDDR2;
break;
110 priv->
base.ram.size = nv_rd32(priv, 0x10020c) & 0xff000000;
120 priv->
base.tile.regions = 8;
121 priv->
base.tile.init = nv20_fb_tile_init;
122 priv->
base.tile.fini = nv20_fb_tile_fini;
123 priv->
base.tile.prog = nv20_fb_tile_prog;
131 .ctor = nv20_fb_ctor,