37 tile->
addr = addr | 1;
55 nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
58 return 2 * (b & 0x8 ? b - 0x10 :
b);
66 for (j = 0; j < 4; j++) {
67 int m = (l >> (8 *
i) & 0xff) + calc_bias(priv, k, i, j);
69 x |= (0x80 |
clamp(m, 0, 0x1f)) << (8 * j);
91 int n = (device->
chipset == 0x31 ? 2 : 4);
92 int l = nv_rd32(priv, 0x1003d0);
94 for (i = 0; i <
n; i++) {
95 for (j = 0; j < 3; j++)
96 nv_wr32(priv, 0x10037c + 0
xc * i + 0x4 * j,
97 calc_ref(priv, l, 0, j));
99 for (j = 0; j < 2; j++)
100 nv_wr32(priv, 0x1003ac + 0x8 * i + 0x4 * j,
101 calc_ref(priv, l, 1, j));
118 *pobject = nv_object(priv);
122 pbus1218 = nv_rd32(priv, 0x001218);
123 switch (pbus1218 & 0x00000300) {
124 case 0x00000000: priv->
base.ram.type = NV_MEM_TYPE_SDRAM;
break;
125 case 0x00000100: priv->
base.ram.type = NV_MEM_TYPE_DDR1;
break;
126 case 0x00000200: priv->
base.ram.type = NV_MEM_TYPE_GDDR3;
break;
127 case 0x00000300: priv->
base.ram.type = NV_MEM_TYPE_GDDR2;
break;
129 priv->
base.ram.size = nv_rd32(priv, 0x10020c) & 0xff000000;
132 priv->
base.tile.regions = 8;
143 .ctor = nv30_fb_ctor,
145 .init = nv30_fb_init,