38 line = nv_rd32(gpio, 0x600818) >> line;
39 return !!(line & 0x0100);
42 line = (line - 2) * 4;
43 line = nv_rd32(gpio, 0x60081c) >> line;
44 return !!(line & 0x04);
47 line = (line - 10) * 4;
48 line = nv_rd32(gpio, 0x600850) >> line;
49 return !!(line & 0x04);
64 data = (dir << 4) | out;
67 line = (line - 2) * 4;
70 data = (dir << 1) | out;
73 line = (line - 10) * 4;
76 data = (dir << 1) | out;
81 nv_mask(gpio, reg, mask << line, data << line);
86 nv10_gpio_irq_enable(
struct nouveau_gpio *gpio,
int line,
bool on)
88 u32 mask = 0x00010001 << line;
90 nv_wr32(gpio, 0x001104, mask);
91 nv_mask(gpio, 0x001144, mask, on ? mask : 0);
98 u32 intr = nv_rd32(priv, 0x001104);
99 u32 hi = (intr & 0x0000ffff) >> 0;
100 u32 lo = (intr & 0xffff0000) >> 16;
102 priv->
base.isr_run(&priv->
base, 0, hi | lo);
104 nv_wr32(priv, 0x001104, intr);
116 *pobject = nv_object(priv);
120 priv->
base.drive = nv10_gpio_drive;
121 priv->
base.sense = nv10_gpio_sense;
122 priv->
base.irq_enable = nv10_gpio_irq_enable;
123 nv_subdev(priv)->intr = nv10_gpio_intr;
144 nv_wr32(priv, 0x001140, 0x00000000);
145 nv_wr32(priv, 0x001100, 0xffffffff);
146 nv_wr32(priv, 0x001144, 0x00000000);
147 nv_wr32(priv, 0x001104, 0xffffffff);
155 nv_wr32(priv, 0x001140, 0x00000000);
156 nv_wr32(priv, 0x001144, 0x00000000);
164 .ctor = nv10_gpio_ctor,
165 .dtor = nv10_gpio_dtor,
166 .init = nv10_gpio_init,
167 .fini = nv10_gpio_fini,