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t3_cpl.h
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1 /*
2  * Copyright (c) 2004-2008 Chelsio, Inc. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses. You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  * Redistribution and use in source and binary forms, with or
11  * without modification, are permitted provided that the following
12  * conditions are met:
13  *
14  * - Redistributions of source code must retain the above
15  * copyright notice, this list of conditions and the following
16  * disclaimer.
17  *
18  * - Redistributions in binary form must reproduce the above
19  * copyright notice, this list of conditions and the following
20  * disclaimer in the documentation and/or other materials
21  * provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #ifndef T3_CPL_H
33 #define T3_CPL_H
34 
35 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
36 # include <asm/byteorder.h>
37 #endif
38 
39 enum CPL_opcode {
43  CPL_SET_TCB = 0x4,
45  CPL_GET_TCB = 0x6,
46  CPL_PCMD = 0x7,
51  CPL_TX_DATA = 0xC,
53  CPL_TX_PKT = 0xE,
62  CPL_PCMD_READ = 0x17,
63  CPL_BARRIER = 0x18,
65 
67  CPL_ERROR = 0x21,
71  CPL_PCMD_RPL = 0x25,
77  CPL_RX_PKT = 0x2B,
82 
86  CPL_ISCSI_HDR = 0x33,
88  CPL_RDMA_CQE = 0x35,
92  CPL_RX_DATA = 0x39,
93 
98 
101 
103 
104  CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
105 
111 
112  NUM_CPL_CMDS /* must be last and previous entries must be sorted */
113 };
114 
115 enum CPL_error {
132 };
133 
134 enum {
138 };
139 
140 enum {
145 };
146 
147 enum {
148  ULP_CRC_HEADER = 1 << 0,
149  ULP_CRC_DATA = 1 << 1
150 };
151 
152 enum {
155 };
156 
157 enum {
161 };
162 
163 enum { /* TX_PKT_LSO ethernet types */
168 };
169 
170 enum { /* TCP congestion control algorithms */
175 };
176 
177 enum { /* RSS hash type */
182 };
183 
184 union opcode_tid {
187 };
188 
189 #define S_OPCODE 24
190 #define V_OPCODE(x) ((x) << S_OPCODE)
191 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
192 #define G_TID(x) ((x) & 0xFFFFFF)
193 
194 #define S_QNUM 0
195 #define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF)
196 
197 #define S_HASHTYPE 22
198 #define M_HASHTYPE 0x3
199 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
200 
201 /* tid is assumed to be 24-bits */
202 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
203 
204 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
205 
206 /* extract the TID from a CPL command */
207 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
208 
209 struct tcp_options {
210  __be16 mss;
211  __u8 wsf;
212 #if defined(__LITTLE_ENDIAN_BITFIELD)
213  __u8:5;
214  __u8 ecn:1;
215  __u8 sack:1;
216  __u8 tstamp:1;
217 #else
218  __u8 tstamp:1;
219  __u8 sack:1;
221  __u8:5;
222 #endif
223 };
224 
225 struct rss_header {
227 #if defined(__LITTLE_ENDIAN_BITFIELD)
228  __u8 cpu_idx:6;
229  __u8 hash_type:2;
230 #else
233 #endif
236 };
237 
238 #ifndef CHELSIO_FW
242 };
243 
244 /* wr_hi fields */
245 #define S_WR_SGE_CREDITS 0
246 #define M_WR_SGE_CREDITS 0xFF
247 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
248 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
249 
250 #define S_WR_SGLSFLT 8
251 #define M_WR_SGLSFLT 0xFF
252 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
253 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
254 
255 #define S_WR_BCNTLFLT 16
256 #define M_WR_BCNTLFLT 0xF
257 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
258 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
259 
260 #define S_WR_DATATYPE 20
261 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
262 #define F_WR_DATATYPE V_WR_DATATYPE(1U)
263 
264 #define S_WR_COMPL 21
265 #define V_WR_COMPL(x) ((x) << S_WR_COMPL)
266 #define F_WR_COMPL V_WR_COMPL(1U)
267 
268 #define S_WR_EOP 22
269 #define V_WR_EOP(x) ((x) << S_WR_EOP)
270 #define F_WR_EOP V_WR_EOP(1U)
271 
272 #define S_WR_SOP 23
273 #define V_WR_SOP(x) ((x) << S_WR_SOP)
274 #define F_WR_SOP V_WR_SOP(1U)
275 
276 #define S_WR_OP 24
277 #define M_WR_OP 0xFF
278 #define V_WR_OP(x) ((x) << S_WR_OP)
279 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
280 
281 /* wr_lo fields */
282 #define S_WR_LEN 0
283 #define M_WR_LEN 0xFF
284 #define V_WR_LEN(x) ((x) << S_WR_LEN)
285 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
286 
287 #define S_WR_TID 8
288 #define M_WR_TID 0xFFFFF
289 #define V_WR_TID(x) ((x) << S_WR_TID)
290 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
291 
292 #define S_WR_CR_FLUSH 30
293 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
294 #define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U)
295 
296 #define S_WR_GEN 31
297 #define V_WR_GEN(x) ((x) << S_WR_GEN)
298 #define F_WR_GEN V_WR_GEN(1U)
299 
300 # define WR_HDR struct work_request_hdr wr
301 # define RSS_HDR
302 #else
303 # define WR_HDR
304 # define RSS_HDR struct rss_header rss_hdr;
305 #endif
306 
307 /* option 0 lower-half fields */
308 #define S_CPL_STATUS 0
309 #define M_CPL_STATUS 0xFF
310 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
311 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
312 
313 #define S_INJECT_TIMER 6
314 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
315 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
316 
317 #define S_NO_OFFLOAD 7
318 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
319 #define F_NO_OFFLOAD V_NO_OFFLOAD(1U)
320 
321 #define S_ULP_MODE 8
322 #define M_ULP_MODE 0xF
323 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
324 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
325 
326 #define S_RCV_BUFSIZ 12
327 #define M_RCV_BUFSIZ 0x3FFF
328 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
329 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
330 
331 #define S_TOS 26
332 #define M_TOS 0x3F
333 #define V_TOS(x) ((x) << S_TOS)
334 #define G_TOS(x) (((x) >> S_TOS) & M_TOS)
335 
336 /* option 0 upper-half fields */
337 #define S_DELACK 0
338 #define V_DELACK(x) ((x) << S_DELACK)
339 #define F_DELACK V_DELACK(1U)
340 
341 #define S_NO_CONG 1
342 #define V_NO_CONG(x) ((x) << S_NO_CONG)
343 #define F_NO_CONG V_NO_CONG(1U)
344 
345 #define S_SRC_MAC_SEL 2
346 #define M_SRC_MAC_SEL 0x3
347 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
348 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
349 
350 #define S_L2T_IDX 4
351 #define M_L2T_IDX 0x7FF
352 #define V_L2T_IDX(x) ((x) << S_L2T_IDX)
353 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
354 
355 #define S_TX_CHANNEL 15
356 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
357 #define F_TX_CHANNEL V_TX_CHANNEL(1U)
358 
359 #define S_TCAM_BYPASS 16
360 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
361 #define F_TCAM_BYPASS V_TCAM_BYPASS(1U)
362 
363 #define S_NAGLE 17
364 #define V_NAGLE(x) ((x) << S_NAGLE)
365 #define F_NAGLE V_NAGLE(1U)
366 
367 #define S_WND_SCALE 18
368 #define M_WND_SCALE 0xF
369 #define V_WND_SCALE(x) ((x) << S_WND_SCALE)
370 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
371 
372 #define S_KEEP_ALIVE 22
373 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
374 #define F_KEEP_ALIVE V_KEEP_ALIVE(1U)
375 
376 #define S_MAX_RETRANS 23
377 #define M_MAX_RETRANS 0xF
378 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
379 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
380 
381 #define S_MAX_RETRANS_OVERRIDE 27
382 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
383 #define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U)
384 
385 #define S_MSS_IDX 28
386 #define M_MSS_IDX 0xF
387 #define V_MSS_IDX(x) ((x) << S_MSS_IDX)
388 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
389 
390 /* option 1 fields */
391 #define S_RSS_ENABLE 0
392 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
393 #define F_RSS_ENABLE V_RSS_ENABLE(1U)
394 
395 #define S_RSS_MASK_LEN 1
396 #define M_RSS_MASK_LEN 0x7
397 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
398 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
399 
400 #define S_CPU_IDX 4
401 #define M_CPU_IDX 0x3F
402 #define V_CPU_IDX(x) ((x) << S_CPU_IDX)
403 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
404 
405 #define S_MAC_MATCH_VALID 18
406 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
407 #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
408 
409 #define S_CONN_POLICY 19
410 #define M_CONN_POLICY 0x3
411 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
412 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
413 
414 #define S_SYN_DEFENSE 21
415 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
416 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
417 
418 #define S_VLAN_PRI 22
419 #define M_VLAN_PRI 0x3
420 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
421 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
422 
423 #define S_VLAN_PRI_VALID 24
424 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
425 #define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U)
426 
427 #define S_PKT_TYPE 25
428 #define M_PKT_TYPE 0x3
429 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
430 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
431 
432 #define S_MAC_MATCH 27
433 #define M_MAC_MATCH 0x1F
434 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
435 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
436 
437 /* option 2 fields */
438 #define S_CPU_INDEX 0
439 #define M_CPU_INDEX 0x7F
440 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
441 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
442 
443 #define S_CPU_INDEX_VALID 7
444 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
445 #define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U)
446 
447 #define S_RX_COALESCE 8
448 #define M_RX_COALESCE 0x3
449 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
450 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
451 
452 #define S_RX_COALESCE_VALID 10
453 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
454 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
455 
456 #define S_CONG_CONTROL_FLAVOR 11
457 #define M_CONG_CONTROL_FLAVOR 0x3
458 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
459 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
460 
461 #define S_PACING_FLAVOR 13
462 #define M_PACING_FLAVOR 0x3
463 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
464 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
465 
466 #define S_FLAVORS_VALID 15
467 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
468 #define F_FLAVORS_VALID V_FLAVORS_VALID(1U)
469 
470 #define S_RX_FC_DISABLE 16
471 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
472 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
473 
474 #define S_RX_FC_VALID 17
475 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
476 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
477 
478 struct cpl_pass_open_req {
480  union opcode_tid ot;
489 };
490 
491 struct cpl_pass_open_rpl {
499 };
500 
501 struct cpl_pass_establish {
512 };
513 
514 /* cpl_pass_establish.tos_tid fields */
515 #define S_PASS_OPEN_TID 0
516 #define M_PASS_OPEN_TID 0xFFFFFF
517 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
518 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
519 
520 #define S_PASS_OPEN_TOS 24
521 #define M_PASS_OPEN_TOS 0xFF
522 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
523 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
524 
525 /* cpl_pass_establish.l2t_idx fields */
526 #define S_L2T_IDX16 5
527 #define M_L2T_IDX16 0x7FF
528 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
529 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
530 
531 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
532 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
533 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
534 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
535 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
536 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
537 
538 struct cpl_pass_accept_req {
545  struct tcp_options tcp_options;
549 #if defined(__LITTLE_ENDIAN_BITFIELD)
550  __u8:3;
551  __u8 addr_idx:3;
552  __u8 port_idx:1;
553  __u8 exact_match:1;
554 #else
558  __u8:3;
559 #endif
563 };
564 
565 struct cpl_pass_accept_rpl {
567  union opcode_tid ot;
573 };
574 
575 struct cpl_act_open_req {
577  union opcode_tid ot;
586 };
587 
588 /* cpl_act_open_req.params fields */
589 #define S_AOPEN_VLAN_PRI 9
590 #define M_AOPEN_VLAN_PRI 0x3
591 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
592 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
593 
594 #define S_AOPEN_VLAN_PRI_VALID 11
595 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
596 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U)
597 
598 #define S_AOPEN_PKT_TYPE 12
599 #define M_AOPEN_PKT_TYPE 0x3
600 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
601 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
602 
603 #define S_AOPEN_MAC_MATCH 14
604 #define M_AOPEN_MAC_MATCH 0x1F
605 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
606 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
607 
608 #define S_AOPEN_MAC_MATCH_VALID 19
609 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
610 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U)
611 
612 #define S_AOPEN_IFF_VLAN 20
613 #define M_AOPEN_IFF_VLAN 0xFFF
614 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
615 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
616 
617 struct cpl_act_open_rpl {
624  __u8 rsvd[3];
626 };
627 
628 struct cpl_act_establish {
639 };
640 
641 struct cpl_get_tcb {
643  union opcode_tid ot;
646 };
647 
648 struct cpl_get_tcb_rpl {
653 };
654 
655 struct cpl_set_tcb {
657  union opcode_tid ot;
661 };
662 
663 /* cpl_set_tcb.reply fields */
664 #define S_NO_REPLY 7
665 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
666 #define F_NO_REPLY V_NO_REPLY(1U)
667 
668 struct cpl_set_tcb_field {
670  union opcode_tid ot;
676 };
677 
678 struct cpl_set_tcb_rpl {
680  __u8 rsvd[3];
682 };
683 
684 struct cpl_pcmd {
686  union opcode_tid ot;
687  __u8 rsvd[3];
688 #if defined(__LITTLE_ENDIAN_BITFIELD)
689  __u8 src:1;
690  __u8 bundle:1;
691  __u8 channel:1;
692  __u8:5;
693 #else
694  __u8:5;
698 #endif
700 };
701 
707 };
708 
709 struct cpl_close_con_req {
711  union opcode_tid ot;
713 };
714 
715 struct cpl_close_con_rpl {
717  __u8 rsvd[3];
721 };
722 
723 struct cpl_close_listserv_req {
725  union opcode_tid ot;
729 };
730 
731 struct cpl_close_listserv_rpl {
733  __u8 rsvd[3];
735 };
736 
743 };
744 
745 struct cpl_abort_req {
747  union opcode_tid ot;
752 };
753 
760 };
761 
762 struct cpl_abort_rpl {
764  union opcode_tid ot;
769 };
770 
771 struct cpl_peer_close {
774 };
775 
776 struct tx_data_wr {
783 };
784 
785 /* tx_data_wr.flags fields */
786 #define S_TX_ACK_PAGES 21
787 #define M_TX_ACK_PAGES 0x7
788 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
789 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
790 
791 /* tx_data_wr.param fields */
792 #define S_TX_PORT 0
793 #define M_TX_PORT 0x7
794 #define V_TX_PORT(x) ((x) << S_TX_PORT)
795 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
796 
797 #define S_TX_MSS 4
798 #define M_TX_MSS 0xF
799 #define V_TX_MSS(x) ((x) << S_TX_MSS)
800 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
801 
802 #define S_TX_QOS 8
803 #define M_TX_QOS 0xFF
804 #define V_TX_QOS(x) ((x) << S_TX_QOS)
805 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
806 
807 #define S_TX_SNDBUF 16
808 #define M_TX_SNDBUF 0xFFFF
809 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
810 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
811 
812 struct cpl_tx_data {
813  union opcode_tid ot;
818 };
819 
820 /* cpl_tx_data.flags fields */
821 #define S_TX_ULP_SUBMODE 6
822 #define M_TX_ULP_SUBMODE 0xF
823 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
824 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
825 
826 #define S_TX_ULP_MODE 10
827 #define M_TX_ULP_MODE 0xF
828 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
829 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
830 
831 #define S_TX_SHOVE 14
832 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
833 #define F_TX_SHOVE V_TX_SHOVE(1U)
834 
835 #define S_TX_MORE 15
836 #define V_TX_MORE(x) ((x) << S_TX_MORE)
837 #define F_TX_MORE V_TX_MORE(1U)
838 
839 /* additional tx_data_wr.flags fields */
840 #define S_TX_CPU_IDX 0
841 #define M_TX_CPU_IDX 0x3F
842 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
843 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
844 
845 #define S_TX_URG 16
846 #define V_TX_URG(x) ((x) << S_TX_URG)
847 #define F_TX_URG V_TX_URG(1U)
848 
849 #define S_TX_CLOSE 17
850 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
851 #define F_TX_CLOSE V_TX_CLOSE(1U)
852 
853 #define S_TX_INIT 18
854 #define V_TX_INIT(x) ((x) << S_TX_INIT)
855 #define F_TX_INIT V_TX_INIT(1U)
856 
857 #define S_TX_IMM_ACK 19
858 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
859 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
860 
861 #define S_TX_IMM_DMA 20
862 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
863 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
864 
865 struct cpl_tx_data_ack {
868 };
869 
870 struct cpl_wr_ack {
876 };
877 
880  __u8 rsvd[3];
882 };
883 
888  __u8 rsvd[7];
895 };
896 
905 };
906 
907 /* cpl_iscsi_hdr.pdu_len_ddp fields */
908 #define S_ISCSI_PDU_LEN 0
909 #define M_ISCSI_PDU_LEN 0x7FFF
910 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
911 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
912 
913 #define S_ISCSI_DDP 15
914 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
915 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
916 
917 struct cpl_rx_data {
923 #if defined(__LITTLE_ENDIAN_BITFIELD)
924  __u8 dack_mode:2;
925  __u8 psh:1;
926  __u8 heartbeat:1;
927  __u8:4;
928 #else
929  __u8:4;
933 #endif
935 };
936 
937 struct cpl_rx_data_ack {
939  union opcode_tid ot;
941 };
942 
943 /* cpl_rx_data_ack.ack_seq fields */
944 #define S_RX_CREDITS 0
945 #define M_RX_CREDITS 0x7FFFFFF
946 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
947 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
948 
949 #define S_RX_MODULATE 27
950 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
951 #define F_RX_MODULATE V_RX_MODULATE(1U)
952 
953 #define S_RX_FORCE_ACK 28
954 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
955 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
956 
957 #define S_RX_DACK_MODE 29
958 #define M_RX_DACK_MODE 0x3
959 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
960 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
961 
962 #define S_RX_DACK_CHANGE 31
963 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
964 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
965 
969 };
970 
974 };
975 
976 struct cpl_rx_data_ddp {
981  union {
984  };
987 };
988 
989 /* cpl_rx_data_ddp.ddpvld_status fields */
990 #define S_DDP_STATUS 0
991 #define M_DDP_STATUS 0xFF
992 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
993 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
994 
995 #define S_DDP_VALID 15
996 #define M_DDP_VALID 0x1FFFF
997 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
998 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
999 
1000 #define S_DDP_PPOD_MISMATCH 15
1001 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1002 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1003 
1004 #define S_DDP_PDU 16
1005 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1006 #define F_DDP_PDU V_DDP_PDU(1U)
1007 
1008 #define S_DDP_LLIMIT_ERR 17
1009 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1010 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1011 
1012 #define S_DDP_PPOD_PARITY_ERR 18
1013 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1014 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1015 
1016 #define S_DDP_PADDING_ERR 19
1017 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1018 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1019 
1020 #define S_DDP_HDRCRC_ERR 20
1021 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1022 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1023 
1024 #define S_DDP_DATACRC_ERR 21
1025 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1026 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1027 
1028 #define S_DDP_INVALID_TAG 22
1029 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1030 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1031 
1032 #define S_DDP_ULIMIT_ERR 23
1033 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1034 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1035 
1036 #define S_DDP_OFFSET_ERR 24
1037 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1038 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1039 
1040 #define S_DDP_COLOR_ERR 25
1041 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1042 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1043 
1044 #define S_DDP_TID_MISMATCH 26
1045 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1046 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1047 
1048 #define S_DDP_INVALID_PPOD 27
1049 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1050 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1051 
1052 #define S_DDP_ULP_MODE 28
1053 #define M_DDP_ULP_MODE 0xF
1054 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1055 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1056 
1057 /* cpl_rx_data_ddp.ddp_report fields */
1058 #define S_DDP_OFFSET 0
1059 #define M_DDP_OFFSET 0x3FFFFF
1060 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1061 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1062 
1063 #define S_DDP_URG 24
1064 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1065 #define F_DDP_URG V_DDP_URG(1U)
1066 
1067 #define S_DDP_PSH 25
1068 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1069 #define F_DDP_PSH V_DDP_PSH(1U)
1070 
1071 #define S_DDP_BUF_COMPLETE 26
1072 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1073 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1074 
1075 #define S_DDP_BUF_TIMED_OUT 27
1076 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1077 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1078 
1079 #define S_DDP_BUF_IDX 28
1080 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1081 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1082 
1083 struct cpl_tx_pkt {
1087 };
1088 
1089 struct cpl_tx_pkt_lso {
1092  __be32 len;
1093 
1096 };
1097 
1098 /* cpl_tx_pkt*.cntrl fields */
1099 #define S_TXPKT_VLAN 0
1100 #define M_TXPKT_VLAN 0xFFFF
1101 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1102 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1103 
1104 #define S_TXPKT_INTF 16
1105 #define M_TXPKT_INTF 0xF
1106 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1107 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1108 
1109 #define S_TXPKT_IPCSUM_DIS 20
1110 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1111 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U)
1112 
1113 #define S_TXPKT_L4CSUM_DIS 21
1114 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1115 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U)
1116 
1117 #define S_TXPKT_VLAN_VLD 22
1118 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1119 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U)
1120 
1121 #define S_TXPKT_LOOPBACK 23
1122 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1123 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1124 
1125 #define S_TXPKT_OPCODE 24
1126 #define M_TXPKT_OPCODE 0xFF
1127 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1128 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1129 
1130 /* cpl_tx_pkt_lso.lso_info fields */
1131 #define S_LSO_MSS 0
1132 #define M_LSO_MSS 0x3FFF
1133 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1134 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1135 
1136 #define S_LSO_ETH_TYPE 14
1137 #define M_LSO_ETH_TYPE 0x3
1138 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1139 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1140 
1141 #define S_LSO_TCPHDR_WORDS 16
1142 #define M_LSO_TCPHDR_WORDS 0xF
1143 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1144 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1145 
1146 #define S_LSO_IPHDR_WORDS 20
1147 #define M_LSO_IPHDR_WORDS 0xF
1148 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1149 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1150 
1151 #define S_LSO_IPV6 24
1152 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1153 #define F_LSO_IPV6 V_LSO_IPV6(1U)
1154 
1156 #ifdef CHELSIO_FW
1157  __u8 rss_opcode;
1158 #if defined(__LITTLE_ENDIAN_BITFIELD)
1159  __u8 err:1;
1160  __u8:7;
1161 #else
1162  __u8:7;
1163  __u8 err:1;
1164 #endif
1165  __u8 rsvd0;
1166 #if defined(__LITTLE_ENDIAN_BITFIELD)
1167  __u8 qid:4;
1168  __u8:4;
1169 #else
1170  __u8:4;
1171  __u8 qid:4;
1172 #endif
1173  __be32 tstamp;
1174 #endif /* CHELSIO_FW */
1175 
1177 #if defined(__LITTLE_ENDIAN_BITFIELD)
1178  __u8 iff:4;
1179  __u8:4;
1180 #else
1181  __u8:4;
1183 #endif
1186 };
1187 
1188 struct cpl_rx_pkt {
1190 #if defined(__LITTLE_ENDIAN_BITFIELD)
1191  __u8 iff:4;
1192  __u8 csum_valid:1;
1193  __u8 ipmi_pkt:1;
1194  __u8 vlan_valid:1;
1195  __u8 fragment:1;
1196 #else
1202 #endif
1206 };
1207 
1208 struct cpl_l2t_write_req {
1210  union opcode_tid ot;
1214 };
1215 
1216 /* cpl_l2t_write_req.params fields */
1217 #define S_L2T_W_IDX 0
1218 #define M_L2T_W_IDX 0x7FF
1219 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1220 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1221 
1222 #define S_L2T_W_VLAN 11
1223 #define M_L2T_W_VLAN 0xFFF
1224 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1225 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1226 
1227 #define S_L2T_W_IFF 23
1228 #define M_L2T_W_IFF 0xF
1229 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1230 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1231 
1232 #define S_L2T_W_PRIO 27
1233 #define M_L2T_W_PRIO 0x7
1234 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1235 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1236 
1237 struct cpl_l2t_write_rpl {
1241 };
1242 
1243 struct cpl_l2t_read_req {
1245  union opcode_tid ot;
1248 };
1249 
1250 struct cpl_l2t_read_rpl {
1255 };
1256 
1257 /* cpl_l2t_read_rpl.params fields */
1258 #define S_L2T_R_PRIO 0
1259 #define M_L2T_R_PRIO 0x7
1260 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1261 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1262 
1263 #define S_L2T_R_VLAN 8
1264 #define M_L2T_R_VLAN 0xFFF
1265 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1266 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1267 
1268 #define S_L2T_R_IFF 20
1269 #define M_L2T_R_IFF 0xF
1270 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1271 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1272 
1273 #define S_L2T_STATUS 24
1274 #define M_L2T_STATUS 0xFF
1275 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1276 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1277 
1278 struct cpl_smt_write_req {
1280  union opcode_tid ot;
1282 #if defined(__LITTLE_ENDIAN_BITFIELD)
1283  __u8 mtu_idx:4;
1284  __u8 iff:4;
1285 #else
1288 #endif
1294 };
1295 
1296 struct cpl_smt_write_rpl {
1300 };
1301 
1302 struct cpl_smt_read_req {
1304  union opcode_tid ot;
1306 #if defined(__LITTLE_ENDIAN_BITFIELD)
1307  __u8:4;
1308  __u8 iff:4;
1309 #else
1311  __u8:4;
1312 #endif
1314 };
1315 
1316 struct cpl_smt_read_rpl {
1319 #if defined(__LITTLE_ENDIAN_BITFIELD)
1320  __u8 mtu_idx:4;
1321  __u8:4;
1322 #else
1323  __u8:4;
1325 #endif
1331 };
1332 
1333 struct cpl_rte_delete_req {
1335  union opcode_tid ot;
1337 };
1338 
1339 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1340 #define S_RTE_REQ_LUT_IX 8
1341 #define M_RTE_REQ_LUT_IX 0x7FF
1342 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1343 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1344 
1345 #define S_RTE_REQ_LUT_BASE 19
1346 #define M_RTE_REQ_LUT_BASE 0x7FF
1347 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1348 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1349 
1350 #define S_RTE_READ_REQ_SELECT 31
1351 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1352 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1353 
1354 struct cpl_rte_delete_rpl {
1358 };
1359 
1360 struct cpl_rte_write_req {
1362  union opcode_tid ot;
1363 #if defined(__LITTLE_ENDIAN_BITFIELD)
1364  __u8:6;
1365  __u8 write_tcam:1;
1366  __u8 write_l2t_lut:1;
1367 #else
1370  __u8:6;
1371 #endif
1378 };
1379 
1380 /* cpl_rte_write_req.lut_params fields */
1381 #define S_RTE_WRITE_REQ_LUT_IX 10
1382 #define M_RTE_WRITE_REQ_LUT_IX 0x7FF
1383 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1384 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1385 
1386 #define S_RTE_WRITE_REQ_LUT_BASE 21
1387 #define M_RTE_WRITE_REQ_LUT_BASE 0x7FF
1388 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1389 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1390 
1391 struct cpl_rte_write_rpl {
1395 };
1396 
1397 struct cpl_rte_read_req {
1399  union opcode_tid ot;
1401 };
1402 
1403 struct cpl_rte_read_rpl {
1408 #if defined(__LITTLE_ENDIAN_BITFIELD)
1409  __u8:7;
1410  __u8 select:1;
1411 #else
1413  __u8:7;
1414 #endif
1417 };
1418 
1423 };
1424 
1425 struct cpl_barrier {
1429 };
1430 
1433  __u8 rsvd[15];
1434 };
1435 
1437 #ifdef CHELSIO_FW
1438  __u8 opcode;
1439  __u8 rsvd[2];
1440 #if defined(__LITTLE_ENDIAN_BITFIELD)
1441  __u8 rspq:3;
1442  __u8:5;
1443 #else
1444  __u8:5;
1445  __u8 rspq:3;
1446 #endif
1447  __be32 tid_len;
1448 #endif
1452 };
1453 
1454 /* cpl_rdma_terminate.tid_len fields */
1455 #define S_FLIT_CNT 0
1456 #define M_FLIT_CNT 0xFF
1457 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1458 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1459 
1460 #define S_TERM_TID 8
1461 #define M_TERM_TID 0xFFFFF
1462 #define V_TERM_TID(x) ((x) << S_TERM_TID)
1463 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1464 
1465 /* ULP_TX opcodes */
1466 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1467 
1468 #define S_ULPTX_CMD 28
1469 #define M_ULPTX_CMD 0xF
1470 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1471 
1472 #define S_ULPTX_NFLITS 0
1473 #define M_ULPTX_NFLITS 0xFF
1474 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1475 
1476 struct ulp_mem_io {
1480 };
1481 
1482 /* ulp_mem_io.cmd_lock_addr fields */
1483 #define S_ULP_MEMIO_ADDR 0
1484 #define M_ULP_MEMIO_ADDR 0x7FFFFFF
1485 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1486 #define S_ULP_MEMIO_LOCK 27
1487 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1488 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1489 
1490 /* ulp_mem_io.len fields */
1491 #define S_ULP_MEMIO_DATA_LEN 28
1492 #define M_ULP_MEMIO_DATA_LEN 0xF
1493 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1494 
1495 #endif /* T3_CPL_H */