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Macros
t4_regs.h File Reference

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Macros

#define MYPF_BASE   0x1b000
 
#define MYPF_REG(reg_addr)   (MYPF_BASE + (reg_addr))
 
#define PF0_BASE   0x1e000
 
#define PF0_REG(reg_addr)   (PF0_BASE + (reg_addr))
 
#define PF_STRIDE   0x400
 
#define PF_BASE(idx)   (PF0_BASE + (idx) * PF_STRIDE)
 
#define PF_REG(idx, reg)   (PF_BASE(idx) + (reg))
 
#define MYPORT_BASE   0x1c000
 
#define MYPORT_REG(reg_addr)   (MYPORT_BASE + (reg_addr))
 
#define PORT0_BASE   0x20000
 
#define PORT0_REG(reg_addr)   (PORT0_BASE + (reg_addr))
 
#define PORT_STRIDE   0x2000
 
#define PORT_BASE(idx)   (PORT0_BASE + (idx) * PORT_STRIDE)
 
#define PORT_REG(idx, reg)   (PORT_BASE(idx) + (reg))
 
#define EDC_STRIDE   (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
 
#define EDC_REG(reg, idx)   (reg + EDC_STRIDE * idx)
 
#define PCIE_MEM_ACCESS_REG(reg_addr, idx)   ((reg_addr) + (idx) * 8)
 
#define PCIE_MAILBOX_REG(reg_addr, idx)   ((reg_addr) + (idx) * 8)
 
#define MC_BIST_STATUS_REG(reg_addr, idx)   ((reg_addr) + (idx) * 4)
 
#define EDC_BIST_STATUS_REG(reg_addr, idx)   ((reg_addr) + (idx) * 4)
 
#define SGE_PF_KDOORBELL   0x0
 
#define QID_MASK   0xffff8000U
 
#define QID_SHIFT   15
 
#define QID(x)   ((x) << QID_SHIFT)
 
#define DBPRIO   0x00004000U
 
#define PIDX_MASK   0x00003fffU
 
#define PIDX_SHIFT   0
 
#define PIDX(x)   ((x) << PIDX_SHIFT)
 
#define SGE_PF_GTS   0x4
 
#define INGRESSQID_MASK   0xffff0000U
 
#define INGRESSQID_SHIFT   16
 
#define INGRESSQID(x)   ((x) << INGRESSQID_SHIFT)
 
#define TIMERREG_MASK   0x0000e000U
 
#define TIMERREG_SHIFT   13
 
#define TIMERREG(x)   ((x) << TIMERREG_SHIFT)
 
#define SEINTARM_MASK   0x00001000U
 
#define SEINTARM_SHIFT   12
 
#define SEINTARM(x)   ((x) << SEINTARM_SHIFT)
 
#define CIDXINC_MASK   0x00000fffU
 
#define CIDXINC_SHIFT   0
 
#define CIDXINC(x)   ((x) << CIDXINC_SHIFT)
 
#define X_RXPKTCPLMODE_SPLIT   1
 
#define X_INGPADBOUNDARY_SHIFT   5
 
#define SGE_CONTROL   0x1008
 
#define DCASYSTYPE   0x00080000U
 
#define RXPKTCPLMODE_MASK   0x00040000U
 
#define RXPKTCPLMODE_SHIFT   18
 
#define RXPKTCPLMODE(x)   ((x) << RXPKTCPLMODE_SHIFT)
 
#define EGRSTATUSPAGESIZE_MASK   0x00020000U
 
#define EGRSTATUSPAGESIZE_SHIFT   17
 
#define EGRSTATUSPAGESIZE(x)   ((x) << EGRSTATUSPAGESIZE_SHIFT)
 
#define PKTSHIFT_MASK   0x00001c00U
 
#define PKTSHIFT_SHIFT   10
 
#define PKTSHIFT(x)   ((x) << PKTSHIFT_SHIFT)
 
#define PKTSHIFT_GET(x)   (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT)
 
#define INGPCIEBOUNDARY_MASK   0x00000380U
 
#define INGPCIEBOUNDARY_SHIFT   7
 
#define INGPCIEBOUNDARY(x)   ((x) << INGPCIEBOUNDARY_SHIFT)
 
#define INGPADBOUNDARY_MASK   0x00000070U
 
#define INGPADBOUNDARY_SHIFT   4
 
#define INGPADBOUNDARY(x)   ((x) << INGPADBOUNDARY_SHIFT)
 
#define INGPADBOUNDARY_GET(x)
 
#define EGRPCIEBOUNDARY_MASK   0x0000000eU
 
#define EGRPCIEBOUNDARY_SHIFT   1
 
#define EGRPCIEBOUNDARY(x)   ((x) << EGRPCIEBOUNDARY_SHIFT)
 
#define GLOBALENABLE   0x00000001U
 
#define SGE_HOST_PAGE_SIZE   0x100c
 
#define HOSTPAGESIZEPF7_MASK   0x0000000fU
 
#define HOSTPAGESIZEPF7_SHIFT   28
 
#define HOSTPAGESIZEPF7(x)   ((x) << HOSTPAGESIZEPF7_SHIFT)
 
#define HOSTPAGESIZEPF6_MASK   0x0000000fU
 
#define HOSTPAGESIZEPF6_SHIFT   24
 
#define HOSTPAGESIZEPF6(x)   ((x) << HOSTPAGESIZEPF6_SHIFT)
 
#define HOSTPAGESIZEPF5_MASK   0x0000000fU
 
#define HOSTPAGESIZEPF5_SHIFT   20
 
#define HOSTPAGESIZEPF5(x)   ((x) << HOSTPAGESIZEPF5_SHIFT)
 
#define HOSTPAGESIZEPF4_MASK   0x0000000fU
 
#define HOSTPAGESIZEPF4_SHIFT   16
 
#define HOSTPAGESIZEPF4(x)   ((x) << HOSTPAGESIZEPF4_SHIFT)
 
#define HOSTPAGESIZEPF3_MASK   0x0000000fU
 
#define HOSTPAGESIZEPF3_SHIFT   12
 
#define HOSTPAGESIZEPF3(x)   ((x) << HOSTPAGESIZEPF3_SHIFT)
 
#define HOSTPAGESIZEPF2_MASK   0x0000000fU
 
#define HOSTPAGESIZEPF2_SHIFT   8
 
#define HOSTPAGESIZEPF2(x)   ((x) << HOSTPAGESIZEPF2_SHIFT)
 
#define HOSTPAGESIZEPF1_MASK   0x0000000fU
 
#define HOSTPAGESIZEPF1_SHIFT   4
 
#define HOSTPAGESIZEPF1(x)   ((x) << HOSTPAGESIZEPF1_SHIFT)
 
#define HOSTPAGESIZEPF0_MASK   0x0000000fU
 
#define HOSTPAGESIZEPF0_SHIFT   0
 
#define HOSTPAGESIZEPF0(x)   ((x) << HOSTPAGESIZEPF0_SHIFT)
 
#define SGE_EGRESS_QUEUES_PER_PAGE_PF   0x1010
 
#define QUEUESPERPAGEPF0_MASK   0x0000000fU
 
#define QUEUESPERPAGEPF0_GET(x)   ((x) & QUEUESPERPAGEPF0_MASK)
 
#define SGE_INT_CAUSE1   0x1024
 
#define SGE_INT_CAUSE2   0x1030
 
#define SGE_INT_CAUSE3   0x103c
 
#define ERR_FLM_DBP   0x80000000U
 
#define ERR_FLM_IDMA1   0x40000000U
 
#define ERR_FLM_IDMA0   0x20000000U
 
#define ERR_FLM_HINT   0x10000000U
 
#define ERR_PCIE_ERROR3   0x08000000U
 
#define ERR_PCIE_ERROR2   0x04000000U
 
#define ERR_PCIE_ERROR1   0x02000000U
 
#define ERR_PCIE_ERROR0   0x01000000U
 
#define ERR_TIMER_ABOVE_MAX_QID   0x00800000U
 
#define ERR_CPL_EXCEED_IQE_SIZE   0x00400000U
 
#define ERR_INVALID_CIDX_INC   0x00200000U
 
#define ERR_ITP_TIME_PAUSED   0x00100000U
 
#define ERR_CPL_OPCODE_0   0x00080000U
 
#define ERR_DROPPED_DB   0x00040000U
 
#define ERR_DATA_CPL_ON_HIGH_QID1   0x00020000U
 
#define ERR_DATA_CPL_ON_HIGH_QID0   0x00010000U
 
#define ERR_BAD_DB_PIDX3   0x00008000U
 
#define ERR_BAD_DB_PIDX2   0x00004000U
 
#define ERR_BAD_DB_PIDX1   0x00002000U
 
#define ERR_BAD_DB_PIDX0   0x00001000U
 
#define ERR_ING_PCIE_CHAN   0x00000800U
 
#define ERR_ING_CTXT_PRIO   0x00000400U
 
#define ERR_EGR_CTXT_PRIO   0x00000200U
 
#define DBFIFO_HP_INT   0x00000100U
 
#define DBFIFO_LP_INT   0x00000080U
 
#define REG_ADDRESS_ERR   0x00000040U
 
#define INGRESS_SIZE_ERR   0x00000020U
 
#define EGRESS_SIZE_ERR   0x00000010U
 
#define ERR_INV_CTXT3   0x00000008U
 
#define ERR_INV_CTXT2   0x00000004U
 
#define ERR_INV_CTXT1   0x00000002U
 
#define ERR_INV_CTXT0   0x00000001U
 
#define SGE_INT_ENABLE3   0x1040
 
#define SGE_FL_BUFFER_SIZE0   0x1044
 
#define SGE_FL_BUFFER_SIZE1   0x1048
 
#define SGE_FL_BUFFER_SIZE2   0x104c
 
#define SGE_FL_BUFFER_SIZE3   0x1050
 
#define SGE_INGRESS_RX_THRESHOLD   0x10a0
 
#define THRESHOLD_0_MASK   0x3f000000U
 
#define THRESHOLD_0_SHIFT   24
 
#define THRESHOLD_0(x)   ((x) << THRESHOLD_0_SHIFT)
 
#define THRESHOLD_0_GET(x)   (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)
 
#define THRESHOLD_1_MASK   0x003f0000U
 
#define THRESHOLD_1_SHIFT   16
 
#define THRESHOLD_1(x)   ((x) << THRESHOLD_1_SHIFT)
 
#define THRESHOLD_1_GET(x)   (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)
 
#define THRESHOLD_2_MASK   0x00003f00U
 
#define THRESHOLD_2_SHIFT   8
 
#define THRESHOLD_2(x)   ((x) << THRESHOLD_2_SHIFT)
 
#define THRESHOLD_2_GET(x)   (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)
 
#define THRESHOLD_3_MASK   0x0000003fU
 
#define THRESHOLD_3_SHIFT   0
 
#define THRESHOLD_3(x)   ((x) << THRESHOLD_3_SHIFT)
 
#define THRESHOLD_3_GET(x)   (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
 
#define SGE_CONM_CTRL   0x1094
 
#define EGRTHRESHOLD_MASK   0x00003f00U
 
#define EGRTHRESHOLDshift   8
 
#define EGRTHRESHOLD(x)   ((x) << EGRTHRESHOLDshift)
 
#define EGRTHRESHOLD_GET(x)   (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
 
#define SGE_TIMER_VALUE_0_AND_1   0x10b8
 
#define TIMERVALUE0_MASK   0xffff0000U
 
#define TIMERVALUE0_SHIFT   16
 
#define TIMERVALUE0(x)   ((x) << TIMERVALUE0_SHIFT)
 
#define TIMERVALUE0_GET(x)   (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
 
#define TIMERVALUE1_MASK   0x0000ffffU
 
#define TIMERVALUE1_SHIFT   0
 
#define TIMERVALUE1(x)   ((x) << TIMERVALUE1_SHIFT)
 
#define TIMERVALUE1_GET(x)   (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
 
#define SGE_TIMER_VALUE_2_AND_3   0x10bc
 
#define TIMERVALUE2_MASK   0xffff0000U
 
#define TIMERVALUE2_SHIFT   16
 
#define TIMERVALUE2(x)   ((x) << TIMERVALUE2_SHIFT)
 
#define TIMERVALUE2_GET(x)   (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
 
#define TIMERVALUE3_MASK   0x0000ffffU
 
#define TIMERVALUE3_SHIFT   0
 
#define TIMERVALUE3(x)   ((x) << TIMERVALUE3_SHIFT)
 
#define TIMERVALUE3_GET(x)   (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
 
#define SGE_TIMER_VALUE_4_AND_5   0x10c0
 
#define TIMERVALUE4_MASK   0xffff0000U
 
#define TIMERVALUE4_SHIFT   16
 
#define TIMERVALUE4(x)   ((x) << TIMERVALUE4_SHIFT)
 
#define TIMERVALUE4_GET(x)   (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
 
#define TIMERVALUE5_MASK   0x0000ffffU
 
#define TIMERVALUE5_SHIFT   0
 
#define TIMERVALUE5(x)   ((x) << TIMERVALUE5_SHIFT)
 
#define TIMERVALUE5_GET(x)   (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
 
#define SGE_DEBUG_INDEX   0x10cc
 
#define SGE_DEBUG_DATA_HIGH   0x10d0
 
#define SGE_DEBUG_DATA_LOW   0x10d4
 
#define SGE_INGRESS_QUEUES_PER_PAGE_PF   0x10f4
 
#define S_HP_INT_THRESH   28
 
#define M_HP_INT_THRESH   0xfU
 
#define V_HP_INT_THRESH(x)   ((x) << S_HP_INT_THRESH)
 
#define M_HP_COUNT   0x7ffU
 
#define S_HP_COUNT   16
 
#define G_HP_COUNT(x)   (((x) >> S_HP_COUNT) & M_HP_COUNT)
 
#define S_LP_INT_THRESH   12
 
#define M_LP_INT_THRESH   0xfU
 
#define V_LP_INT_THRESH(x)   ((x) << S_LP_INT_THRESH)
 
#define M_LP_COUNT   0x7ffU
 
#define S_LP_COUNT   0
 
#define G_LP_COUNT(x)   (((x) >> S_LP_COUNT) & M_LP_COUNT)
 
#define A_SGE_DBFIFO_STATUS   0x10a4
 
#define S_ENABLE_DROP   13
 
#define V_ENABLE_DROP(x)   ((x) << S_ENABLE_DROP)
 
#define F_ENABLE_DROP   V_ENABLE_DROP(1U)
 
#define S_DROPPED_DB   0
 
#define V_DROPPED_DB(x)   ((x) << S_DROPPED_DB)
 
#define F_DROPPED_DB   V_DROPPED_DB(1U)
 
#define A_SGE_DOORBELL_CONTROL   0x10a8
 
#define A_SGE_CTXT_CMD   0x11fc
 
#define A_SGE_DBQ_CTXT_BADDR   0x1084
 
#define PCIE_PF_CLI   0x44
 
#define PCIE_INT_CAUSE   0x3004
 
#define UNXSPLCPLERR   0x20000000U
 
#define PCIEPINT   0x10000000U
 
#define PCIESINT   0x08000000U
 
#define RPLPERR   0x04000000U
 
#define RXWRPERR   0x02000000U
 
#define RXCPLPERR   0x01000000U
 
#define PIOTAGPERR   0x00800000U
 
#define MATAGPERR   0x00400000U
 
#define INTXCLRPERR   0x00200000U
 
#define FIDPERR   0x00100000U
 
#define CFGSNPPERR   0x00080000U
 
#define HRSPPERR   0x00040000U
 
#define HREQPERR   0x00020000U
 
#define HCNTPERR   0x00010000U
 
#define DRSPPERR   0x00008000U
 
#define DREQPERR   0x00004000U
 
#define DCNTPERR   0x00002000U
 
#define CRSPPERR   0x00001000U
 
#define CREQPERR   0x00000800U
 
#define CCNTPERR   0x00000400U
 
#define TARTAGPERR   0x00000200U
 
#define PIOREQPERR   0x00000100U
 
#define PIOCPLPERR   0x00000080U
 
#define MSIXDIPERR   0x00000040U
 
#define MSIXDATAPERR   0x00000020U
 
#define MSIXADDRHPERR   0x00000010U
 
#define MSIXADDRLPERR   0x00000008U
 
#define MSIDATAPERR   0x00000004U
 
#define MSIADDRHPERR   0x00000002U
 
#define MSIADDRLPERR   0x00000001U
 
#define PCIE_NONFAT_ERR   0x3010
 
#define PCIE_MEM_ACCESS_BASE_WIN   0x3068
 
#define PCIEOFST_MASK   0xfffffc00U
 
#define BIR_MASK   0x00000300U
 
#define BIR_SHIFT   8
 
#define BIR(x)   ((x) << BIR_SHIFT)
 
#define WINDOW_MASK   0x000000ffU
 
#define WINDOW_SHIFT   0
 
#define WINDOW(x)   ((x) << WINDOW_SHIFT)
 
#define PCIE_MEM_ACCESS_OFFSET   0x306c
 
#define PCIE_FW   0x30b8
 
#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS   0x5908
 
#define RNPP   0x80000000U
 
#define RPCP   0x20000000U
 
#define RCIP   0x08000000U
 
#define RCCP   0x04000000U
 
#define RFTP   0x00800000U
 
#define PTRP   0x00100000U
 
#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS   0x59a4
 
#define TPCP   0x40000000U
 
#define TNPP   0x20000000U
 
#define TFTP   0x10000000U
 
#define TCAP   0x08000000U
 
#define TCIP   0x04000000U
 
#define RCAP   0x02000000U
 
#define PLUP   0x00800000U
 
#define PLDN   0x00400000U
 
#define OTDD   0x00200000U
 
#define GTRP   0x00100000U
 
#define RDPE   0x00040000U
 
#define TDCE   0x00020000U
 
#define TDUE   0x00010000U
 
#define MC_INT_CAUSE   0x7518
 
#define ECC_UE_INT_CAUSE   0x00000004U
 
#define ECC_CE_INT_CAUSE   0x00000002U
 
#define PERR_INT_CAUSE   0x00000001U
 
#define MC_ECC_STATUS   0x751c
 
#define ECC_CECNT_MASK   0xffff0000U
 
#define ECC_CECNT_SHIFT   16
 
#define ECC_CECNT(x)   ((x) << ECC_CECNT_SHIFT)
 
#define ECC_CECNT_GET(x)   (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)
 
#define ECC_UECNT_MASK   0x0000ffffU
 
#define ECC_UECNT_SHIFT   0
 
#define ECC_UECNT(x)   ((x) << ECC_UECNT_SHIFT)
 
#define ECC_UECNT_GET(x)   (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)
 
#define MC_BIST_CMD   0x7600
 
#define START_BIST   0x80000000U
 
#define BIST_CMD_GAP_MASK   0x0000ff00U
 
#define BIST_CMD_GAP_SHIFT   8
 
#define BIST_CMD_GAP(x)   ((x) << BIST_CMD_GAP_SHIFT)
 
#define BIST_OPCODE_MASK   0x00000003U
 
#define BIST_OPCODE_SHIFT   0
 
#define BIST_OPCODE(x)   ((x) << BIST_OPCODE_SHIFT)
 
#define MC_BIST_CMD_ADDR   0x7604
 
#define MC_BIST_CMD_LEN   0x7608
 
#define MC_BIST_DATA_PATTERN   0x760c
 
#define BIST_DATA_TYPE_MASK   0x0000000fU
 
#define BIST_DATA_TYPE_SHIFT   0
 
#define BIST_DATA_TYPE(x)   ((x) << BIST_DATA_TYPE_SHIFT)
 
#define MC_BIST_STATUS_RDATA   0x7688
 
#define MA_EXT_MEMORY_BAR   0x77c8
 
#define EXT_MEM_SIZE_MASK   0x00000fffU
 
#define EXT_MEM_SIZE_SHIFT   0
 
#define EXT_MEM_SIZE_GET(x)   (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT)
 
#define MA_TARGET_MEM_ENABLE   0x77d8
 
#define EXT_MEM_ENABLE   0x00000004U
 
#define EDRAM1_ENABLE   0x00000002U
 
#define EDRAM0_ENABLE   0x00000001U
 
#define MA_INT_CAUSE   0x77e0
 
#define MEM_PERR_INT_CAUSE   0x00000002U
 
#define MEM_WRAP_INT_CAUSE   0x00000001U
 
#define MA_INT_WRAP_STATUS   0x77e4
 
#define MEM_WRAP_ADDRESS_MASK   0xfffffff0U
 
#define MEM_WRAP_ADDRESS_SHIFT   4
 
#define MEM_WRAP_ADDRESS_GET(x)   (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)
 
#define MEM_WRAP_CLIENT_NUM_MASK   0x0000000fU
 
#define MEM_WRAP_CLIENT_NUM_SHIFT   0
 
#define MEM_WRAP_CLIENT_NUM_GET(x)   (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
 
#define MA_PCIE_FW   0x30b8
 
#define MA_PARITY_ERROR_STATUS   0x77f4
 
#define EDC_0_BASE_ADDR   0x7900
 
#define EDC_BIST_CMD   0x7904
 
#define EDC_BIST_CMD_ADDR   0x7908
 
#define EDC_BIST_CMD_LEN   0x790c
 
#define EDC_BIST_DATA_PATTERN   0x7910
 
#define EDC_BIST_STATUS_RDATA   0x7928
 
#define EDC_INT_CAUSE   0x7978
 
#define ECC_UE_PAR   0x00000020U
 
#define ECC_CE_PAR   0x00000010U
 
#define PERR_PAR_CAUSE   0x00000008U
 
#define EDC_ECC_STATUS   0x797c
 
#define EDC_1_BASE_ADDR   0x7980
 
#define CIM_BOOT_CFG   0x7b00
 
#define BOOTADDR_MASK   0xffffff00U
 
#define UPCRST   0x1U
 
#define CIM_PF_MAILBOX_DATA   0x240
 
#define CIM_PF_MAILBOX_CTRL   0x280
 
#define MBMSGVALID   0x00000008U
 
#define MBINTREQ   0x00000004U
 
#define MBOWNER_MASK   0x00000003U
 
#define MBOWNER_SHIFT   0
 
#define MBOWNER(x)   ((x) << MBOWNER_SHIFT)
 
#define MBOWNER_GET(x)   (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
 
#define CIM_PF_HOST_INT_CAUSE   0x28c
 
#define MBMSGRDYINT   0x00080000U
 
#define CIM_HOST_INT_CAUSE   0x7b2c
 
#define TIEQOUTPARERRINT   0x00100000U
 
#define TIEQINPARERRINT   0x00080000U
 
#define MBHOSTPARERR   0x00040000U
 
#define MBUPPARERR   0x00020000U
 
#define IBQPARERR   0x0001f800U
 
#define IBQTP0PARERR   0x00010000U
 
#define IBQTP1PARERR   0x00008000U
 
#define IBQULPPARERR   0x00004000U
 
#define IBQSGELOPARERR   0x00002000U
 
#define IBQSGEHIPARERR   0x00001000U
 
#define IBQNCSIPARERR   0x00000800U
 
#define OBQPARERR   0x000007e0U
 
#define OBQULP0PARERR   0x00000400U
 
#define OBQULP1PARERR   0x00000200U
 
#define OBQULP2PARERR   0x00000100U
 
#define OBQULP3PARERR   0x00000080U
 
#define OBQSGEPARERR   0x00000040U
 
#define OBQNCSIPARERR   0x00000020U
 
#define PREFDROPINT   0x00000002U
 
#define UPACCNONZERO   0x00000001U
 
#define CIM_HOST_UPACC_INT_CAUSE   0x7b34
 
#define EEPROMWRINT   0x40000000U
 
#define TIMEOUTMAINT   0x20000000U
 
#define TIMEOUTINT   0x10000000U
 
#define RSPOVRLOOKUPINT   0x08000000U
 
#define REQOVRLOOKUPINT   0x04000000U
 
#define BLKWRPLINT   0x02000000U
 
#define BLKRDPLINT   0x01000000U
 
#define SGLWRPLINT   0x00800000U
 
#define SGLRDPLINT   0x00400000U
 
#define BLKWRCTLINT   0x00200000U
 
#define BLKRDCTLINT   0x00100000U
 
#define SGLWRCTLINT   0x00080000U
 
#define SGLRDCTLINT   0x00040000U
 
#define BLKWREEPROMINT   0x00020000U
 
#define BLKRDEEPROMINT   0x00010000U
 
#define SGLWREEPROMINT   0x00008000U
 
#define SGLRDEEPROMINT   0x00004000U
 
#define BLKWRFLASHINT   0x00002000U
 
#define BLKRDFLASHINT   0x00001000U
 
#define SGLWRFLASHINT   0x00000800U
 
#define SGLRDFLASHINT   0x00000400U
 
#define BLKWRBOOTINT   0x00000200U
 
#define BLKRDBOOTINT   0x00000100U
 
#define SGLWRBOOTINT   0x00000080U
 
#define SGLRDBOOTINT   0x00000040U
 
#define ILLWRBEINT   0x00000020U
 
#define ILLRDBEINT   0x00000010U
 
#define ILLRDINT   0x00000008U
 
#define ILLWRINT   0x00000004U
 
#define ILLTRANSINT   0x00000002U
 
#define RSVDSPACEINT   0x00000001U
 
#define TP_OUT_CONFIG   0x7d04
 
#define VLANEXTENABLE_MASK   0x0000f000U
 
#define VLANEXTENABLE_SHIFT   12
 
#define TP_GLOBAL_CONFIG   0x7d08
 
#define FIVETUPLELOOKUP_SHIFT   17
 
#define FIVETUPLELOOKUP_MASK   0x00060000U
 
#define FIVETUPLELOOKUP(x)   ((x) << FIVETUPLELOOKUP_SHIFT)
 
#define FIVETUPLELOOKUP_GET(x)
 
#define TP_PARA_REG2   0x7d68
 
#define MAXRXDATA_MASK   0xffff0000U
 
#define MAXRXDATA_SHIFT   16
 
#define MAXRXDATA_GET(x)   (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)
 
#define TP_TIMER_RESOLUTION   0x7d90
 
#define TIMERRESOLUTION_MASK   0x00ff0000U
 
#define TIMERRESOLUTION_SHIFT   16
 
#define TIMERRESOLUTION_GET(x)   (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
 
#define DELAYEDACKRESOLUTION_MASK   0x000000ffU
 
#define DELAYEDACKRESOLUTION_SHIFT   0
 
#define DELAYEDACKRESOLUTION_GET(x)   (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)
 
#define TP_SHIFT_CNT   0x7dc0
 
#define SYNSHIFTMAX_SHIFT   24
 
#define SYNSHIFTMAX_MASK   0xff000000U
 
#define SYNSHIFTMAX(x)   ((x) << SYNSHIFTMAX_SHIFT)
 
#define SYNSHIFTMAX_GET(x)
 
#define RXTSHIFTMAXR1_SHIFT   20
 
#define RXTSHIFTMAXR1_MASK   0x00f00000U
 
#define RXTSHIFTMAXR1(x)   ((x) << RXTSHIFTMAXR1_SHIFT)
 
#define RXTSHIFTMAXR1_GET(x)
 
#define RXTSHIFTMAXR2_SHIFT   16
 
#define RXTSHIFTMAXR2_MASK   0x000f0000U
 
#define RXTSHIFTMAXR2(x)   ((x) << RXTSHIFTMAXR2_SHIFT)
 
#define RXTSHIFTMAXR2_GET(x)
 
#define PERSHIFTBACKOFFMAX_SHIFT   12
 
#define PERSHIFTBACKOFFMAX_MASK   0x0000f000U
 
#define PERSHIFTBACKOFFMAX(x)   ((x) << PERSHIFTBACKOFFMAX_SHIFT)
 
#define PERSHIFTBACKOFFMAX_GET(x)
 
#define PERSHIFTMAX_SHIFT   8
 
#define PERSHIFTMAX_MASK   0x00000f00U
 
#define PERSHIFTMAX(x)   ((x) << PERSHIFTMAX_SHIFT)
 
#define PERSHIFTMAX_GET(x)
 
#define KEEPALIVEMAXR1_SHIFT   4
 
#define KEEPALIVEMAXR1_MASK   0x000000f0U
 
#define KEEPALIVEMAXR1(x)   ((x) << KEEPALIVEMAXR1_SHIFT)
 
#define KEEPALIVEMAXR1_GET(x)
 
#define KEEPALIVEMAXR2_SHIFT   0
 
#define KEEPALIVEMAXR2_MASK   0x0000000fU
 
#define KEEPALIVEMAXR2(x)   ((x) << KEEPALIVEMAXR2_SHIFT)
 
#define KEEPALIVEMAXR2_GET(x)
 
#define TP_CCTRL_TABLE   0x7ddc
 
#define TP_MTU_TABLE   0x7de4
 
#define MTUINDEX_MASK   0xff000000U
 
#define MTUINDEX_SHIFT   24
 
#define MTUINDEX(x)   ((x) << MTUINDEX_SHIFT)
 
#define MTUWIDTH_MASK   0x000f0000U
 
#define MTUWIDTH_SHIFT   16
 
#define MTUWIDTH(x)   ((x) << MTUWIDTH_SHIFT)
 
#define MTUWIDTH_GET(x)   (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)
 
#define MTUVALUE_MASK   0x00003fffU
 
#define MTUVALUE_SHIFT   0
 
#define MTUVALUE(x)   ((x) << MTUVALUE_SHIFT)
 
#define MTUVALUE_GET(x)   (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)
 
#define TP_RSS_LKP_TABLE   0x7dec
 
#define LKPTBLROWVLD   0x80000000U
 
#define LKPTBLQUEUE1_MASK   0x000ffc00U
 
#define LKPTBLQUEUE1_SHIFT   10
 
#define LKPTBLQUEUE1(x)   ((x) << LKPTBLQUEUE1_SHIFT)
 
#define LKPTBLQUEUE1_GET(x)   (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)
 
#define LKPTBLQUEUE0_MASK   0x000003ffU
 
#define LKPTBLQUEUE0_SHIFT   0
 
#define LKPTBLQUEUE0(x)   ((x) << LKPTBLQUEUE0_SHIFT)
 
#define LKPTBLQUEUE0_GET(x)   (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)
 
#define TP_PIO_ADDR   0x7e40
 
#define TP_PIO_DATA   0x7e44
 
#define TP_MIB_INDEX   0x7e50
 
#define TP_MIB_DATA   0x7e54
 
#define TP_INT_CAUSE   0x7e74
 
#define FLMTXFLSTEMPTY   0x40000000U
 
#define TP_VLAN_PRI_MAP   0x140
 
#define FRAGMENTATION_SHIFT   9
 
#define FRAGMENTATION_MASK   0x00000200U
 
#define MPSHITTYPE_MASK   0x00000100U
 
#define MACMATCH_MASK   0x00000080U
 
#define ETHERTYPE_MASK   0x00000040U
 
#define PROTOCOL_MASK   0x00000020U
 
#define TOS_MASK   0x00000010U
 
#define VLAN_MASK   0x00000008U
 
#define VNIC_ID_MASK   0x00000004U
 
#define PORT_MASK   0x00000002U
 
#define FCOE_SHIFT   0
 
#define FCOE_MASK   0x00000001U
 
#define TP_INGRESS_CONFIG   0x141
 
#define VNIC   0x00000800U
 
#define CSUM_HAS_PSEUDO_HDR   0x00000400U
 
#define RM_OVLAN   0x00000200U
 
#define LOOKUPEVERYPKT   0x00000100U
 
#define TP_MIB_MAC_IN_ERR_0   0x0
 
#define TP_MIB_TCP_OUT_RST   0xc
 
#define TP_MIB_TCP_IN_SEG_HI   0x10
 
#define TP_MIB_TCP_IN_SEG_LO   0x11
 
#define TP_MIB_TCP_OUT_SEG_HI   0x12
 
#define TP_MIB_TCP_OUT_SEG_LO   0x13
 
#define TP_MIB_TCP_RXT_SEG_HI   0x14
 
#define TP_MIB_TCP_RXT_SEG_LO   0x15
 
#define TP_MIB_TNL_CNG_DROP_0   0x18
 
#define TP_MIB_TCP_V6IN_ERR_0   0x28
 
#define TP_MIB_TCP_V6OUT_RST   0x2c
 
#define TP_MIB_OFD_ARP_DROP   0x36
 
#define TP_MIB_TNL_DROP_0   0x44
 
#define TP_MIB_OFD_VLN_DROP_0   0x58
 
#define ULP_TX_INT_CAUSE   0x8dcc
 
#define PBL_BOUND_ERR_CH3   0x80000000U
 
#define PBL_BOUND_ERR_CH2   0x40000000U
 
#define PBL_BOUND_ERR_CH1   0x20000000U
 
#define PBL_BOUND_ERR_CH0   0x10000000U
 
#define PM_RX_INT_CAUSE   0x8fdc
 
#define ZERO_E_CMD_ERROR   0x00400000U
 
#define PMRX_FRAMING_ERROR   0x003ffff0U
 
#define OCSPI_PAR_ERROR   0x00000008U
 
#define DB_OPTIONS_PAR_ERROR   0x00000004U
 
#define IESPI_PAR_ERROR   0x00000002U
 
#define E_PCMD_PAR_ERROR   0x00000001U
 
#define PM_TX_INT_CAUSE   0x8ffc
 
#define PCMD_LEN_OVFL0   0x80000000U
 
#define PCMD_LEN_OVFL1   0x40000000U
 
#define PCMD_LEN_OVFL2   0x20000000U
 
#define ZERO_C_CMD_ERROR   0x10000000U
 
#define PMTX_FRAMING_ERROR   0x0ffffff0U
 
#define OESPI_PAR_ERROR   0x00000008U
 
#define ICSPI_PAR_ERROR   0x00000002U
 
#define C_PCMD_PAR_ERROR   0x00000001U
 
#define MPS_PORT_STAT_TX_PORT_BYTES_L   0x400
 
#define MPS_PORT_STAT_TX_PORT_BYTES_H   0x404
 
#define MPS_PORT_STAT_TX_PORT_FRAMES_L   0x408
 
#define MPS_PORT_STAT_TX_PORT_FRAMES_H   0x40c
 
#define MPS_PORT_STAT_TX_PORT_BCAST_L   0x410
 
#define MPS_PORT_STAT_TX_PORT_BCAST_H   0x414
 
#define MPS_PORT_STAT_TX_PORT_MCAST_L   0x418
 
#define MPS_PORT_STAT_TX_PORT_MCAST_H   0x41c
 
#define MPS_PORT_STAT_TX_PORT_UCAST_L   0x420
 
#define MPS_PORT_STAT_TX_PORT_UCAST_H   0x424
 
#define MPS_PORT_STAT_TX_PORT_ERROR_L   0x428
 
#define MPS_PORT_STAT_TX_PORT_ERROR_H   0x42c
 
#define MPS_PORT_STAT_TX_PORT_64B_L   0x430
 
#define MPS_PORT_STAT_TX_PORT_64B_H   0x434
 
#define MPS_PORT_STAT_TX_PORT_65B_127B_L   0x438
 
#define MPS_PORT_STAT_TX_PORT_65B_127B_H   0x43c
 
#define MPS_PORT_STAT_TX_PORT_128B_255B_L   0x440
 
#define MPS_PORT_STAT_TX_PORT_128B_255B_H   0x444
 
#define MPS_PORT_STAT_TX_PORT_256B_511B_L   0x448
 
#define MPS_PORT_STAT_TX_PORT_256B_511B_H   0x44c
 
#define MPS_PORT_STAT_TX_PORT_512B_1023B_L   0x450
 
#define MPS_PORT_STAT_TX_PORT_512B_1023B_H   0x454
 
#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L   0x458
 
#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H   0x45c
 
#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L   0x460
 
#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H   0x464
 
#define MPS_PORT_STAT_TX_PORT_DROP_L   0x468
 
#define MPS_PORT_STAT_TX_PORT_DROP_H   0x46c
 
#define MPS_PORT_STAT_TX_PORT_PAUSE_L   0x470
 
#define MPS_PORT_STAT_TX_PORT_PAUSE_H   0x474
 
#define MPS_PORT_STAT_TX_PORT_PPP0_L   0x478
 
#define MPS_PORT_STAT_TX_PORT_PPP0_H   0x47c
 
#define MPS_PORT_STAT_TX_PORT_PPP1_L   0x480
 
#define MPS_PORT_STAT_TX_PORT_PPP1_H   0x484
 
#define MPS_PORT_STAT_TX_PORT_PPP2_L   0x488
 
#define MPS_PORT_STAT_TX_PORT_PPP2_H   0x48c
 
#define MPS_PORT_STAT_TX_PORT_PPP3_L   0x490
 
#define MPS_PORT_STAT_TX_PORT_PPP3_H   0x494
 
#define MPS_PORT_STAT_TX_PORT_PPP4_L   0x498
 
#define MPS_PORT_STAT_TX_PORT_PPP4_H   0x49c
 
#define MPS_PORT_STAT_TX_PORT_PPP5_L   0x4a0
 
#define MPS_PORT_STAT_TX_PORT_PPP5_H   0x4a4
 
#define MPS_PORT_STAT_TX_PORT_PPP6_L   0x4a8
 
#define MPS_PORT_STAT_TX_PORT_PPP6_H   0x4ac
 
#define MPS_PORT_STAT_TX_PORT_PPP7_L   0x4b0
 
#define MPS_PORT_STAT_TX_PORT_PPP7_H   0x4b4
 
#define MPS_PORT_STAT_LB_PORT_BYTES_L   0x4c0
 
#define MPS_PORT_STAT_LB_PORT_BYTES_H   0x4c4
 
#define MPS_PORT_STAT_LB_PORT_FRAMES_L   0x4c8
 
#define MPS_PORT_STAT_LB_PORT_FRAMES_H   0x4cc
 
#define MPS_PORT_STAT_LB_PORT_BCAST_L   0x4d0
 
#define MPS_PORT_STAT_LB_PORT_BCAST_H   0x4d4
 
#define MPS_PORT_STAT_LB_PORT_MCAST_L   0x4d8
 
#define MPS_PORT_STAT_LB_PORT_MCAST_H   0x4dc
 
#define MPS_PORT_STAT_LB_PORT_UCAST_L   0x4e0
 
#define MPS_PORT_STAT_LB_PORT_UCAST_H   0x4e4
 
#define MPS_PORT_STAT_LB_PORT_ERROR_L   0x4e8
 
#define MPS_PORT_STAT_LB_PORT_ERROR_H   0x4ec
 
#define MPS_PORT_STAT_LB_PORT_64B_L   0x4f0
 
#define MPS_PORT_STAT_LB_PORT_64B_H   0x4f4
 
#define MPS_PORT_STAT_LB_PORT_65B_127B_L   0x4f8
 
#define MPS_PORT_STAT_LB_PORT_65B_127B_H   0x4fc
 
#define MPS_PORT_STAT_LB_PORT_128B_255B_L   0x500
 
#define MPS_PORT_STAT_LB_PORT_128B_255B_H   0x504
 
#define MPS_PORT_STAT_LB_PORT_256B_511B_L   0x508
 
#define MPS_PORT_STAT_LB_PORT_256B_511B_H   0x50c
 
#define MPS_PORT_STAT_LB_PORT_512B_1023B_L   0x510
 
#define MPS_PORT_STAT_LB_PORT_512B_1023B_H   0x514
 
#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L   0x518
 
#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H   0x51c
 
#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L   0x520
 
#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H   0x524
 
#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES   0x528
 
#define MPS_PORT_STAT_RX_PORT_BYTES_L   0x540
 
#define MPS_PORT_STAT_RX_PORT_BYTES_H   0x544
 
#define MPS_PORT_STAT_RX_PORT_FRAMES_L   0x548
 
#define MPS_PORT_STAT_RX_PORT_FRAMES_H   0x54c
 
#define MPS_PORT_STAT_RX_PORT_BCAST_L   0x550
 
#define MPS_PORT_STAT_RX_PORT_BCAST_H   0x554
 
#define MPS_PORT_STAT_RX_PORT_MCAST_L   0x558
 
#define MPS_PORT_STAT_RX_PORT_MCAST_H   0x55c
 
#define MPS_PORT_STAT_RX_PORT_UCAST_L   0x560
 
#define MPS_PORT_STAT_RX_PORT_UCAST_H   0x564
 
#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L   0x568
 
#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H   0x56c
 
#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L   0x570
 
#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H   0x574
 
#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L   0x578
 
#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H   0x57c
 
#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L   0x580
 
#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H   0x584
 
#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L   0x588
 
#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H   0x58c
 
#define MPS_PORT_STAT_RX_PORT_64B_L   0x590
 
#define MPS_PORT_STAT_RX_PORT_64B_H   0x594
 
#define MPS_PORT_STAT_RX_PORT_65B_127B_L   0x598
 
#define MPS_PORT_STAT_RX_PORT_65B_127B_H   0x59c
 
#define MPS_PORT_STAT_RX_PORT_128B_255B_L   0x5a0
 
#define MPS_PORT_STAT_RX_PORT_128B_255B_H   0x5a4
 
#define MPS_PORT_STAT_RX_PORT_256B_511B_L   0x5a8
 
#define MPS_PORT_STAT_RX_PORT_256B_511B_H   0x5ac
 
#define MPS_PORT_STAT_RX_PORT_512B_1023B_L   0x5b0
 
#define MPS_PORT_STAT_RX_PORT_512B_1023B_H   0x5b4
 
#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L   0x5b8
 
#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H   0x5bc
 
#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L   0x5c0
 
#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H   0x5c4
 
#define MPS_PORT_STAT_RX_PORT_PAUSE_L   0x5c8
 
#define MPS_PORT_STAT_RX_PORT_PAUSE_H   0x5cc
 
#define MPS_PORT_STAT_RX_PORT_PPP0_L   0x5d0
 
#define MPS_PORT_STAT_RX_PORT_PPP0_H   0x5d4
 
#define MPS_PORT_STAT_RX_PORT_PPP1_L   0x5d8
 
#define MPS_PORT_STAT_RX_PORT_PPP1_H   0x5dc
 
#define MPS_PORT_STAT_RX_PORT_PPP2_L   0x5e0
 
#define MPS_PORT_STAT_RX_PORT_PPP2_H   0x5e4
 
#define MPS_PORT_STAT_RX_PORT_PPP3_L   0x5e8
 
#define MPS_PORT_STAT_RX_PORT_PPP3_H   0x5ec
 
#define MPS_PORT_STAT_RX_PORT_PPP4_L   0x5f0
 
#define MPS_PORT_STAT_RX_PORT_PPP4_H   0x5f4
 
#define MPS_PORT_STAT_RX_PORT_PPP5_L   0x5f8
 
#define MPS_PORT_STAT_RX_PORT_PPP5_H   0x5fc
 
#define MPS_PORT_STAT_RX_PORT_PPP6_L   0x600
 
#define MPS_PORT_STAT_RX_PORT_PPP6_H   0x604
 
#define MPS_PORT_STAT_RX_PORT_PPP7_L   0x608
 
#define MPS_PORT_STAT_RX_PORT_PPP7_H   0x60c
 
#define MPS_PORT_STAT_RX_PORT_LESS_64B_L   0x610
 
#define MPS_PORT_STAT_RX_PORT_LESS_64B_H   0x614
 
#define MPS_CMN_CTL   0x9000
 
#define NUMPORTS_MASK   0x00000003U
 
#define NUMPORTS_SHIFT   0
 
#define NUMPORTS_GET(x)   (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)
 
#define MPS_INT_CAUSE   0x9008
 
#define STATINT   0x00000020U
 
#define TXINT   0x00000010U
 
#define RXINT   0x00000008U
 
#define TRCINT   0x00000004U
 
#define CLSINT   0x00000002U
 
#define PLINT   0x00000001U
 
#define MPS_TX_INT_CAUSE   0x9408
 
#define PORTERR   0x00010000U
 
#define FRMERR   0x00008000U
 
#define SECNTERR   0x00004000U
 
#define BUBBLE   0x00002000U
 
#define TXDESCFIFO   0x00001e00U
 
#define TXDATAFIFO   0x000001e0U
 
#define NCSIFIFO   0x00000010U
 
#define TPFIFO   0x0000000fU
 
#define MPS_STAT_PERR_INT_CAUSE_SRAM   0x9614
 
#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO   0x9620
 
#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO   0x962c
 
#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L   0x9640
 
#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H   0x9644
 
#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L   0x9648
 
#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H   0x964c
 
#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L   0x9650
 
#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H   0x9654
 
#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L   0x9658
 
#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H   0x965c
 
#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L   0x9660
 
#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H   0x9664
 
#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L   0x9668
 
#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H   0x966c
 
#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L   0x9670
 
#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H   0x9674
 
#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L   0x9678
 
#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H   0x967c
 
#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L   0x9680
 
#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H   0x9684
 
#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L   0x9688
 
#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H   0x968c
 
#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L   0x9690
 
#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H   0x9694
 
#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L   0x9698
 
#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H   0x969c
 
#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L   0x96a0
 
#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H   0x96a4
 
#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L   0x96a8
 
#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H   0x96ac
 
#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L   0x96b0
 
#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H   0x96b4
 
#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L   0x96b8
 
#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H   0x96bc
 
#define MPS_TRC_CFG   0x9800
 
#define TRCFIFOEMPTY   0x00000010U
 
#define TRCIGNOREDROPINPUT   0x00000008U
 
#define TRCKEEPDUPLICATES   0x00000004U
 
#define TRCEN   0x00000002U
 
#define TRCMULTIFILTER   0x00000001U
 
#define MPS_TRC_RSS_CONTROL   0x9808
 
#define RSSCONTROL_MASK   0x00ff0000U
 
#define RSSCONTROL_SHIFT   16
 
#define RSSCONTROL(x)   ((x) << RSSCONTROL_SHIFT)
 
#define QUEUENUMBER_MASK   0x0000ffffU
 
#define QUEUENUMBER_SHIFT   0
 
#define QUEUENUMBER(x)   ((x) << QUEUENUMBER_SHIFT)
 
#define MPS_TRC_FILTER_MATCH_CTL_A   0x9810
 
#define TFINVERTMATCH   0x01000000U
 
#define TFPKTTOOLARGE   0x00800000U
 
#define TFEN   0x00400000U
 
#define TFPORT_MASK   0x003c0000U
 
#define TFPORT_SHIFT   18
 
#define TFPORT(x)   ((x) << TFPORT_SHIFT)
 
#define TFPORT_GET(x)   (((x) & TFPORT_MASK) >> TFPORT_SHIFT)
 
#define TFDROP   0x00020000U
 
#define TFSOPEOPERR   0x00010000U
 
#define TFLENGTH_MASK   0x00001f00U
 
#define TFLENGTH_SHIFT   8
 
#define TFLENGTH(x)   ((x) << TFLENGTH_SHIFT)
 
#define TFLENGTH_GET(x)   (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)
 
#define TFOFFSET_MASK   0x0000001fU
 
#define TFOFFSET_SHIFT   0
 
#define TFOFFSET(x)   ((x) << TFOFFSET_SHIFT)
 
#define TFOFFSET_GET(x)   (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)
 
#define MPS_TRC_FILTER_MATCH_CTL_B   0x9820
 
#define TFMINPKTSIZE_MASK   0x01ff0000U
 
#define TFMINPKTSIZE_SHIFT   16
 
#define TFMINPKTSIZE(x)   ((x) << TFMINPKTSIZE_SHIFT)
 
#define TFMINPKTSIZE_GET(x)   (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)
 
#define TFCAPTUREMAX_MASK   0x00003fffU
 
#define TFCAPTUREMAX_SHIFT   0
 
#define TFCAPTUREMAX(x)   ((x) << TFCAPTUREMAX_SHIFT)
 
#define TFCAPTUREMAX_GET(x)   (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)
 
#define MPS_TRC_INT_CAUSE   0x985c
 
#define MISCPERR   0x00000100U
 
#define PKTFIFO   0x000000f0U
 
#define FILTMEM   0x0000000fU
 
#define MPS_TRC_FILTER0_MATCH   0x9c00
 
#define MPS_TRC_FILTER0_DONT_CARE   0x9c80
 
#define MPS_TRC_FILTER1_MATCH   0x9d00
 
#define MPS_CLS_INT_CAUSE   0xd028
 
#define PLERRENB   0x00000008U
 
#define HASHSRAM   0x00000004U
 
#define MATCHTCAM   0x00000002U
 
#define MATCHSRAM   0x00000001U
 
#define MPS_RX_PERR_INT_CAUSE   0x11074
 
#define CPL_INTR_CAUSE   0x19054
 
#define CIM_OP_MAP_PERR   0x00000020U
 
#define CIM_OVFL_ERROR   0x00000010U
 
#define TP_FRAMING_ERROR   0x00000008U
 
#define SGE_FRAMING_ERROR   0x00000004U
 
#define CIM_FRAMING_ERROR   0x00000002U
 
#define ZERO_SWITCH_ERROR   0x00000001U
 
#define SMB_INT_CAUSE   0x19090
 
#define MSTTXFIFOPARINT   0x00200000U
 
#define MSTRXFIFOPARINT   0x00100000U
 
#define SLVFIFOPARINT   0x00080000U
 
#define ULP_RX_INT_CAUSE   0x19158
 
#define ULP_RX_ISCSI_TAGMASK   0x19164
 
#define ULP_RX_ISCSI_PSZ   0x19168
 
#define HPZ3_MASK   0x0f000000U
 
#define HPZ3_SHIFT   24
 
#define HPZ3(x)   ((x) << HPZ3_SHIFT)
 
#define HPZ2_MASK   0x000f0000U
 
#define HPZ2_SHIFT   16
 
#define HPZ2(x)   ((x) << HPZ2_SHIFT)
 
#define HPZ1_MASK   0x00000f00U
 
#define HPZ1_SHIFT   8
 
#define HPZ1(x)   ((x) << HPZ1_SHIFT)
 
#define HPZ0_MASK   0x0000000fU
 
#define HPZ0_SHIFT   0
 
#define HPZ0(x)   ((x) << HPZ0_SHIFT)
 
#define ULP_RX_TDDP_PSZ   0x19178
 
#define SF_DATA   0x193f8
 
#define SF_OP   0x193fc
 
#define BUSY   0x80000000U
 
#define SF_LOCK   0x00000010U
 
#define SF_CONT   0x00000008U
 
#define BYTECNT_MASK   0x00000006U
 
#define BYTECNT_SHIFT   1
 
#define BYTECNT(x)   ((x) << BYTECNT_SHIFT)
 
#define OP_WR   0x00000001U
 
#define PL_PF_INT_CAUSE   0x3c0
 
#define PFSW   0x00000008U
 
#define PFSGE   0x00000004U
 
#define PFCIM   0x00000002U
 
#define PFMPS   0x00000001U
 
#define PL_PF_INT_ENABLE   0x3c4
 
#define PL_PF_CTL   0x3c8
 
#define SWINT   0x00000001U
 
#define PL_WHOAMI   0x19400
 
#define SOURCEPF_MASK   0x00000700U
 
#define SOURCEPF_SHIFT   8
 
#define SOURCEPF(x)   ((x) << SOURCEPF_SHIFT)
 
#define SOURCEPF_GET(x)   (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
 
#define ISVF   0x00000080U
 
#define VFID_MASK   0x0000007fU
 
#define VFID_SHIFT   0
 
#define VFID(x)   ((x) << VFID_SHIFT)
 
#define VFID_GET(x)   (((x) & VFID_MASK) >> VFID_SHIFT)
 
#define PL_INT_CAUSE   0x1940c
 
#define ULP_TX   0x08000000U
 
#define SGE   0x04000000U
 
#define HMA   0x02000000U
 
#define CPL_SWITCH   0x01000000U
 
#define ULP_RX   0x00800000U
 
#define PM_RX   0x00400000U
 
#define PM_TX   0x00200000U
 
#define MA   0x00100000U
 
#define TP   0x00080000U
 
#define LE   0x00040000U
 
#define EDC1   0x00020000U
 
#define EDC0   0x00010000U
 
#define MC   0x00008000U
 
#define PCIE   0x00004000U
 
#define PMU   0x00002000U
 
#define XGMAC_KR1   0x00001000U
 
#define XGMAC_KR0   0x00000800U
 
#define XGMAC1   0x00000400U
 
#define XGMAC0   0x00000200U
 
#define SMB   0x00000100U
 
#define SF   0x00000080U
 
#define PL   0x00000040U
 
#define NCSI   0x00000020U
 
#define MPS   0x00000010U
 
#define MI   0x00000008U
 
#define DBG   0x00000004U
 
#define I2CM   0x00000002U
 
#define CIM   0x00000001U
 
#define PL_INT_MAP0   0x19414
 
#define PL_RST   0x19428
 
#define PIORST   0x00000002U
 
#define PIORSTMODE   0x00000001U
 
#define PL_PL_INT_CAUSE   0x19430
 
#define FATALPERR   0x00000010U
 
#define PERRVFID   0x00000001U
 
#define PL_REV   0x1943c
 
#define LE_DB_CONFIG   0x19c04
 
#define HASHEN   0x00100000U
 
#define LE_DB_SERVER_INDEX   0x19c18
 
#define LE_DB_ACT_CNT_IPV4   0x19c20
 
#define LE_DB_ACT_CNT_IPV6   0x19c24
 
#define LE_DB_INT_CAUSE   0x19c3c
 
#define REQQPARERR   0x00010000U
 
#define UNKNOWNCMD   0x00008000U
 
#define PARITYERR   0x00000040U
 
#define LIPMISS   0x00000020U
 
#define LIP0   0x00000010U
 
#define LE_DB_TID_HASHBASE   0x19df8
 
#define NCSI_INT_CAUSE   0x1a0d8
 
#define CIM_DM_PRTY_ERR   0x00000100U
 
#define MPS_DM_PRTY_ERR   0x00000080U
 
#define TXFIFO_PRTY_ERR   0x00000002U
 
#define RXFIFO_PRTY_ERR   0x00000001U
 
#define XGMAC_PORT_CFG2   0x1018
 
#define PATEN   0x00040000U
 
#define MAGICEN   0x00020000U
 
#define XGMAC_PORT_MAGIC_MACID_LO   0x1024
 
#define XGMAC_PORT_MAGIC_MACID_HI   0x1028
 
#define XGMAC_PORT_EPIO_DATA0   0x10c0
 
#define XGMAC_PORT_EPIO_DATA1   0x10c4
 
#define XGMAC_PORT_EPIO_DATA2   0x10c8
 
#define XGMAC_PORT_EPIO_DATA3   0x10cc
 
#define XGMAC_PORT_EPIO_OP   0x10d0
 
#define EPIOWR   0x00000100U
 
#define ADDRESS_MASK   0x000000ffU
 
#define ADDRESS_SHIFT   0
 
#define ADDRESS(x)   ((x) << ADDRESS_SHIFT)
 
#define XGMAC_PORT_INT_CAUSE   0x10dc
 

Macro Definition Documentation

#define A_SGE_CTXT_CMD   0x11fc

Definition at line 277 of file t4_regs.h.

#define A_SGE_DBFIFO_STATUS   0x10a4

Definition at line 267 of file t4_regs.h.

#define A_SGE_DBQ_CTXT_BADDR   0x1084

Definition at line 278 of file t4_regs.h.

#define A_SGE_DOORBELL_CONTROL   0x10a8

Definition at line 275 of file t4_regs.h.

#define ADDRESS (   x)    ((x) << ADDRESS_SHIFT)

Definition at line 1032 of file t4_regs.h.

#define ADDRESS_MASK   0x000000ffU

Definition at line 1030 of file t4_regs.h.

#define ADDRESS_SHIFT   0

Definition at line 1031 of file t4_regs.h.

#define BIR (   x)    ((x) << BIR_SHIFT)

Definition at line 318 of file t4_regs.h.

#define BIR_MASK   0x00000300U

Definition at line 316 of file t4_regs.h.

#define BIR_SHIFT   8

Definition at line 317 of file t4_regs.h.

#define BIST_CMD_GAP (   x)    ((x) << BIST_CMD_GAP_SHIFT)

Definition at line 368 of file t4_regs.h.

#define BIST_CMD_GAP_MASK   0x0000ff00U

Definition at line 366 of file t4_regs.h.

#define BIST_CMD_GAP_SHIFT   8

Definition at line 367 of file t4_regs.h.

#define BIST_DATA_TYPE (   x)    ((x) << BIST_DATA_TYPE_SHIFT)

Definition at line 378 of file t4_regs.h.

#define BIST_DATA_TYPE_MASK   0x0000000fU

Definition at line 376 of file t4_regs.h.

#define BIST_DATA_TYPE_SHIFT   0

Definition at line 377 of file t4_regs.h.

#define BIST_OPCODE (   x)    ((x) << BIST_OPCODE_SHIFT)

Definition at line 371 of file t4_regs.h.

#define BIST_OPCODE_MASK   0x00000003U

Definition at line 369 of file t4_regs.h.

#define BIST_OPCODE_SHIFT   0

Definition at line 370 of file t4_regs.h.

#define BLKRDBOOTINT   0x00000100U

Definition at line 483 of file t4_regs.h.

#define BLKRDCTLINT   0x00100000U

Definition at line 471 of file t4_regs.h.

#define BLKRDEEPROMINT   0x00010000U

Definition at line 475 of file t4_regs.h.

#define BLKRDFLASHINT   0x00001000U

Definition at line 479 of file t4_regs.h.

#define BLKRDPLINT   0x01000000U

Definition at line 467 of file t4_regs.h.

#define BLKWRBOOTINT   0x00000200U

Definition at line 482 of file t4_regs.h.

#define BLKWRCTLINT   0x00200000U

Definition at line 470 of file t4_regs.h.

#define BLKWREEPROMINT   0x00020000U

Definition at line 474 of file t4_regs.h.

#define BLKWRFLASHINT   0x00002000U

Definition at line 478 of file t4_regs.h.

#define BLKWRPLINT   0x02000000U

Definition at line 466 of file t4_regs.h.

#define BOOTADDR_MASK   0xffffff00U

Definition at line 423 of file t4_regs.h.

#define BUBBLE   0x00002000U

Definition at line 790 of file t4_regs.h.

#define BUSY   0x80000000U

Definition at line 925 of file t4_regs.h.

#define BYTECNT (   x)    ((x) << BYTECNT_SHIFT)

Definition at line 930 of file t4_regs.h.

#define BYTECNT_MASK   0x00000006U

Definition at line 928 of file t4_regs.h.

#define BYTECNT_SHIFT   1

Definition at line 929 of file t4_regs.h.

#define C_PCMD_PAR_ERROR   0x00000001U

Definition at line 644 of file t4_regs.h.

#define CCNTPERR   0x00000400U

Definition at line 301 of file t4_regs.h.

#define CFGSNPPERR   0x00080000U

Definition at line 292 of file t4_regs.h.

#define CIDXINC (   x)    ((x) << CIDXINC_SHIFT)

Definition at line 87 of file t4_regs.h.

#define CIDXINC_MASK   0x00000fffU

Definition at line 85 of file t4_regs.h.

#define CIDXINC_SHIFT   0

Definition at line 86 of file t4_regs.h.

#define CIM   0x00000001U

Definition at line 982 of file t4_regs.h.

#define CIM_BOOT_CFG   0x7b00

Definition at line 422 of file t4_regs.h.

#define CIM_DM_PRTY_ERR   0x00000100U

Definition at line 1012 of file t4_regs.h.

#define CIM_FRAMING_ERROR   0x00000002U

Definition at line 897 of file t4_regs.h.

#define CIM_HOST_INT_CAUSE   0x7b2c

Definition at line 438 of file t4_regs.h.

#define CIM_HOST_UPACC_INT_CAUSE   0x7b34

Definition at line 460 of file t4_regs.h.

#define CIM_OP_MAP_PERR   0x00000020U

Definition at line 893 of file t4_regs.h.

#define CIM_OVFL_ERROR   0x00000010U

Definition at line 894 of file t4_regs.h.

#define CIM_PF_HOST_INT_CAUSE   0x28c

Definition at line 435 of file t4_regs.h.

#define CIM_PF_MAILBOX_CTRL   0x280

Definition at line 427 of file t4_regs.h.

#define CIM_PF_MAILBOX_DATA   0x240

Definition at line 426 of file t4_regs.h.

#define CLSINT   0x00000002U

Definition at line 783 of file t4_regs.h.

#define CPL_INTR_CAUSE   0x19054

Definition at line 892 of file t4_regs.h.

#define CPL_SWITCH   0x01000000U

Definition at line 958 of file t4_regs.h.

#define CREQPERR   0x00000800U

Definition at line 300 of file t4_regs.h.

#define CRSPPERR   0x00001000U

Definition at line 299 of file t4_regs.h.

#define CSUM_HAS_PSEUDO_HDR   0x00000400U

Definition at line 603 of file t4_regs.h.

#define DB_OPTIONS_PAR_ERROR   0x00000004U

Definition at line 632 of file t4_regs.h.

#define DBFIFO_HP_INT   0x00000100U

Definition at line 181 of file t4_regs.h.

#define DBFIFO_LP_INT   0x00000080U

Definition at line 182 of file t4_regs.h.

#define DBG   0x00000004U

Definition at line 980 of file t4_regs.h.

#define DBPRIO   0x00004000U

Definition at line 70 of file t4_regs.h.

#define DCASYSTYPE   0x00080000U

Definition at line 93 of file t4_regs.h.

#define DCNTPERR   0x00002000U

Definition at line 298 of file t4_regs.h.

#define DELAYEDACKRESOLUTION_GET (   x)    (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)

Definition at line 515 of file t4_regs.h.

#define DELAYEDACKRESOLUTION_MASK   0x000000ffU

Definition at line 513 of file t4_regs.h.

#define DELAYEDACKRESOLUTION_SHIFT   0

Definition at line 514 of file t4_regs.h.

#define DREQPERR   0x00004000U

Definition at line 297 of file t4_regs.h.

#define DRSPPERR   0x00008000U

Definition at line 296 of file t4_regs.h.

#define E_PCMD_PAR_ERROR   0x00000001U

Definition at line 634 of file t4_regs.h.

#define ECC_CE_INT_CAUSE   0x00000002U

Definition at line 351 of file t4_regs.h.

#define ECC_CE_PAR   0x00000010U

Definition at line 415 of file t4_regs.h.

#define ECC_CECNT (   x)    ((x) << ECC_CECNT_SHIFT)

Definition at line 357 of file t4_regs.h.

#define ECC_CECNT_GET (   x)    (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)

Definition at line 358 of file t4_regs.h.

#define ECC_CECNT_MASK   0xffff0000U

Definition at line 355 of file t4_regs.h.

#define ECC_CECNT_SHIFT   16

Definition at line 356 of file t4_regs.h.

#define ECC_UE_INT_CAUSE   0x00000004U

Definition at line 350 of file t4_regs.h.

#define ECC_UE_PAR   0x00000020U

Definition at line 414 of file t4_regs.h.

#define ECC_UECNT (   x)    ((x) << ECC_UECNT_SHIFT)

Definition at line 361 of file t4_regs.h.

#define ECC_UECNT_GET (   x)    (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)

Definition at line 362 of file t4_regs.h.

#define ECC_UECNT_MASK   0x0000ffffU

Definition at line 359 of file t4_regs.h.

#define ECC_UECNT_SHIFT   0

Definition at line 360 of file t4_regs.h.

#define EDC0   0x00010000U

Definition at line 966 of file t4_regs.h.

#define EDC1   0x00020000U

Definition at line 965 of file t4_regs.h.

#define EDC_0_BASE_ADDR   0x7900

Definition at line 406 of file t4_regs.h.

#define EDC_1_BASE_ADDR   0x7980

Definition at line 420 of file t4_regs.h.

#define EDC_BIST_CMD   0x7904

Definition at line 408 of file t4_regs.h.

#define EDC_BIST_CMD_ADDR   0x7908

Definition at line 409 of file t4_regs.h.

#define EDC_BIST_CMD_LEN   0x790c

Definition at line 410 of file t4_regs.h.

#define EDC_BIST_DATA_PATTERN   0x7910

Definition at line 411 of file t4_regs.h.

#define EDC_BIST_STATUS_RDATA   0x7928

Definition at line 412 of file t4_regs.h.

#define EDC_BIST_STATUS_REG (   reg_addr,
  idx 
)    ((reg_addr) + (idx) * 4)

Definition at line 64 of file t4_regs.h.

#define EDC_ECC_STATUS   0x797c

Definition at line 418 of file t4_regs.h.

#define EDC_INT_CAUSE   0x7978

Definition at line 413 of file t4_regs.h.

#define EDC_REG (   reg,
  idx 
)    (reg + EDC_STRIDE * idx)

Definition at line 59 of file t4_regs.h.

#define EDC_STRIDE   (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)

Definition at line 58 of file t4_regs.h.

#define EDRAM0_ENABLE   0x00000001U

Definition at line 390 of file t4_regs.h.

#define EDRAM1_ENABLE   0x00000002U

Definition at line 389 of file t4_regs.h.

#define EEPROMWRINT   0x40000000U

Definition at line 461 of file t4_regs.h.

#define EGRESS_SIZE_ERR   0x00000010U

Definition at line 185 of file t4_regs.h.

#define EGRPCIEBOUNDARY (   x)    ((x) << EGRPCIEBOUNDARY_SHIFT)

Definition at line 114 of file t4_regs.h.

#define EGRPCIEBOUNDARY_MASK   0x0000000eU

Definition at line 112 of file t4_regs.h.

#define EGRPCIEBOUNDARY_SHIFT   1

Definition at line 113 of file t4_regs.h.

#define EGRSTATUSPAGESIZE (   x)    ((x) << EGRSTATUSPAGESIZE_SHIFT)

Definition at line 99 of file t4_regs.h.

#define EGRSTATUSPAGESIZE_MASK   0x00020000U

Definition at line 97 of file t4_regs.h.

#define EGRSTATUSPAGESIZE_SHIFT   17

Definition at line 98 of file t4_regs.h.

#define EGRTHRESHOLD (   x)    ((x) << EGRTHRESHOLDshift)

Definition at line 217 of file t4_regs.h.

#define EGRTHRESHOLD_GET (   x)    (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)

Definition at line 218 of file t4_regs.h.

#define EGRTHRESHOLD_MASK   0x00003f00U

Definition at line 215 of file t4_regs.h.

#define EGRTHRESHOLDshift   8

Definition at line 216 of file t4_regs.h.

#define EPIOWR   0x00000100U

Definition at line 1029 of file t4_regs.h.

#define ERR_BAD_DB_PIDX0   0x00001000U

Definition at line 177 of file t4_regs.h.

#define ERR_BAD_DB_PIDX1   0x00002000U

Definition at line 176 of file t4_regs.h.

#define ERR_BAD_DB_PIDX2   0x00004000U

Definition at line 175 of file t4_regs.h.

#define ERR_BAD_DB_PIDX3   0x00008000U

Definition at line 174 of file t4_regs.h.

#define ERR_CPL_EXCEED_IQE_SIZE   0x00400000U

Definition at line 167 of file t4_regs.h.

#define ERR_CPL_OPCODE_0   0x00080000U

Definition at line 170 of file t4_regs.h.

#define ERR_DATA_CPL_ON_HIGH_QID0   0x00010000U

Definition at line 173 of file t4_regs.h.

#define ERR_DATA_CPL_ON_HIGH_QID1   0x00020000U

Definition at line 172 of file t4_regs.h.

#define ERR_DROPPED_DB   0x00040000U

Definition at line 171 of file t4_regs.h.

#define ERR_EGR_CTXT_PRIO   0x00000200U

Definition at line 180 of file t4_regs.h.

#define ERR_FLM_DBP   0x80000000U

Definition at line 158 of file t4_regs.h.

#define ERR_FLM_HINT   0x10000000U

Definition at line 161 of file t4_regs.h.

#define ERR_FLM_IDMA0   0x20000000U

Definition at line 160 of file t4_regs.h.

#define ERR_FLM_IDMA1   0x40000000U

Definition at line 159 of file t4_regs.h.

#define ERR_ING_CTXT_PRIO   0x00000400U

Definition at line 179 of file t4_regs.h.

#define ERR_ING_PCIE_CHAN   0x00000800U

Definition at line 178 of file t4_regs.h.

#define ERR_INV_CTXT0   0x00000001U

Definition at line 189 of file t4_regs.h.

#define ERR_INV_CTXT1   0x00000002U

Definition at line 188 of file t4_regs.h.

#define ERR_INV_CTXT2   0x00000004U

Definition at line 187 of file t4_regs.h.

#define ERR_INV_CTXT3   0x00000008U

Definition at line 186 of file t4_regs.h.

#define ERR_INVALID_CIDX_INC   0x00200000U

Definition at line 168 of file t4_regs.h.

#define ERR_ITP_TIME_PAUSED   0x00100000U

Definition at line 169 of file t4_regs.h.

#define ERR_PCIE_ERROR0   0x01000000U

Definition at line 165 of file t4_regs.h.

#define ERR_PCIE_ERROR1   0x02000000U

Definition at line 164 of file t4_regs.h.

#define ERR_PCIE_ERROR2   0x04000000U

Definition at line 163 of file t4_regs.h.

#define ERR_PCIE_ERROR3   0x08000000U

Definition at line 162 of file t4_regs.h.

#define ERR_TIMER_ABOVE_MAX_QID   0x00800000U

Definition at line 166 of file t4_regs.h.

#define ETHERTYPE_MASK   0x00000040U

Definition at line 592 of file t4_regs.h.

#define EXT_MEM_ENABLE   0x00000004U

Definition at line 388 of file t4_regs.h.

#define EXT_MEM_SIZE_GET (   x)    (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT)

Definition at line 385 of file t4_regs.h.

#define EXT_MEM_SIZE_MASK   0x00000fffU

Definition at line 383 of file t4_regs.h.

#define EXT_MEM_SIZE_SHIFT   0

Definition at line 384 of file t4_regs.h.

#define F_DROPPED_DB   V_DROPPED_DB(1U)

Definition at line 274 of file t4_regs.h.

#define F_ENABLE_DROP   V_ENABLE_DROP(1U)

Definition at line 271 of file t4_regs.h.

#define FATALPERR   0x00000010U

Definition at line 990 of file t4_regs.h.

#define FCOE_MASK   0x00000001U

Definition at line 599 of file t4_regs.h.

#define FCOE_SHIFT   0

Definition at line 598 of file t4_regs.h.

#define FIDPERR   0x00100000U

Definition at line 291 of file t4_regs.h.

#define FILTMEM   0x0000000fU

Definition at line 879 of file t4_regs.h.

#define FIVETUPLELOOKUP (   x)    ((x) << FIVETUPLELOOKUP_SHIFT)

Definition at line 500 of file t4_regs.h.

#define FIVETUPLELOOKUP_GET (   x)
Value:
(((x) & FIVETUPLELOOKUP_MASK) >> \
FIVETUPLELOOKUP_SHIFT)

Definition at line 501 of file t4_regs.h.

#define FIVETUPLELOOKUP_MASK   0x00060000U

Definition at line 499 of file t4_regs.h.

#define FIVETUPLELOOKUP_SHIFT   17

Definition at line 498 of file t4_regs.h.

#define FLMTXFLSTEMPTY   0x40000000U

Definition at line 585 of file t4_regs.h.

#define FRAGMENTATION_MASK   0x00000200U

Definition at line 589 of file t4_regs.h.

#define FRAGMENTATION_SHIFT   9

Definition at line 588 of file t4_regs.h.

#define FRMERR   0x00008000U

Definition at line 788 of file t4_regs.h.

#define G_HP_COUNT (   x)    (((x) >> S_HP_COUNT) & M_HP_COUNT)

Definition at line 260 of file t4_regs.h.

#define G_LP_COUNT (   x)    (((x) >> S_LP_COUNT) & M_LP_COUNT)

Definition at line 266 of file t4_regs.h.

#define GLOBALENABLE   0x00000001U

Definition at line 115 of file t4_regs.h.

#define GTRP   0x00100000U

Definition at line 344 of file t4_regs.h.

#define HASHEN   0x00100000U

Definition at line 996 of file t4_regs.h.

#define HASHSRAM   0x00000004U

Definition at line 886 of file t4_regs.h.

#define HCNTPERR   0x00010000U

Definition at line 295 of file t4_regs.h.

#define HMA   0x02000000U

Definition at line 957 of file t4_regs.h.

#define HOSTPAGESIZEPF0 (   x)    ((x) << HOSTPAGESIZEPF0_SHIFT)

Definition at line 149 of file t4_regs.h.

#define HOSTPAGESIZEPF0_MASK   0x0000000fU

Definition at line 147 of file t4_regs.h.

#define HOSTPAGESIZEPF0_SHIFT   0

Definition at line 148 of file t4_regs.h.

#define HOSTPAGESIZEPF1 (   x)    ((x) << HOSTPAGESIZEPF1_SHIFT)

Definition at line 145 of file t4_regs.h.

#define HOSTPAGESIZEPF1_MASK   0x0000000fU

Definition at line 143 of file t4_regs.h.

#define HOSTPAGESIZEPF1_SHIFT   4

Definition at line 144 of file t4_regs.h.

#define HOSTPAGESIZEPF2 (   x)    ((x) << HOSTPAGESIZEPF2_SHIFT)

Definition at line 141 of file t4_regs.h.

#define HOSTPAGESIZEPF2_MASK   0x0000000fU

Definition at line 139 of file t4_regs.h.

#define HOSTPAGESIZEPF2_SHIFT   8

Definition at line 140 of file t4_regs.h.

#define HOSTPAGESIZEPF3 (   x)    ((x) << HOSTPAGESIZEPF3_SHIFT)

Definition at line 137 of file t4_regs.h.

#define HOSTPAGESIZEPF3_MASK   0x0000000fU

Definition at line 135 of file t4_regs.h.

#define HOSTPAGESIZEPF3_SHIFT   12

Definition at line 136 of file t4_regs.h.

#define HOSTPAGESIZEPF4 (   x)    ((x) << HOSTPAGESIZEPF4_SHIFT)

Definition at line 133 of file t4_regs.h.

#define HOSTPAGESIZEPF4_MASK   0x0000000fU

Definition at line 131 of file t4_regs.h.

#define HOSTPAGESIZEPF4_SHIFT   16

Definition at line 132 of file t4_regs.h.

#define HOSTPAGESIZEPF5 (   x)    ((x) << HOSTPAGESIZEPF5_SHIFT)

Definition at line 129 of file t4_regs.h.

#define HOSTPAGESIZEPF5_MASK   0x0000000fU

Definition at line 127 of file t4_regs.h.

#define HOSTPAGESIZEPF5_SHIFT   20

Definition at line 128 of file t4_regs.h.

#define HOSTPAGESIZEPF6 (   x)    ((x) << HOSTPAGESIZEPF6_SHIFT)

Definition at line 125 of file t4_regs.h.

#define HOSTPAGESIZEPF6_MASK   0x0000000fU

Definition at line 123 of file t4_regs.h.

#define HOSTPAGESIZEPF6_SHIFT   24

Definition at line 124 of file t4_regs.h.

#define HOSTPAGESIZEPF7 (   x)    ((x) << HOSTPAGESIZEPF7_SHIFT)

Definition at line 121 of file t4_regs.h.

#define HOSTPAGESIZEPF7_MASK   0x0000000fU

Definition at line 119 of file t4_regs.h.

#define HOSTPAGESIZEPF7_SHIFT   28

Definition at line 120 of file t4_regs.h.

#define HPZ0 (   x)    ((x) << HPZ0_SHIFT)

Definition at line 919 of file t4_regs.h.

#define HPZ0_MASK   0x0000000fU

Definition at line 917 of file t4_regs.h.

#define HPZ0_SHIFT   0

Definition at line 918 of file t4_regs.h.

#define HPZ1 (   x)    ((x) << HPZ1_SHIFT)

Definition at line 916 of file t4_regs.h.

#define HPZ1_MASK   0x00000f00U

Definition at line 914 of file t4_regs.h.

#define HPZ1_SHIFT   8

Definition at line 915 of file t4_regs.h.

#define HPZ2 (   x)    ((x) << HPZ2_SHIFT)

Definition at line 913 of file t4_regs.h.

#define HPZ2_MASK   0x000f0000U

Definition at line 911 of file t4_regs.h.

#define HPZ2_SHIFT   16

Definition at line 912 of file t4_regs.h.

#define HPZ3 (   x)    ((x) << HPZ3_SHIFT)

Definition at line 910 of file t4_regs.h.

#define HPZ3_MASK   0x0f000000U

Definition at line 908 of file t4_regs.h.

#define HPZ3_SHIFT   24

Definition at line 909 of file t4_regs.h.

#define HREQPERR   0x00020000U

Definition at line 294 of file t4_regs.h.

#define HRSPPERR   0x00040000U

Definition at line 293 of file t4_regs.h.

#define I2CM   0x00000002U

Definition at line 981 of file t4_regs.h.

#define IBQNCSIPARERR   0x00000800U

Definition at line 449 of file t4_regs.h.

#define IBQPARERR   0x0001f800U

Definition at line 443 of file t4_regs.h.

#define IBQSGEHIPARERR   0x00001000U

Definition at line 448 of file t4_regs.h.

#define IBQSGELOPARERR   0x00002000U

Definition at line 447 of file t4_regs.h.

#define IBQTP0PARERR   0x00010000U

Definition at line 444 of file t4_regs.h.

#define IBQTP1PARERR   0x00008000U

Definition at line 445 of file t4_regs.h.

#define IBQULPPARERR   0x00004000U

Definition at line 446 of file t4_regs.h.

#define ICSPI_PAR_ERROR   0x00000002U

Definition at line 643 of file t4_regs.h.

#define IESPI_PAR_ERROR   0x00000002U

Definition at line 633 of file t4_regs.h.

#define ILLRDBEINT   0x00000010U

Definition at line 487 of file t4_regs.h.

#define ILLRDINT   0x00000008U

Definition at line 488 of file t4_regs.h.

#define ILLTRANSINT   0x00000002U

Definition at line 490 of file t4_regs.h.

#define ILLWRBEINT   0x00000020U

Definition at line 486 of file t4_regs.h.

#define ILLWRINT   0x00000004U

Definition at line 489 of file t4_regs.h.

#define INGPADBOUNDARY (   x)    ((x) << INGPADBOUNDARY_SHIFT)

Definition at line 109 of file t4_regs.h.

#define INGPADBOUNDARY_GET (   x)
Value:
(((x) & INGPADBOUNDARY_MASK) \
>> INGPADBOUNDARY_SHIFT)

Definition at line 110 of file t4_regs.h.

#define INGPADBOUNDARY_MASK   0x00000070U

Definition at line 107 of file t4_regs.h.

#define INGPADBOUNDARY_SHIFT   4

Definition at line 108 of file t4_regs.h.

#define INGPCIEBOUNDARY (   x)    ((x) << INGPCIEBOUNDARY_SHIFT)

Definition at line 106 of file t4_regs.h.

#define INGPCIEBOUNDARY_MASK   0x00000380U

Definition at line 104 of file t4_regs.h.

#define INGPCIEBOUNDARY_SHIFT   7

Definition at line 105 of file t4_regs.h.

#define INGRESS_SIZE_ERR   0x00000020U

Definition at line 184 of file t4_regs.h.

#define INGRESSQID (   x)    ((x) << INGRESSQID_SHIFT)

Definition at line 78 of file t4_regs.h.

#define INGRESSQID_MASK   0xffff0000U

Definition at line 76 of file t4_regs.h.

#define INGRESSQID_SHIFT   16

Definition at line 77 of file t4_regs.h.

#define INTXCLRPERR   0x00200000U

Definition at line 290 of file t4_regs.h.

#define ISVF   0x00000080U

Definition at line 948 of file t4_regs.h.

#define KEEPALIVEMAXR1 (   x)    ((x) << KEEPALIVEMAXR1_SHIFT)

Definition at line 546 of file t4_regs.h.

#define KEEPALIVEMAXR1_GET (   x)
Value:
(((x) & KEEPALIVEMAXR1_MASK) >> \
KEEPALIVEMAXR1_SHIFT)

Definition at line 547 of file t4_regs.h.

#define KEEPALIVEMAXR1_MASK   0x000000f0U

Definition at line 545 of file t4_regs.h.

#define KEEPALIVEMAXR1_SHIFT   4

Definition at line 544 of file t4_regs.h.

#define KEEPALIVEMAXR2 (   x)    ((x) << KEEPALIVEMAXR2_SHIFT)

Definition at line 551 of file t4_regs.h.

#define KEEPALIVEMAXR2_GET (   x)
Value:
(((x) & KEEPALIVEMAXR2_MASK) >> \
KEEPALIVEMAXR2_SHIFT)

Definition at line 552 of file t4_regs.h.

#define KEEPALIVEMAXR2_MASK   0x0000000fU

Definition at line 550 of file t4_regs.h.

#define KEEPALIVEMAXR2_SHIFT   0

Definition at line 549 of file t4_regs.h.

#define LE   0x00040000U

Definition at line 964 of file t4_regs.h.

#define LE_DB_ACT_CNT_IPV4   0x19c20

Definition at line 999 of file t4_regs.h.

#define LE_DB_ACT_CNT_IPV6   0x19c24

Definition at line 1000 of file t4_regs.h.

#define LE_DB_CONFIG   0x19c04

Definition at line 995 of file t4_regs.h.

#define LE_DB_INT_CAUSE   0x19c3c

Definition at line 1002 of file t4_regs.h.

#define LE_DB_SERVER_INDEX   0x19c18

Definition at line 998 of file t4_regs.h.

#define LE_DB_TID_HASHBASE   0x19df8

Definition at line 1009 of file t4_regs.h.

#define LIP0   0x00000010U

Definition at line 1007 of file t4_regs.h.

#define LIPMISS   0x00000020U

Definition at line 1006 of file t4_regs.h.

#define LKPTBLQUEUE0 (   x)    ((x) << LKPTBLQUEUE0_SHIFT)

Definition at line 577 of file t4_regs.h.

#define LKPTBLQUEUE0_GET (   x)    (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)

Definition at line 578 of file t4_regs.h.

#define LKPTBLQUEUE0_MASK   0x000003ffU

Definition at line 575 of file t4_regs.h.

#define LKPTBLQUEUE0_SHIFT   0

Definition at line 576 of file t4_regs.h.

#define LKPTBLQUEUE1 (   x)    ((x) << LKPTBLQUEUE1_SHIFT)

Definition at line 573 of file t4_regs.h.

#define LKPTBLQUEUE1_GET (   x)    (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)

Definition at line 574 of file t4_regs.h.

#define LKPTBLQUEUE1_MASK   0x000ffc00U

Definition at line 571 of file t4_regs.h.

#define LKPTBLQUEUE1_SHIFT   10

Definition at line 572 of file t4_regs.h.

#define LKPTBLROWVLD   0x80000000U

Definition at line 570 of file t4_regs.h.

#define LOOKUPEVERYPKT   0x00000100U

Definition at line 605 of file t4_regs.h.

#define M_HP_COUNT   0x7ffU

Definition at line 258 of file t4_regs.h.

#define M_HP_INT_THRESH   0xfU

Definition at line 256 of file t4_regs.h.

#define M_LP_COUNT   0x7ffU

Definition at line 264 of file t4_regs.h.

#define M_LP_INT_THRESH   0xfU

Definition at line 262 of file t4_regs.h.

#define MA   0x00100000U

Definition at line 962 of file t4_regs.h.

#define MA_EXT_MEMORY_BAR   0x77c8

Definition at line 382 of file t4_regs.h.

#define MA_INT_CAUSE   0x77e0

Definition at line 392 of file t4_regs.h.

#define MA_INT_WRAP_STATUS   0x77e4

Definition at line 396 of file t4_regs.h.

#define MA_PARITY_ERROR_STATUS   0x77f4

Definition at line 404 of file t4_regs.h.

#define MA_PCIE_FW   0x30b8

Definition at line 403 of file t4_regs.h.

#define MA_TARGET_MEM_ENABLE   0x77d8

Definition at line 387 of file t4_regs.h.

#define MACMATCH_MASK   0x00000080U

Definition at line 591 of file t4_regs.h.

#define MAGICEN   0x00020000U

Definition at line 1019 of file t4_regs.h.

#define MATAGPERR   0x00400000U

Definition at line 289 of file t4_regs.h.

#define MATCHSRAM   0x00000001U

Definition at line 888 of file t4_regs.h.

#define MATCHTCAM   0x00000002U

Definition at line 887 of file t4_regs.h.

#define MAXRXDATA_GET (   x)    (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)

Definition at line 507 of file t4_regs.h.

#define MAXRXDATA_MASK   0xffff0000U

Definition at line 505 of file t4_regs.h.

#define MAXRXDATA_SHIFT   16

Definition at line 506 of file t4_regs.h.

#define MBHOSTPARERR   0x00040000U

Definition at line 441 of file t4_regs.h.

#define MBINTREQ   0x00000004U

Definition at line 429 of file t4_regs.h.

#define MBMSGRDYINT   0x00080000U

Definition at line 436 of file t4_regs.h.

#define MBMSGVALID   0x00000008U

Definition at line 428 of file t4_regs.h.

#define MBOWNER (   x)    ((x) << MBOWNER_SHIFT)

Definition at line 432 of file t4_regs.h.

#define MBOWNER_GET (   x)    (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)

Definition at line 433 of file t4_regs.h.

#define MBOWNER_MASK   0x00000003U

Definition at line 430 of file t4_regs.h.

#define MBOWNER_SHIFT   0

Definition at line 431 of file t4_regs.h.

#define MBUPPARERR   0x00020000U

Definition at line 442 of file t4_regs.h.

#define MC   0x00008000U

Definition at line 967 of file t4_regs.h.

#define MC_BIST_CMD   0x7600

Definition at line 364 of file t4_regs.h.

#define MC_BIST_CMD_ADDR   0x7604

Definition at line 373 of file t4_regs.h.

#define MC_BIST_CMD_LEN   0x7608

Definition at line 374 of file t4_regs.h.

#define MC_BIST_DATA_PATTERN   0x760c

Definition at line 375 of file t4_regs.h.

#define MC_BIST_STATUS_RDATA   0x7688

Definition at line 380 of file t4_regs.h.

#define MC_BIST_STATUS_REG (   reg_addr,
  idx 
)    ((reg_addr) + (idx) * 4)

Definition at line 63 of file t4_regs.h.

#define MC_ECC_STATUS   0x751c

Definition at line 354 of file t4_regs.h.

#define MC_INT_CAUSE   0x7518

Definition at line 349 of file t4_regs.h.

#define MEM_PERR_INT_CAUSE   0x00000002U

Definition at line 393 of file t4_regs.h.

#define MEM_WRAP_ADDRESS_GET (   x)    (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)

Definition at line 399 of file t4_regs.h.

#define MEM_WRAP_ADDRESS_MASK   0xfffffff0U

Definition at line 397 of file t4_regs.h.

#define MEM_WRAP_ADDRESS_SHIFT   4

Definition at line 398 of file t4_regs.h.

#define MEM_WRAP_CLIENT_NUM_GET (   x)    (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)

Definition at line 402 of file t4_regs.h.

#define MEM_WRAP_CLIENT_NUM_MASK   0x0000000fU

Definition at line 400 of file t4_regs.h.

#define MEM_WRAP_CLIENT_NUM_SHIFT   0

Definition at line 401 of file t4_regs.h.

#define MEM_WRAP_INT_CAUSE   0x00000001U

Definition at line 394 of file t4_regs.h.

#define MI   0x00000008U

Definition at line 979 of file t4_regs.h.

#define MISCPERR   0x00000100U

Definition at line 877 of file t4_regs.h.

#define MPS   0x00000010U

Definition at line 978 of file t4_regs.h.

#define MPS_CLS_INT_CAUSE   0xd028

Definition at line 884 of file t4_regs.h.

#define MPS_CMN_CTL   0x9000

Definition at line 773 of file t4_regs.h.

#define MPS_DM_PRTY_ERR   0x00000080U

Definition at line 1013 of file t4_regs.h.

#define MPS_INT_CAUSE   0x9008

Definition at line 778 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H   0x51c

Definition at line 715 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L   0x518

Definition at line 714 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_128B_255B_H   0x504

Definition at line 709 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_128B_255B_L   0x500

Definition at line 708 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H   0x524

Definition at line 717 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L   0x520

Definition at line 716 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_256B_511B_H   0x50c

Definition at line 711 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_256B_511B_L   0x508

Definition at line 710 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_512B_1023B_H   0x514

Definition at line 713 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_512B_1023B_L   0x510

Definition at line 712 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_64B_H   0x4f4

Definition at line 705 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_64B_L   0x4f0

Definition at line 704 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_65B_127B_H   0x4fc

Definition at line 707 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_65B_127B_L   0x4f8

Definition at line 706 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_BCAST_H   0x4d4

Definition at line 697 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_BCAST_L   0x4d0

Definition at line 696 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_BYTES_H   0x4c4

Definition at line 693 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_BYTES_L   0x4c0

Definition at line 692 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES   0x528

Definition at line 718 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_ERROR_H   0x4ec

Definition at line 703 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_ERROR_L   0x4e8

Definition at line 702 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_FRAMES_H   0x4cc

Definition at line 695 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_FRAMES_L   0x4c8

Definition at line 694 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_MCAST_H   0x4dc

Definition at line 699 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_MCAST_L   0x4d8

Definition at line 698 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_UCAST_H   0x4e4

Definition at line 701 of file t4_regs.h.

#define MPS_PORT_STAT_LB_PORT_UCAST_L   0x4e0

Definition at line 700 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H   0x5bc

Definition at line 750 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L   0x5b8

Definition at line 749 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_128B_255B_H   0x5a4

Definition at line 744 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_128B_255B_L   0x5a0

Definition at line 743 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H   0x5c4

Definition at line 752 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L   0x5c0

Definition at line 751 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_256B_511B_H   0x5ac

Definition at line 746 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_256B_511B_L   0x5a8

Definition at line 745 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_512B_1023B_H   0x5b4

Definition at line 748 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_512B_1023B_L   0x5b0

Definition at line 747 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_64B_H   0x594

Definition at line 740 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_64B_L   0x590

Definition at line 739 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_65B_127B_H   0x59c

Definition at line 742 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_65B_127B_L   0x598

Definition at line 741 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_BCAST_H   0x554

Definition at line 724 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_BCAST_L   0x550

Definition at line 723 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_BYTES_H   0x544

Definition at line 720 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_BYTES_L   0x540

Definition at line 719 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H   0x57c

Definition at line 734 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L   0x578

Definition at line 733 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_FRAMES_H   0x54c

Definition at line 722 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_FRAMES_L   0x548

Definition at line 721 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H   0x584

Definition at line 736 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L   0x580

Definition at line 735 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_LESS_64B_H   0x614

Definition at line 772 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_LESS_64B_L   0x610

Definition at line 771 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_MCAST_H   0x55c

Definition at line 726 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_MCAST_L   0x558

Definition at line 725 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H   0x574

Definition at line 732 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L   0x570

Definition at line 731 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H   0x56c

Definition at line 730 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L   0x568

Definition at line 729 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PAUSE_H   0x5cc

Definition at line 754 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PAUSE_L   0x5c8

Definition at line 753 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP0_H   0x5d4

Definition at line 756 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP0_L   0x5d0

Definition at line 755 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP1_H   0x5dc

Definition at line 758 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP1_L   0x5d8

Definition at line 757 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP2_H   0x5e4

Definition at line 760 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP2_L   0x5e0

Definition at line 759 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP3_H   0x5ec

Definition at line 762 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP3_L   0x5e8

Definition at line 761 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP4_H   0x5f4

Definition at line 764 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP4_L   0x5f0

Definition at line 763 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP5_H   0x5fc

Definition at line 766 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP5_L   0x5f8

Definition at line 765 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP6_H   0x604

Definition at line 768 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP6_L   0x600

Definition at line 767 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP7_H   0x60c

Definition at line 770 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_PPP7_L   0x608

Definition at line 769 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H   0x58c

Definition at line 738 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L   0x588

Definition at line 737 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_UCAST_H   0x564

Definition at line 728 of file t4_regs.h.

#define MPS_PORT_STAT_RX_PORT_UCAST_L   0x560

Definition at line 727 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H   0x45c

Definition at line 669 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L   0x458

Definition at line 668 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_128B_255B_H   0x444

Definition at line 663 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_128B_255B_L   0x440

Definition at line 662 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H   0x464

Definition at line 671 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L   0x460

Definition at line 670 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_256B_511B_H   0x44c

Definition at line 665 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_256B_511B_L   0x448

Definition at line 664 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_512B_1023B_H   0x454

Definition at line 667 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_512B_1023B_L   0x450

Definition at line 666 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_64B_H   0x434

Definition at line 659 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_64B_L   0x430

Definition at line 658 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_65B_127B_H   0x43c

Definition at line 661 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_65B_127B_L   0x438

Definition at line 660 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_BCAST_H   0x414

Definition at line 651 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_BCAST_L   0x410

Definition at line 650 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_BYTES_H   0x404

Definition at line 647 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_BYTES_L   0x400

Definition at line 646 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_DROP_H   0x46c

Definition at line 673 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_DROP_L   0x468

Definition at line 672 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_ERROR_H   0x42c

Definition at line 657 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_ERROR_L   0x428

Definition at line 656 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_FRAMES_H   0x40c

Definition at line 649 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_FRAMES_L   0x408

Definition at line 648 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_MCAST_H   0x41c

Definition at line 653 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_MCAST_L   0x418

Definition at line 652 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PAUSE_H   0x474

Definition at line 675 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PAUSE_L   0x470

Definition at line 674 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP0_H   0x47c

Definition at line 677 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP0_L   0x478

Definition at line 676 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP1_H   0x484

Definition at line 679 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP1_L   0x480

Definition at line 678 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP2_H   0x48c

Definition at line 681 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP2_L   0x488

Definition at line 680 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP3_H   0x494

Definition at line 683 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP3_L   0x490

Definition at line 682 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP4_H   0x49c

Definition at line 685 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP4_L   0x498

Definition at line 684 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP5_H   0x4a4

Definition at line 687 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP5_L   0x4a0

Definition at line 686 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP6_H   0x4ac

Definition at line 689 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP6_L   0x4a8

Definition at line 688 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP7_H   0x4b4

Definition at line 691 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_PPP7_L   0x4b0

Definition at line 690 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_UCAST_H   0x424

Definition at line 655 of file t4_regs.h.

#define MPS_PORT_STAT_TX_PORT_UCAST_L   0x420

Definition at line 654 of file t4_regs.h.

#define MPS_RX_PERR_INT_CAUSE   0x11074

Definition at line 890 of file t4_regs.h.

#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO   0x962c

Definition at line 798 of file t4_regs.h.

#define MPS_STAT_PERR_INT_CAUSE_SRAM   0x9614

Definition at line 796 of file t4_regs.h.

#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO   0x9620

Definition at line 797 of file t4_regs.h.

#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H   0x9664

Definition at line 809 of file t4_regs.h.

#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L   0x9660

Definition at line 808 of file t4_regs.h.

#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H   0x96a4

Definition at line 825 of file t4_regs.h.

#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L   0x96a0

Definition at line 824 of file t4_regs.h.

#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H   0x9644

Definition at line 801 of file t4_regs.h.

#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L   0x9640

Definition at line 800 of file t4_regs.h.

#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H   0x9684

Definition at line 817 of file t4_regs.h.

#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L   0x9680

Definition at line 816 of file t4_regs.h.

#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H   0x966c

Definition at line 811 of file t4_regs.h.

#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L   0x9668

Definition at line 810 of file t4_regs.h.

#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H   0x96ac

Definition at line 827 of file t4_regs.h.

#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L   0x96a8

Definition at line 826 of file t4_regs.h.

#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H   0x964c

Definition at line 803 of file t4_regs.h.

#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L   0x9648

Definition at line 802 of file t4_regs.h.

#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H   0x968c

Definition at line 819 of file t4_regs.h.

#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L   0x9688

Definition at line 818 of file t4_regs.h.

#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H   0x9674

Definition at line 813 of file t4_regs.h.

#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L   0x9670

Definition at line 812 of file t4_regs.h.

#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H   0x96b4

Definition at line 829 of file t4_regs.h.

#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L   0x96b0

Definition at line 828 of file t4_regs.h.

#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H   0x9654

Definition at line 805 of file t4_regs.h.

#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L   0x9650

Definition at line 804 of file t4_regs.h.

#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H   0x9694

Definition at line 821 of file t4_regs.h.

#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L   0x9690

Definition at line 820 of file t4_regs.h.

#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H   0x967c

Definition at line 815 of file t4_regs.h.

#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L   0x9678

Definition at line 814 of file t4_regs.h.

#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H   0x96bc

Definition at line 831 of file t4_regs.h.

#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L   0x96b8

Definition at line 830 of file t4_regs.h.

#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H   0x965c

Definition at line 807 of file t4_regs.h.

#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L   0x9658

Definition at line 806 of file t4_regs.h.

#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H   0x969c

Definition at line 823 of file t4_regs.h.

#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L   0x9698

Definition at line 822 of file t4_regs.h.

#define MPS_TRC_CFG   0x9800

Definition at line 832 of file t4_regs.h.

#define MPS_TRC_FILTER0_DONT_CARE   0x9c80

Definition at line 882 of file t4_regs.h.

#define MPS_TRC_FILTER0_MATCH   0x9c00

Definition at line 881 of file t4_regs.h.

#define MPS_TRC_FILTER1_MATCH   0x9d00

Definition at line 883 of file t4_regs.h.

#define MPS_TRC_FILTER_MATCH_CTL_A   0x9810

Definition at line 847 of file t4_regs.h.

#define MPS_TRC_FILTER_MATCH_CTL_B   0x9820

Definition at line 866 of file t4_regs.h.

#define MPS_TRC_INT_CAUSE   0x985c

Definition at line 876 of file t4_regs.h.

#define MPS_TRC_RSS_CONTROL   0x9808

Definition at line 839 of file t4_regs.h.

#define MPS_TX_INT_CAUSE   0x9408

Definition at line 786 of file t4_regs.h.

#define MPSHITTYPE_MASK   0x00000100U

Definition at line 590 of file t4_regs.h.

#define MSIADDRHPERR   0x00000002U

Definition at line 310 of file t4_regs.h.

#define MSIADDRLPERR   0x00000001U

Definition at line 311 of file t4_regs.h.

#define MSIDATAPERR   0x00000004U

Definition at line 309 of file t4_regs.h.

#define MSIXADDRHPERR   0x00000010U

Definition at line 307 of file t4_regs.h.

#define MSIXADDRLPERR   0x00000008U

Definition at line 308 of file t4_regs.h.

#define MSIXDATAPERR   0x00000020U

Definition at line 306 of file t4_regs.h.

#define MSIXDIPERR   0x00000040U

Definition at line 305 of file t4_regs.h.

#define MSTRXFIFOPARINT   0x00100000U

Definition at line 902 of file t4_regs.h.

#define MSTTXFIFOPARINT   0x00200000U

Definition at line 901 of file t4_regs.h.

#define MTUINDEX (   x)    ((x) << MTUINDEX_SHIFT)

Definition at line 559 of file t4_regs.h.

#define MTUINDEX_MASK   0xff000000U

Definition at line 557 of file t4_regs.h.

#define MTUINDEX_SHIFT   24

Definition at line 558 of file t4_regs.h.

#define MTUVALUE (   x)    ((x) << MTUVALUE_SHIFT)

Definition at line 566 of file t4_regs.h.

#define MTUVALUE_GET (   x)    (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)

Definition at line 567 of file t4_regs.h.

#define MTUVALUE_MASK   0x00003fffU

Definition at line 564 of file t4_regs.h.

#define MTUVALUE_SHIFT   0

Definition at line 565 of file t4_regs.h.

#define MTUWIDTH (   x)    ((x) << MTUWIDTH_SHIFT)

Definition at line 562 of file t4_regs.h.

#define MTUWIDTH_GET (   x)    (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)

Definition at line 563 of file t4_regs.h.

#define MTUWIDTH_MASK   0x000f0000U

Definition at line 560 of file t4_regs.h.

#define MTUWIDTH_SHIFT   16

Definition at line 561 of file t4_regs.h.

#define MYPF_BASE   0x1b000

Definition at line 38 of file t4_regs.h.

#define MYPF_REG (   reg_addr)    (MYPF_BASE + (reg_addr))

Definition at line 39 of file t4_regs.h.

#define MYPORT_BASE   0x1c000

Definition at line 48 of file t4_regs.h.

#define MYPORT_REG (   reg_addr)    (MYPORT_BASE + (reg_addr))

Definition at line 49 of file t4_regs.h.

#define NCSI   0x00000020U

Definition at line 977 of file t4_regs.h.

#define NCSI_INT_CAUSE   0x1a0d8

Definition at line 1011 of file t4_regs.h.

#define NCSIFIFO   0x00000010U

Definition at line 793 of file t4_regs.h.

#define NUMPORTS_GET (   x)    (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)

Definition at line 776 of file t4_regs.h.

#define NUMPORTS_MASK   0x00000003U

Definition at line 774 of file t4_regs.h.

#define NUMPORTS_SHIFT   0

Definition at line 775 of file t4_regs.h.

#define OBQNCSIPARERR   0x00000020U

Definition at line 456 of file t4_regs.h.

#define OBQPARERR   0x000007e0U

Definition at line 450 of file t4_regs.h.

#define OBQSGEPARERR   0x00000040U

Definition at line 455 of file t4_regs.h.

#define OBQULP0PARERR   0x00000400U

Definition at line 451 of file t4_regs.h.

#define OBQULP1PARERR   0x00000200U

Definition at line 452 of file t4_regs.h.

#define OBQULP2PARERR   0x00000100U

Definition at line 453 of file t4_regs.h.

#define OBQULP3PARERR   0x00000080U

Definition at line 454 of file t4_regs.h.

#define OCSPI_PAR_ERROR   0x00000008U

Definition at line 631 of file t4_regs.h.

#define OESPI_PAR_ERROR   0x00000008U

Definition at line 642 of file t4_regs.h.

#define OP_WR   0x00000001U

Definition at line 931 of file t4_regs.h.

#define OTDD   0x00200000U

Definition at line 343 of file t4_regs.h.

#define PARITYERR   0x00000040U

Definition at line 1005 of file t4_regs.h.

#define PATEN   0x00040000U

Definition at line 1018 of file t4_regs.h.

#define PBL_BOUND_ERR_CH0   0x10000000U

Definition at line 626 of file t4_regs.h.

#define PBL_BOUND_ERR_CH1   0x20000000U

Definition at line 625 of file t4_regs.h.

#define PBL_BOUND_ERR_CH2   0x40000000U

Definition at line 624 of file t4_regs.h.

#define PBL_BOUND_ERR_CH3   0x80000000U

Definition at line 623 of file t4_regs.h.

#define PCIE   0x00004000U

Definition at line 968 of file t4_regs.h.

#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS   0x59a4

Definition at line 334 of file t4_regs.h.

#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS   0x5908

Definition at line 326 of file t4_regs.h.

#define PCIE_FW   0x30b8

Definition at line 324 of file t4_regs.h.

#define PCIE_INT_CAUSE   0x3004

Definition at line 281 of file t4_regs.h.

#define PCIE_MAILBOX_REG (   reg_addr,
  idx 
)    ((reg_addr) + (idx) * 8)

Definition at line 62 of file t4_regs.h.

#define PCIE_MEM_ACCESS_BASE_WIN   0x3068

Definition at line 314 of file t4_regs.h.

#define PCIE_MEM_ACCESS_OFFSET   0x306c

Definition at line 322 of file t4_regs.h.

#define PCIE_MEM_ACCESS_REG (   reg_addr,
  idx 
)    ((reg_addr) + (idx) * 8)

Definition at line 61 of file t4_regs.h.

#define PCIE_NONFAT_ERR   0x3010

Definition at line 313 of file t4_regs.h.

#define PCIE_PF_CLI   0x44

Definition at line 280 of file t4_regs.h.

#define PCIEOFST_MASK   0xfffffc00U

Definition at line 315 of file t4_regs.h.

#define PCIEPINT   0x10000000U

Definition at line 283 of file t4_regs.h.

#define PCIESINT   0x08000000U

Definition at line 284 of file t4_regs.h.

#define PCMD_LEN_OVFL0   0x80000000U

Definition at line 637 of file t4_regs.h.

#define PCMD_LEN_OVFL1   0x40000000U

Definition at line 638 of file t4_regs.h.

#define PCMD_LEN_OVFL2   0x20000000U

Definition at line 639 of file t4_regs.h.

#define PERR_INT_CAUSE   0x00000001U

Definition at line 352 of file t4_regs.h.

#define PERR_PAR_CAUSE   0x00000008U

Definition at line 416 of file t4_regs.h.

#define PERRVFID   0x00000001U

Definition at line 991 of file t4_regs.h.

#define PERSHIFTBACKOFFMAX (   x)    ((x) << PERSHIFTBACKOFFMAX_SHIFT)

Definition at line 536 of file t4_regs.h.

#define PERSHIFTBACKOFFMAX_GET (   x)
Value:
(((x) & PERSHIFTBACKOFFMAX_MASK) >> \
PERSHIFTBACKOFFMAX_SHIFT)

Definition at line 537 of file t4_regs.h.

#define PERSHIFTBACKOFFMAX_MASK   0x0000f000U

Definition at line 535 of file t4_regs.h.

#define PERSHIFTBACKOFFMAX_SHIFT   12

Definition at line 534 of file t4_regs.h.

#define PERSHIFTMAX (   x)    ((x) << PERSHIFTMAX_SHIFT)

Definition at line 541 of file t4_regs.h.

#define PERSHIFTMAX_GET (   x)
Value:
(((x) & PERSHIFTMAX_MASK) >> \
PERSHIFTMAX_SHIFT)

Definition at line 542 of file t4_regs.h.

#define PERSHIFTMAX_MASK   0x00000f00U

Definition at line 540 of file t4_regs.h.

#define PERSHIFTMAX_SHIFT   8

Definition at line 539 of file t4_regs.h.

#define PF0_BASE   0x1e000

Definition at line 41 of file t4_regs.h.

#define PF0_REG (   reg_addr)    (PF0_BASE + (reg_addr))

Definition at line 42 of file t4_regs.h.

#define PF_BASE (   idx)    (PF0_BASE + (idx) * PF_STRIDE)

Definition at line 45 of file t4_regs.h.

#define PF_REG (   idx,
  reg 
)    (PF_BASE(idx) + (reg))

Definition at line 46 of file t4_regs.h.

#define PF_STRIDE   0x400

Definition at line 44 of file t4_regs.h.

#define PFCIM   0x00000002U

Definition at line 936 of file t4_regs.h.

#define PFMPS   0x00000001U

Definition at line 937 of file t4_regs.h.

#define PFSGE   0x00000004U

Definition at line 935 of file t4_regs.h.

#define PFSW   0x00000008U

Definition at line 934 of file t4_regs.h.

#define PIDX (   x)    ((x) << PIDX_SHIFT)

Definition at line 73 of file t4_regs.h.

#define PIDX_MASK   0x00003fffU

Definition at line 71 of file t4_regs.h.

#define PIDX_SHIFT   0

Definition at line 72 of file t4_regs.h.

#define PIOCPLPERR   0x00000080U

Definition at line 304 of file t4_regs.h.

#define PIOREQPERR   0x00000100U

Definition at line 303 of file t4_regs.h.

#define PIORST   0x00000002U

Definition at line 986 of file t4_regs.h.

#define PIORSTMODE   0x00000001U

Definition at line 987 of file t4_regs.h.

#define PIOTAGPERR   0x00800000U

Definition at line 288 of file t4_regs.h.

#define PKTFIFO   0x000000f0U

Definition at line 878 of file t4_regs.h.

#define PKTSHIFT (   x)    ((x) << PKTSHIFT_SHIFT)

Definition at line 102 of file t4_regs.h.

#define PKTSHIFT_GET (   x)    (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT)

Definition at line 103 of file t4_regs.h.

#define PKTSHIFT_MASK   0x00001c00U

Definition at line 100 of file t4_regs.h.

#define PKTSHIFT_SHIFT   10

Definition at line 101 of file t4_regs.h.

#define PL   0x00000040U

Definition at line 976 of file t4_regs.h.

#define PL_INT_CAUSE   0x1940c

Definition at line 954 of file t4_regs.h.

#define PL_INT_MAP0   0x19414

Definition at line 984 of file t4_regs.h.

#define PL_PF_CTL   0x3c8

Definition at line 940 of file t4_regs.h.

#define PL_PF_INT_CAUSE   0x3c0

Definition at line 933 of file t4_regs.h.

#define PL_PF_INT_ENABLE   0x3c4

Definition at line 939 of file t4_regs.h.

#define PL_PL_INT_CAUSE   0x19430

Definition at line 989 of file t4_regs.h.

#define PL_REV   0x1943c

Definition at line 993 of file t4_regs.h.

#define PL_RST   0x19428

Definition at line 985 of file t4_regs.h.

#define PL_WHOAMI   0x19400

Definition at line 943 of file t4_regs.h.

#define PLDN   0x00400000U

Definition at line 342 of file t4_regs.h.

#define PLERRENB   0x00000008U

Definition at line 885 of file t4_regs.h.

#define PLINT   0x00000001U

Definition at line 784 of file t4_regs.h.

#define PLUP   0x00800000U

Definition at line 341 of file t4_regs.h.

#define PM_RX   0x00400000U

Definition at line 960 of file t4_regs.h.

#define PM_RX_INT_CAUSE   0x8fdc

Definition at line 628 of file t4_regs.h.

#define PM_TX   0x00200000U

Definition at line 961 of file t4_regs.h.

#define PM_TX_INT_CAUSE   0x8ffc

Definition at line 636 of file t4_regs.h.

#define PMRX_FRAMING_ERROR   0x003ffff0U

Definition at line 630 of file t4_regs.h.

#define PMTX_FRAMING_ERROR   0x0ffffff0U

Definition at line 641 of file t4_regs.h.

#define PMU   0x00002000U

Definition at line 969 of file t4_regs.h.

#define PORT0_BASE   0x20000

Definition at line 51 of file t4_regs.h.

#define PORT0_REG (   reg_addr)    (PORT0_BASE + (reg_addr))

Definition at line 52 of file t4_regs.h.

#define PORT_BASE (   idx)    (PORT0_BASE + (idx) * PORT_STRIDE)

Definition at line 55 of file t4_regs.h.

#define PORT_MASK   0x00000002U

Definition at line 597 of file t4_regs.h.

#define PORT_REG (   idx,
  reg 
)    (PORT_BASE(idx) + (reg))

Definition at line 56 of file t4_regs.h.

#define PORT_STRIDE   0x2000

Definition at line 54 of file t4_regs.h.

#define PORTERR   0x00010000U

Definition at line 787 of file t4_regs.h.

#define PREFDROPINT   0x00000002U

Definition at line 457 of file t4_regs.h.

#define PROTOCOL_MASK   0x00000020U

Definition at line 593 of file t4_regs.h.

#define PTRP   0x00100000U

Definition at line 332 of file t4_regs.h.

#define QID (   x)    ((x) << QID_SHIFT)

Definition at line 69 of file t4_regs.h.

#define QID_MASK   0xffff8000U

Definition at line 67 of file t4_regs.h.

#define QID_SHIFT   15

Definition at line 68 of file t4_regs.h.

#define QUEUENUMBER (   x)    ((x) << QUEUENUMBER_SHIFT)

Definition at line 845 of file t4_regs.h.

#define QUEUENUMBER_MASK   0x0000ffffU

Definition at line 843 of file t4_regs.h.

#define QUEUENUMBER_SHIFT   0

Definition at line 844 of file t4_regs.h.

#define QUEUESPERPAGEPF0_GET (   x)    ((x) & QUEUESPERPAGEPF0_MASK)

Definition at line 153 of file t4_regs.h.

#define QUEUESPERPAGEPF0_MASK   0x0000000fU

Definition at line 152 of file t4_regs.h.

#define RCAP   0x02000000U

Definition at line 340 of file t4_regs.h.

#define RCCP   0x04000000U

Definition at line 330 of file t4_regs.h.

#define RCIP   0x08000000U

Definition at line 329 of file t4_regs.h.

#define RDPE   0x00040000U

Definition at line 345 of file t4_regs.h.

#define REG_ADDRESS_ERR   0x00000040U

Definition at line 183 of file t4_regs.h.

#define REQOVRLOOKUPINT   0x04000000U

Definition at line 465 of file t4_regs.h.

#define REQQPARERR   0x00010000U

Definition at line 1003 of file t4_regs.h.

#define RFTP   0x00800000U

Definition at line 331 of file t4_regs.h.

#define RM_OVLAN   0x00000200U

Definition at line 604 of file t4_regs.h.

#define RNPP   0x80000000U

Definition at line 327 of file t4_regs.h.

#define RPCP   0x20000000U

Definition at line 328 of file t4_regs.h.

#define RPLPERR   0x04000000U

Definition at line 285 of file t4_regs.h.

#define RSPOVRLOOKUPINT   0x08000000U

Definition at line 464 of file t4_regs.h.

#define RSSCONTROL (   x)    ((x) << RSSCONTROL_SHIFT)

Definition at line 842 of file t4_regs.h.

#define RSSCONTROL_MASK   0x00ff0000U

Definition at line 840 of file t4_regs.h.

#define RSSCONTROL_SHIFT   16

Definition at line 841 of file t4_regs.h.

#define RSVDSPACEINT   0x00000001U

Definition at line 491 of file t4_regs.h.

#define RXCPLPERR   0x01000000U

Definition at line 287 of file t4_regs.h.

#define RXFIFO_PRTY_ERR   0x00000001U

Definition at line 1015 of file t4_regs.h.

#define RXINT   0x00000008U

Definition at line 781 of file t4_regs.h.

#define RXPKTCPLMODE (   x)    ((x) << RXPKTCPLMODE_SHIFT)

Definition at line 96 of file t4_regs.h.

#define RXPKTCPLMODE_MASK   0x00040000U

Definition at line 94 of file t4_regs.h.

#define RXPKTCPLMODE_SHIFT   18

Definition at line 95 of file t4_regs.h.

#define RXTSHIFTMAXR1 (   x)    ((x) << RXTSHIFTMAXR1_SHIFT)

Definition at line 526 of file t4_regs.h.

#define RXTSHIFTMAXR1_GET (   x)
Value:
(((x) & RXTSHIFTMAXR1_MASK) >> \
RXTSHIFTMAXR1_SHIFT)

Definition at line 527 of file t4_regs.h.

#define RXTSHIFTMAXR1_MASK   0x00f00000U

Definition at line 525 of file t4_regs.h.

#define RXTSHIFTMAXR1_SHIFT   20

Definition at line 524 of file t4_regs.h.

#define RXTSHIFTMAXR2 (   x)    ((x) << RXTSHIFTMAXR2_SHIFT)

Definition at line 531 of file t4_regs.h.

#define RXTSHIFTMAXR2_GET (   x)
Value:
(((x) & RXTSHIFTMAXR2_MASK) >> \
RXTSHIFTMAXR2_SHIFT)

Definition at line 532 of file t4_regs.h.

#define RXTSHIFTMAXR2_MASK   0x000f0000U

Definition at line 530 of file t4_regs.h.

#define RXTSHIFTMAXR2_SHIFT   16

Definition at line 529 of file t4_regs.h.

#define RXWRPERR   0x02000000U

Definition at line 286 of file t4_regs.h.

#define S_DROPPED_DB   0

Definition at line 272 of file t4_regs.h.

#define S_ENABLE_DROP   13

Definition at line 269 of file t4_regs.h.

#define S_HP_COUNT   16

Definition at line 259 of file t4_regs.h.

#define S_HP_INT_THRESH   28

Definition at line 255 of file t4_regs.h.

#define S_LP_COUNT   0

Definition at line 265 of file t4_regs.h.

#define S_LP_INT_THRESH   12

Definition at line 261 of file t4_regs.h.

#define SECNTERR   0x00004000U

Definition at line 789 of file t4_regs.h.

#define SEINTARM (   x)    ((x) << SEINTARM_SHIFT)

Definition at line 84 of file t4_regs.h.

#define SEINTARM_MASK   0x00001000U

Definition at line 82 of file t4_regs.h.

#define SEINTARM_SHIFT   12

Definition at line 83 of file t4_regs.h.

#define SF   0x00000080U

Definition at line 975 of file t4_regs.h.

#define SF_CONT   0x00000008U

Definition at line 927 of file t4_regs.h.

#define SF_DATA   0x193f8

Definition at line 923 of file t4_regs.h.

#define SF_LOCK   0x00000010U

Definition at line 926 of file t4_regs.h.

#define SF_OP   0x193fc

Definition at line 924 of file t4_regs.h.

#define SGE   0x04000000U

Definition at line 956 of file t4_regs.h.

#define SGE_CONM_CTRL   0x1094

Definition at line 214 of file t4_regs.h.

#define SGE_CONTROL   0x1008

Definition at line 92 of file t4_regs.h.

#define SGE_DEBUG_DATA_HIGH   0x10d0

Definition at line 251 of file t4_regs.h.

#define SGE_DEBUG_DATA_LOW   0x10d4

Definition at line 252 of file t4_regs.h.

#define SGE_DEBUG_INDEX   0x10cc

Definition at line 250 of file t4_regs.h.

#define SGE_EGRESS_QUEUES_PER_PAGE_PF   0x1010

Definition at line 151 of file t4_regs.h.

#define SGE_FL_BUFFER_SIZE0   0x1044

Definition at line 192 of file t4_regs.h.

#define SGE_FL_BUFFER_SIZE1   0x1048

Definition at line 193 of file t4_regs.h.

#define SGE_FL_BUFFER_SIZE2   0x104c

Definition at line 194 of file t4_regs.h.

#define SGE_FL_BUFFER_SIZE3   0x1050

Definition at line 195 of file t4_regs.h.

#define SGE_FRAMING_ERROR   0x00000004U

Definition at line 896 of file t4_regs.h.

#define SGE_HOST_PAGE_SIZE   0x100c

Definition at line 117 of file t4_regs.h.

#define SGE_INGRESS_QUEUES_PER_PAGE_PF   0x10f4

Definition at line 253 of file t4_regs.h.

#define SGE_INGRESS_RX_THRESHOLD   0x10a0

Definition at line 196 of file t4_regs.h.

#define SGE_INT_CAUSE1   0x1024

Definition at line 155 of file t4_regs.h.

#define SGE_INT_CAUSE2   0x1030

Definition at line 156 of file t4_regs.h.

#define SGE_INT_CAUSE3   0x103c

Definition at line 157 of file t4_regs.h.

#define SGE_INT_ENABLE3   0x1040

Definition at line 191 of file t4_regs.h.

#define SGE_PF_GTS   0x4

Definition at line 75 of file t4_regs.h.

#define SGE_PF_KDOORBELL   0x0

Definition at line 66 of file t4_regs.h.

#define SGE_TIMER_VALUE_0_AND_1   0x10b8

Definition at line 220 of file t4_regs.h.

#define SGE_TIMER_VALUE_2_AND_3   0x10bc

Definition at line 230 of file t4_regs.h.

#define SGE_TIMER_VALUE_4_AND_5   0x10c0

Definition at line 240 of file t4_regs.h.

#define SGLRDBOOTINT   0x00000040U

Definition at line 485 of file t4_regs.h.

#define SGLRDCTLINT   0x00040000U

Definition at line 473 of file t4_regs.h.

#define SGLRDEEPROMINT   0x00004000U

Definition at line 477 of file t4_regs.h.

#define SGLRDFLASHINT   0x00000400U

Definition at line 481 of file t4_regs.h.

#define SGLRDPLINT   0x00400000U

Definition at line 469 of file t4_regs.h.

#define SGLWRBOOTINT   0x00000080U

Definition at line 484 of file t4_regs.h.

#define SGLWRCTLINT   0x00080000U

Definition at line 472 of file t4_regs.h.

#define SGLWREEPROMINT   0x00008000U

Definition at line 476 of file t4_regs.h.

#define SGLWRFLASHINT   0x00000800U

Definition at line 480 of file t4_regs.h.

#define SGLWRPLINT   0x00800000U

Definition at line 468 of file t4_regs.h.

#define SLVFIFOPARINT   0x00080000U

Definition at line 903 of file t4_regs.h.

#define SMB   0x00000100U

Definition at line 974 of file t4_regs.h.

#define SMB_INT_CAUSE   0x19090

Definition at line 900 of file t4_regs.h.

#define SOURCEPF (   x)    ((x) << SOURCEPF_SHIFT)

Definition at line 946 of file t4_regs.h.

#define SOURCEPF_GET (   x)    (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)

Definition at line 947 of file t4_regs.h.

#define SOURCEPF_MASK   0x00000700U

Definition at line 944 of file t4_regs.h.

#define SOURCEPF_SHIFT   8

Definition at line 945 of file t4_regs.h.

#define START_BIST   0x80000000U

Definition at line 365 of file t4_regs.h.

#define STATINT   0x00000020U

Definition at line 779 of file t4_regs.h.

#define SWINT   0x00000001U

Definition at line 941 of file t4_regs.h.

#define SYNSHIFTMAX (   x)    ((x) << SYNSHIFTMAX_SHIFT)

Definition at line 521 of file t4_regs.h.

#define SYNSHIFTMAX_GET (   x)
Value:
(((x) & SYNSHIFTMAX_MASK) >> \
SYNSHIFTMAX_SHIFT)

Definition at line 522 of file t4_regs.h.

#define SYNSHIFTMAX_MASK   0xff000000U

Definition at line 520 of file t4_regs.h.

#define SYNSHIFTMAX_SHIFT   24

Definition at line 519 of file t4_regs.h.

#define TARTAGPERR   0x00000200U

Definition at line 302 of file t4_regs.h.

#define TCAP   0x08000000U

Definition at line 338 of file t4_regs.h.

#define TCIP   0x04000000U

Definition at line 339 of file t4_regs.h.

#define TDCE   0x00020000U

Definition at line 346 of file t4_regs.h.

#define TDUE   0x00010000U

Definition at line 347 of file t4_regs.h.

#define TFCAPTUREMAX (   x)    ((x) << TFCAPTUREMAX_SHIFT)

Definition at line 873 of file t4_regs.h.

#define TFCAPTUREMAX_GET (   x)    (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)

Definition at line 874 of file t4_regs.h.

#define TFCAPTUREMAX_MASK   0x00003fffU

Definition at line 871 of file t4_regs.h.

#define TFCAPTUREMAX_SHIFT   0

Definition at line 872 of file t4_regs.h.

#define TFDROP   0x00020000U

Definition at line 855 of file t4_regs.h.

#define TFEN   0x00400000U

Definition at line 850 of file t4_regs.h.

#define TFINVERTMATCH   0x01000000U

Definition at line 848 of file t4_regs.h.

#define TFLENGTH (   x)    ((x) << TFLENGTH_SHIFT)

Definition at line 859 of file t4_regs.h.

#define TFLENGTH_GET (   x)    (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)

Definition at line 860 of file t4_regs.h.

#define TFLENGTH_MASK   0x00001f00U

Definition at line 857 of file t4_regs.h.

#define TFLENGTH_SHIFT   8

Definition at line 858 of file t4_regs.h.

#define TFMINPKTSIZE (   x)    ((x) << TFMINPKTSIZE_SHIFT)

Definition at line 869 of file t4_regs.h.

#define TFMINPKTSIZE_GET (   x)    (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)

Definition at line 870 of file t4_regs.h.

#define TFMINPKTSIZE_MASK   0x01ff0000U

Definition at line 867 of file t4_regs.h.

#define TFMINPKTSIZE_SHIFT   16

Definition at line 868 of file t4_regs.h.

#define TFOFFSET (   x)    ((x) << TFOFFSET_SHIFT)

Definition at line 863 of file t4_regs.h.

#define TFOFFSET_GET (   x)    (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)

Definition at line 864 of file t4_regs.h.

#define TFOFFSET_MASK   0x0000001fU

Definition at line 861 of file t4_regs.h.

#define TFOFFSET_SHIFT   0

Definition at line 862 of file t4_regs.h.

#define TFPKTTOOLARGE   0x00800000U

Definition at line 849 of file t4_regs.h.

#define TFPORT (   x)    ((x) << TFPORT_SHIFT)

Definition at line 853 of file t4_regs.h.

#define TFPORT_GET (   x)    (((x) & TFPORT_MASK) >> TFPORT_SHIFT)

Definition at line 854 of file t4_regs.h.

#define TFPORT_MASK   0x003c0000U

Definition at line 851 of file t4_regs.h.

#define TFPORT_SHIFT   18

Definition at line 852 of file t4_regs.h.

#define TFSOPEOPERR   0x00010000U

Definition at line 856 of file t4_regs.h.

#define TFTP   0x10000000U

Definition at line 337 of file t4_regs.h.

#define THRESHOLD_0 (   x)    ((x) << THRESHOLD_0_SHIFT)

Definition at line 199 of file t4_regs.h.

#define THRESHOLD_0_GET (   x)    (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)

Definition at line 200 of file t4_regs.h.

#define THRESHOLD_0_MASK   0x3f000000U

Definition at line 197 of file t4_regs.h.

#define THRESHOLD_0_SHIFT   24

Definition at line 198 of file t4_regs.h.

#define THRESHOLD_1 (   x)    ((x) << THRESHOLD_1_SHIFT)

Definition at line 203 of file t4_regs.h.

#define THRESHOLD_1_GET (   x)    (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)

Definition at line 204 of file t4_regs.h.

#define THRESHOLD_1_MASK   0x003f0000U

Definition at line 201 of file t4_regs.h.

#define THRESHOLD_1_SHIFT   16

Definition at line 202 of file t4_regs.h.

#define THRESHOLD_2 (   x)    ((x) << THRESHOLD_2_SHIFT)

Definition at line 207 of file t4_regs.h.

#define THRESHOLD_2_GET (   x)    (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)

Definition at line 208 of file t4_regs.h.

#define THRESHOLD_2_MASK   0x00003f00U

Definition at line 205 of file t4_regs.h.

#define THRESHOLD_2_SHIFT   8

Definition at line 206 of file t4_regs.h.

#define THRESHOLD_3 (   x)    ((x) << THRESHOLD_3_SHIFT)

Definition at line 211 of file t4_regs.h.

#define THRESHOLD_3_GET (   x)    (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)

Definition at line 212 of file t4_regs.h.

#define THRESHOLD_3_MASK   0x0000003fU

Definition at line 209 of file t4_regs.h.

#define THRESHOLD_3_SHIFT   0

Definition at line 210 of file t4_regs.h.

#define TIEQINPARERRINT   0x00080000U

Definition at line 440 of file t4_regs.h.

#define TIEQOUTPARERRINT   0x00100000U

Definition at line 439 of file t4_regs.h.

#define TIMEOUTINT   0x10000000U

Definition at line 463 of file t4_regs.h.

#define TIMEOUTMAINT   0x20000000U

Definition at line 462 of file t4_regs.h.

#define TIMERREG (   x)    ((x) << TIMERREG_SHIFT)

Definition at line 81 of file t4_regs.h.

#define TIMERREG_MASK   0x0000e000U

Definition at line 79 of file t4_regs.h.

#define TIMERREG_SHIFT   13

Definition at line 80 of file t4_regs.h.

#define TIMERRESOLUTION_GET (   x)    (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)

Definition at line 512 of file t4_regs.h.

#define TIMERRESOLUTION_MASK   0x00ff0000U

Definition at line 510 of file t4_regs.h.

#define TIMERRESOLUTION_SHIFT   16

Definition at line 511 of file t4_regs.h.

#define TIMERVALUE0 (   x)    ((x) << TIMERVALUE0_SHIFT)

Definition at line 223 of file t4_regs.h.

#define TIMERVALUE0_GET (   x)    (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)

Definition at line 224 of file t4_regs.h.

#define TIMERVALUE0_MASK   0xffff0000U

Definition at line 221 of file t4_regs.h.

#define TIMERVALUE0_SHIFT   16

Definition at line 222 of file t4_regs.h.

#define TIMERVALUE1 (   x)    ((x) << TIMERVALUE1_SHIFT)

Definition at line 227 of file t4_regs.h.

#define TIMERVALUE1_GET (   x)    (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)

Definition at line 228 of file t4_regs.h.

#define TIMERVALUE1_MASK   0x0000ffffU

Definition at line 225 of file t4_regs.h.

#define TIMERVALUE1_SHIFT   0

Definition at line 226 of file t4_regs.h.

#define TIMERVALUE2 (   x)    ((x) << TIMERVALUE2_SHIFT)

Definition at line 233 of file t4_regs.h.

#define TIMERVALUE2_GET (   x)    (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)

Definition at line 234 of file t4_regs.h.

#define TIMERVALUE2_MASK   0xffff0000U

Definition at line 231 of file t4_regs.h.

#define TIMERVALUE2_SHIFT   16

Definition at line 232 of file t4_regs.h.

#define TIMERVALUE3 (   x)    ((x) << TIMERVALUE3_SHIFT)

Definition at line 237 of file t4_regs.h.

#define TIMERVALUE3_GET (   x)    (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)

Definition at line 238 of file t4_regs.h.

#define TIMERVALUE3_MASK   0x0000ffffU

Definition at line 235 of file t4_regs.h.

#define TIMERVALUE3_SHIFT   0

Definition at line 236 of file t4_regs.h.

#define TIMERVALUE4 (   x)    ((x) << TIMERVALUE4_SHIFT)

Definition at line 243 of file t4_regs.h.

#define TIMERVALUE4_GET (   x)    (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)

Definition at line 244 of file t4_regs.h.

#define TIMERVALUE4_MASK   0xffff0000U

Definition at line 241 of file t4_regs.h.

#define TIMERVALUE4_SHIFT   16

Definition at line 242 of file t4_regs.h.

#define TIMERVALUE5 (   x)    ((x) << TIMERVALUE5_SHIFT)

Definition at line 247 of file t4_regs.h.

#define TIMERVALUE5_GET (   x)    (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)

Definition at line 248 of file t4_regs.h.

#define TIMERVALUE5_MASK   0x0000ffffU

Definition at line 245 of file t4_regs.h.

#define TIMERVALUE5_SHIFT   0

Definition at line 246 of file t4_regs.h.

#define TNPP   0x20000000U

Definition at line 336 of file t4_regs.h.

#define TOS_MASK   0x00000010U

Definition at line 594 of file t4_regs.h.

#define TP   0x00080000U

Definition at line 963 of file t4_regs.h.

#define TP_CCTRL_TABLE   0x7ddc

Definition at line 555 of file t4_regs.h.

#define TP_FRAMING_ERROR   0x00000008U

Definition at line 895 of file t4_regs.h.

#define TP_GLOBAL_CONFIG   0x7d08

Definition at line 497 of file t4_regs.h.

#define TP_INGRESS_CONFIG   0x141

Definition at line 601 of file t4_regs.h.

#define TP_INT_CAUSE   0x7e74

Definition at line 584 of file t4_regs.h.

#define TP_MIB_DATA   0x7e54

Definition at line 583 of file t4_regs.h.

#define TP_MIB_INDEX   0x7e50

Definition at line 582 of file t4_regs.h.

#define TP_MIB_MAC_IN_ERR_0   0x0

Definition at line 607 of file t4_regs.h.

#define TP_MIB_OFD_ARP_DROP   0x36

Definition at line 618 of file t4_regs.h.

#define TP_MIB_OFD_VLN_DROP_0   0x58

Definition at line 620 of file t4_regs.h.

#define TP_MIB_TCP_IN_SEG_HI   0x10

Definition at line 609 of file t4_regs.h.

#define TP_MIB_TCP_IN_SEG_LO   0x11

Definition at line 610 of file t4_regs.h.

#define TP_MIB_TCP_OUT_RST   0xc

Definition at line 608 of file t4_regs.h.

#define TP_MIB_TCP_OUT_SEG_HI   0x12

Definition at line 611 of file t4_regs.h.

#define TP_MIB_TCP_OUT_SEG_LO   0x13

Definition at line 612 of file t4_regs.h.

#define TP_MIB_TCP_RXT_SEG_HI   0x14

Definition at line 613 of file t4_regs.h.

#define TP_MIB_TCP_RXT_SEG_LO   0x15

Definition at line 614 of file t4_regs.h.

#define TP_MIB_TCP_V6IN_ERR_0   0x28

Definition at line 616 of file t4_regs.h.

#define TP_MIB_TCP_V6OUT_RST   0x2c

Definition at line 617 of file t4_regs.h.

#define TP_MIB_TNL_CNG_DROP_0   0x18

Definition at line 615 of file t4_regs.h.

#define TP_MIB_TNL_DROP_0   0x44

Definition at line 619 of file t4_regs.h.

#define TP_MTU_TABLE   0x7de4

Definition at line 556 of file t4_regs.h.

#define TP_OUT_CONFIG   0x7d04

Definition at line 493 of file t4_regs.h.

#define TP_PARA_REG2   0x7d68

Definition at line 504 of file t4_regs.h.

#define TP_PIO_ADDR   0x7e40

Definition at line 580 of file t4_regs.h.

#define TP_PIO_DATA   0x7e44

Definition at line 581 of file t4_regs.h.

#define TP_RSS_LKP_TABLE   0x7dec

Definition at line 569 of file t4_regs.h.

#define TP_SHIFT_CNT   0x7dc0

Definition at line 518 of file t4_regs.h.

#define TP_TIMER_RESOLUTION   0x7d90

Definition at line 509 of file t4_regs.h.

#define TP_VLAN_PRI_MAP   0x140

Definition at line 587 of file t4_regs.h.

#define TPCP   0x40000000U

Definition at line 335 of file t4_regs.h.

#define TPFIFO   0x0000000fU

Definition at line 794 of file t4_regs.h.

#define TRCEN   0x00000002U

Definition at line 836 of file t4_regs.h.

#define TRCFIFOEMPTY   0x00000010U

Definition at line 833 of file t4_regs.h.

#define TRCIGNOREDROPINPUT   0x00000008U

Definition at line 834 of file t4_regs.h.

#define TRCINT   0x00000004U

Definition at line 782 of file t4_regs.h.

#define TRCKEEPDUPLICATES   0x00000004U

Definition at line 835 of file t4_regs.h.

#define TRCMULTIFILTER   0x00000001U

Definition at line 837 of file t4_regs.h.

#define TXDATAFIFO   0x000001e0U

Definition at line 792 of file t4_regs.h.

#define TXDESCFIFO   0x00001e00U

Definition at line 791 of file t4_regs.h.

#define TXFIFO_PRTY_ERR   0x00000002U

Definition at line 1014 of file t4_regs.h.

#define TXINT   0x00000010U

Definition at line 780 of file t4_regs.h.

#define ULP_RX   0x00800000U

Definition at line 959 of file t4_regs.h.

#define ULP_RX_INT_CAUSE   0x19158

Definition at line 905 of file t4_regs.h.

#define ULP_RX_ISCSI_PSZ   0x19168

Definition at line 907 of file t4_regs.h.

#define ULP_RX_ISCSI_TAGMASK   0x19164

Definition at line 906 of file t4_regs.h.

#define ULP_RX_TDDP_PSZ   0x19178

Definition at line 921 of file t4_regs.h.

#define ULP_TX   0x08000000U

Definition at line 955 of file t4_regs.h.

#define ULP_TX_INT_CAUSE   0x8dcc

Definition at line 622 of file t4_regs.h.

#define UNKNOWNCMD   0x00008000U

Definition at line 1004 of file t4_regs.h.

#define UNXSPLCPLERR   0x20000000U

Definition at line 282 of file t4_regs.h.

#define UPACCNONZERO   0x00000001U

Definition at line 458 of file t4_regs.h.

#define UPCRST   0x1U

Definition at line 424 of file t4_regs.h.

#define V_DROPPED_DB (   x)    ((x) << S_DROPPED_DB)

Definition at line 273 of file t4_regs.h.

#define V_ENABLE_DROP (   x)    ((x) << S_ENABLE_DROP)

Definition at line 270 of file t4_regs.h.

#define V_HP_INT_THRESH (   x)    ((x) << S_HP_INT_THRESH)

Definition at line 257 of file t4_regs.h.

#define V_LP_INT_THRESH (   x)    ((x) << S_LP_INT_THRESH)

Definition at line 263 of file t4_regs.h.

#define VFID (   x)    ((x) << VFID_SHIFT)

Definition at line 951 of file t4_regs.h.

#define VFID_GET (   x)    (((x) & VFID_MASK) >> VFID_SHIFT)

Definition at line 952 of file t4_regs.h.

#define VFID_MASK   0x0000007fU

Definition at line 949 of file t4_regs.h.

#define VFID_SHIFT   0

Definition at line 950 of file t4_regs.h.

#define VLAN_MASK   0x00000008U

Definition at line 595 of file t4_regs.h.

#define VLANEXTENABLE_MASK   0x0000f000U

Definition at line 494 of file t4_regs.h.

#define VLANEXTENABLE_SHIFT   12

Definition at line 495 of file t4_regs.h.

#define VNIC   0x00000800U

Definition at line 602 of file t4_regs.h.

#define VNIC_ID_MASK   0x00000004U

Definition at line 596 of file t4_regs.h.

#define WINDOW (   x)    ((x) << WINDOW_SHIFT)

Definition at line 321 of file t4_regs.h.

#define WINDOW_MASK   0x000000ffU

Definition at line 319 of file t4_regs.h.

#define WINDOW_SHIFT   0

Definition at line 320 of file t4_regs.h.

#define X_INGPADBOUNDARY_SHIFT   5

Definition at line 90 of file t4_regs.h.

#define X_RXPKTCPLMODE_SPLIT   1

Definition at line 89 of file t4_regs.h.

#define XGMAC0   0x00000200U

Definition at line 973 of file t4_regs.h.

#define XGMAC1   0x00000400U

Definition at line 972 of file t4_regs.h.

#define XGMAC_KR0   0x00000800U

Definition at line 971 of file t4_regs.h.

#define XGMAC_KR1   0x00001000U

Definition at line 970 of file t4_regs.h.

#define XGMAC_PORT_CFG2   0x1018

Definition at line 1017 of file t4_regs.h.

#define XGMAC_PORT_EPIO_DATA0   0x10c0

Definition at line 1024 of file t4_regs.h.

#define XGMAC_PORT_EPIO_DATA1   0x10c4

Definition at line 1025 of file t4_regs.h.

#define XGMAC_PORT_EPIO_DATA2   0x10c8

Definition at line 1026 of file t4_regs.h.

#define XGMAC_PORT_EPIO_DATA3   0x10cc

Definition at line 1027 of file t4_regs.h.

#define XGMAC_PORT_EPIO_OP   0x10d0

Definition at line 1028 of file t4_regs.h.

#define XGMAC_PORT_INT_CAUSE   0x10dc

Definition at line 1034 of file t4_regs.h.

#define XGMAC_PORT_MAGIC_MACID_HI   0x1028

Definition at line 1022 of file t4_regs.h.

#define XGMAC_PORT_MAGIC_MACID_LO   0x1024

Definition at line 1021 of file t4_regs.h.

#define ZERO_C_CMD_ERROR   0x10000000U

Definition at line 640 of file t4_regs.h.

#define ZERO_E_CMD_ERROR   0x00400000U

Definition at line 629 of file t4_regs.h.

#define ZERO_SWITCH_ERROR   0x00000001U

Definition at line 898 of file t4_regs.h.

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