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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/kernel.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/fb.h>#include <linux/interrupt.h>#include <linux/delay.h>#include <linux/console.h>#include <linux/mfd/core.h>#include <linux/mfd/tmio.h>#include <linux/uaccess.h>Go to the source code of this file.
Data Structures | |
| struct | tmiofb_par |
Macros | |
| #define | TMIOFB_ACC_CSADR(x) (0x00000000 | ((x) & 0x001ffffe)) |
| #define | TMIOFB_ACC_CHPIX(x) (0x01000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_CVPIX(x) (0x02000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_PSADR(x) (0x03000000 | ((x) & 0x00fffffe)) |
| #define | TMIOFB_ACC_PHPIX(x) (0x04000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_PVPIX(x) (0x05000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_PHOFS(x) (0x06000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_PVOFS(x) (0x07000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_POADR(x) (0x08000000 | ((x) & 0x00fffffe)) |
| #define | TMIOFB_ACC_RSTR(x) (0x09000000 | ((x) & 0x000000ff)) |
| #define | TMIOFB_ACC_TCLOR(x) (0x0A000000 | ((x) & 0x0000ffff)) |
| #define | TMIOFB_ACC_FILL(x) (0x0B000000 | ((x) & 0x0000ffff)) |
| #define | TMIOFB_ACC_DSADR(x) (0x0C000000 | ((x) & 0x00fffffe)) |
| #define | TMIOFB_ACC_SSADR(x) (0x0D000000 | ((x) & 0x00fffffe)) |
| #define | TMIOFB_ACC_DHPIX(x) (0x0E000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_DVPIX(x) (0x0F000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_SHPIX(x) (0x10000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_SVPIX(x) (0x11000000 | ((x) & 0x000003ff)) |
| #define | TMIOFB_ACC_LBINI(x) (0x12000000 | ((x) & 0x0000ffff)) |
| #define | TMIOFB_ACC_LBK2(x) (0x13000000 | ((x) & 0x0000ffff)) |
| #define | TMIOFB_ACC_SHBINI(x) (0x14000000 | ((x) & 0x0000ffff)) |
| #define | TMIOFB_ACC_SHBK2(x) (0x15000000 | ((x) & 0x0000ffff)) |
| #define | TMIOFB_ACC_SVBINI(x) (0x16000000 | ((x) & 0x0000ffff)) |
| #define | TMIOFB_ACC_SVBK2(x) (0x17000000 | ((x) & 0x0000ffff)) |
| #define | TMIOFB_ACC_CMGO 0x20000000 |
| #define | TMIOFB_ACC_CMGO_CEND 0x00000001 |
| #define | TMIOFB_ACC_CMGO_INT 0x00000002 |
| #define | TMIOFB_ACC_CMGO_CMOD 0x00000010 |
| #define | TMIOFB_ACC_CMGO_CDVRV 0x00000020 |
| #define | TMIOFB_ACC_CMGO_CDHRV 0x00000040 |
| #define | TMIOFB_ACC_CMGO_RUND 0x00008000 |
| #define | TMIOFB_ACC_SCGO 0x21000000 |
| #define | TMIOFB_ACC_SCGO_CEND 0x00000001 |
| #define | TMIOFB_ACC_SCGO_INT 0x00000002 |
| #define | TMIOFB_ACC_SCGO_ROP3 0x00000004 |
| #define | TMIOFB_ACC_SCGO_TRNS 0x00000008 |
| #define | TMIOFB_ACC_SCGO_DVRV 0x00000010 |
| #define | TMIOFB_ACC_SCGO_DHRV 0x00000020 |
| #define | TMIOFB_ACC_SCGO_SVRV 0x00000040 |
| #define | TMIOFB_ACC_SCGO_SHRV 0x00000080 |
| #define | TMIOFB_ACC_SCGO_DSTXY 0x00008000 |
| #define | TMIOFB_ACC_SBGO 0x22000000 |
| #define | TMIOFB_ACC_SBGO_CEND 0x00000001 |
| #define | TMIOFB_ACC_SBGO_INT 0x00000002 |
| #define | TMIOFB_ACC_SBGO_DVRV 0x00000010 |
| #define | TMIOFB_ACC_SBGO_DHRV 0x00000020 |
| #define | TMIOFB_ACC_SBGO_SVRV 0x00000040 |
| #define | TMIOFB_ACC_SBGO_SHRV 0x00000080 |
| #define | TMIOFB_ACC_SBGO_SBMD 0x00000100 |
| #define | TMIOFB_ACC_FLGO 0x23000000 |
| #define | TMIOFB_ACC_FLGO_CEND 0x00000001 |
| #define | TMIOFB_ACC_FLGO_INT 0x00000002 |
| #define | TMIOFB_ACC_FLGO_ROP3 0x00000004 |
| #define | TMIOFB_ACC_LDGO 0x24000000 |
| #define | TMIOFB_ACC_LDGO_CEND 0x00000001 |
| #define | TMIOFB_ACC_LDGO_INT 0x00000002 |
| #define | TMIOFB_ACC_LDGO_ROP3 0x00000004 |
| #define | TMIOFB_ACC_LDGO_ENDPX 0x00000008 |
| #define | TMIOFB_ACC_LDGO_LVRV 0x00000010 |
| #define | TMIOFB_ACC_LDGO_LHRV 0x00000020 |
| #define | TMIOFB_ACC_LDGO_LDMOD 0x00000040 |
| #define | TMIOFB_FIFO_SIZE 512 |
| #define | CCR_CMD 0x04 /* Command */ |
| #define | CCR_REVID 0x08 /* Revision ID */ |
| #define | CCR_BASEL 0x10 /* LCD Control Reg Base Addr Low */ |
| #define | CCR_BASEH 0x12 /* LCD Control Reg Base Addr High */ |
| #define | CCR_UGCC 0x40 /* Unified Gated Clock Control */ |
| #define | CCR_GCC 0x42 /* Gated Clock Control */ |
| #define | CCR_USC 0x50 /* Unified Software Clear */ |
| #define | CCR_VRAMRTC 0x60 /* VRAM Timing Control */ |
| #define | CCR_VRAMSAC 0x62 /* VRAM Access Control */ |
| #define | CCR_VRAMBC 0x64 /* VRAM Block Control */ |
| #define | LCR_UIS 0x000 /* Unified Interrupt Status */ |
| #define | LCR_VHPN 0x008 /* VRAM Horizontal Pixel Number */ |
| #define | LCR_CFSAL 0x00a /* Command FIFO Start Address Low */ |
| #define | LCR_CFSAH 0x00c /* Command FIFO Start Address High */ |
| #define | LCR_CFS 0x00e /* Command FIFO Size */ |
| #define | LCR_CFWS 0x010 /* Command FIFO Writeable Size */ |
| #define | LCR_BBIE 0x012 /* BitBLT Interrupt Enable */ |
| #define | LCR_BBISC 0x014 /* BitBLT Interrupt Status and Clear */ |
| #define | LCR_CCS 0x016 /* Command Count Status */ |
| #define | LCR_BBES 0x018 /* BitBLT Execution Status */ |
| #define | LCR_CMDL 0x01c /* Command Low */ |
| #define | LCR_CMDH 0x01e /* Command High */ |
| #define | LCR_CFC 0x022 /* Command FIFO Clear */ |
| #define | LCR_CCIFC 0x024 /* CMOS Camera IF Control */ |
| #define | LCR_HWT 0x026 /* Hardware Test */ |
| #define | LCR_LCDCCRC 0x100 /* LCDC Clock and Reset Control */ |
| #define | LCR_LCDCC 0x102 /* LCDC Control */ |
| #define | LCR_LCDCOPC 0x104 /* LCDC Output Pin Control */ |
| #define | LCR_LCDIS 0x108 /* LCD Interrupt Status */ |
| #define | LCR_LCDIM 0x10a /* LCD Interrupt Mask */ |
| #define | LCR_LCDIE 0x10c /* LCD Interrupt Enable */ |
| #define | LCR_GDSAL 0x122 /* Graphics Display Start Address Low */ |
| #define | LCR_GDSAH 0x124 /* Graphics Display Start Address High */ |
| #define | LCR_VHPCL 0x12a /* VRAM Horizontal Pixel Count Low */ |
| #define | LCR_VHPCH 0x12c /* VRAM Horizontal Pixel Count High */ |
| #define | LCR_GM 0x12e /* Graphic Mode(VRAM access enable) */ |
| #define | LCR_HT 0x140 /* Horizontal Total */ |
| #define | LCR_HDS 0x142 /* Horizontal Display Start */ |
| #define | LCR_HSS 0x144 /* H-Sync Start */ |
| #define | LCR_HSE 0x146 /* H-Sync End */ |
| #define | LCR_HNP 0x14c /* Horizontal Number of Pixels */ |
| #define | LCR_VT 0x150 /* Vertical Total */ |
| #define | LCR_VDS 0x152 /* Vertical Display Start */ |
| #define | LCR_VSS 0x154 /* V-Sync Start */ |
| #define | LCR_VSE 0x156 /* V-Sync End */ |
| #define | LCR_CDLN 0x160 /* Current Display Line Number */ |
| #define | LCR_ILN 0x162 /* Interrupt Line Number */ |
| #define | LCR_SP 0x164 /* Sync Polarity */ |
| #define | LCR_MISC 0x166 /* MISC(RGB565 mode) */ |
| #define | LCR_VIHSS 0x16a /* Video Interface H-Sync Start */ |
| #define | LCR_VIVS 0x16c /* Video Interface Vertical Start */ |
| #define | LCR_VIVE 0x16e /* Video Interface Vertical End */ |
| #define | LCR_VIVSS 0x170 /* Video Interface V-Sync Start */ |
| #define | LCR_VCCIS 0x17e /* Video / CMOS Camera Interface Select */ |
| #define | LCR_VIDWSAL 0x180 /* VI Data Write Start Address Low */ |
| #define | LCR_VIDWSAH 0x182 /* VI Data Write Start Address High */ |
| #define | LCR_VIDRSAL 0x184 /* VI Data Read Start Address Low */ |
| #define | LCR_VIDRSAH 0x186 /* VI Data Read Start Address High */ |
| #define | LCR_VIPDDST 0x188 /* VI Picture Data Display Start Timing */ |
| #define | LCR_VIPDDET 0x186 /* VI Picture Data Display End Timing */ |
| #define | LCR_VIE 0x18c /* Video Interface Enable */ |
| #define | LCR_VCS 0x18e /* Video/Camera Select */ |
| #define | LCR_VPHWC 0x194 /* Video Picture Horizontal Wait Count */ |
| #define | LCR_VPHS 0x196 /* Video Picture Horizontal Size */ |
| #define | LCR_VPVWC 0x198 /* Video Picture Vertical Wait Count */ |
| #define | LCR_VPVS 0x19a /* Video Picture Vertical Size */ |
| #define | LCR_PLHPIX 0x1a0 /* PLHPIX */ |
| #define | LCR_XS 0x1a2 /* XStart */ |
| #define | LCR_XCKHW 0x1a4 /* XCK High Width */ |
| #define | LCR_STHS 0x1a8 /* STH Start */ |
| #define | LCR_VT2 0x1aa /* Vertical Total */ |
| #define | LCR_YCKSW 0x1ac /* YCK Start Wait */ |
| #define | LCR_YSTS 0x1ae /* YST Start */ |
| #define | LCR_PPOLS 0x1b0 /* #PPOL Start */ |
| #define | LCR_PRECW 0x1b2 /* PREC Width */ |
| #define | LCR_VCLKHW 0x1b4 /* VCLK High Width */ |
| #define | LCR_OC 0x1b6 /* Output Control */ |
| #define | tmiofb_suspend NULL |
| #define | tmiofb_resume NULL |
Functions | |
| module_init (tmiofb_init) | |
| module_exit (tmiofb_cleanup) | |
| MODULE_DESCRIPTION ("TMIO framebuffer driver") | |
| MODULE_AUTHOR ("Chris Humbert, Dirk Opfer, Dmitry Baryshkov") | |
| MODULE_LICENSE ("GPL") | |
| #define CCR_BASEH 0x12 /* LCD Control Reg Base Addr High */ |
| #define LCR_BBISC 0x014 /* BitBLT Interrupt Status and Clear */ |
| #define LCR_CFSAH 0x00c /* Command FIFO Start Address High */ |
| #define LCR_CFSAL 0x00a /* Command FIFO Start Address Low */ |
| #define LCR_GDSAH 0x124 /* Graphics Display Start Address High */ |
| #define LCR_GDSAL 0x122 /* Graphics Display Start Address Low */ |
| #define LCR_GM 0x12e /* Graphic Mode(VRAM access enable) */ |
| #define LCR_LCDCCRC 0x100 /* LCDC Clock and Reset Control */ |
| #define LCR_VCCIS 0x17e /* Video / CMOS Camera Interface Select */ |
| #define LCR_VHPCH 0x12c /* VRAM Horizontal Pixel Count High */ |
| #define LCR_VHPCL 0x12a /* VRAM Horizontal Pixel Count Low */ |
| #define LCR_VIDRSAH 0x186 /* VI Data Read Start Address High */ |
| #define LCR_VIDRSAL 0x184 /* VI Data Read Start Address Low */ |
| #define LCR_VIDWSAH 0x182 /* VI Data Write Start Address High */ |
| #define LCR_VIDWSAL 0x180 /* VI Data Write Start Address Low */ |
| #define LCR_VIPDDET 0x186 /* VI Picture Data Display End Timing */ |
| #define LCR_VIPDDST 0x188 /* VI Picture Data Display Start Timing */ |
| #define LCR_VIVS 0x16c /* Video Interface Vertical Start */ |
| #define LCR_VPHWC 0x194 /* Video Picture Horizontal Wait Count */ |
| #define LCR_VPVWC 0x198 /* Video Picture Vertical Wait Count */ |
| #define TMIOFB_ACC_CHPIX | ( | x | ) | (0x01000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_CSADR | ( | x | ) | (0x00000000 | ((x) & 0x001ffffe)) |
| #define TMIOFB_ACC_CVPIX | ( | x | ) | (0x02000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_DHPIX | ( | x | ) | (0x0E000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_DSADR | ( | x | ) | (0x0C000000 | ((x) & 0x00fffffe)) |
| #define TMIOFB_ACC_DVPIX | ( | x | ) | (0x0F000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_FILL | ( | x | ) | (0x0B000000 | ((x) & 0x0000ffff)) |
| #define TMIOFB_ACC_LBINI | ( | x | ) | (0x12000000 | ((x) & 0x0000ffff)) |
| #define TMIOFB_ACC_LBK2 | ( | x | ) | (0x13000000 | ((x) & 0x0000ffff)) |
| #define TMIOFB_ACC_PHOFS | ( | x | ) | (0x06000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_PHPIX | ( | x | ) | (0x04000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_POADR | ( | x | ) | (0x08000000 | ((x) & 0x00fffffe)) |
| #define TMIOFB_ACC_PSADR | ( | x | ) | (0x03000000 | ((x) & 0x00fffffe)) |
| #define TMIOFB_ACC_PVOFS | ( | x | ) | (0x07000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_PVPIX | ( | x | ) | (0x05000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_RSTR | ( | x | ) | (0x09000000 | ((x) & 0x000000ff)) |
| #define TMIOFB_ACC_SHBINI | ( | x | ) | (0x14000000 | ((x) & 0x0000ffff)) |
| #define TMIOFB_ACC_SHBK2 | ( | x | ) | (0x15000000 | ((x) & 0x0000ffff)) |
| #define TMIOFB_ACC_SHPIX | ( | x | ) | (0x10000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_SSADR | ( | x | ) | (0x0D000000 | ((x) & 0x00fffffe)) |
| #define TMIOFB_ACC_SVBINI | ( | x | ) | (0x16000000 | ((x) & 0x0000ffff)) |
| #define TMIOFB_ACC_SVBK2 | ( | x | ) | (0x17000000 | ((x) & 0x0000ffff)) |
| #define TMIOFB_ACC_SVPIX | ( | x | ) | (0x11000000 | ((x) & 0x000003ff)) |
| #define TMIOFB_ACC_TCLOR | ( | x | ) | (0x0A000000 | ((x) & 0x0000ffff)) |
| MODULE_AUTHOR | ( | "Chris | Humbert, |
| Dirk | Opfer, | ||
| Dmitry Baryshkov" | |||
| ) |
| MODULE_DESCRIPTION | ( | "TMIO framebuffer driver" | ) |
| module_exit | ( | tmiofb_cleanup | ) |
| module_init | ( | tmiofb_init | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
1.8.2