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| #define TOPIC97_AUDIO_VIDEO_SWITCH 0x003c /* 8 bit */ |
| #define TOPIC97_AVS_AUDIO_CONTROL 0x02 |
| #define TOPIC97_AVS_VIDEO_CONTROL 0x01 |
| #define TOPIC97_ICR_INTA 0x10 |
| #define TOPIC97_ICR_INTB 0x20 |
| #define TOPIC97_ICR_IRQNP 0x02 |
| #define TOPIC97_ICR_IRQSEL 0x01 |
| #define TOPIC97_ICR_STSIRQNP 0x04 |
| #define TOPIC97_INT_CONTROL 0x00a1 /* 8 bit */ |
| #define TOPIC97_MISC1 0x00ad /* 8bit */ |
| #define TOPIC97_MISC1_CLOCKRUN_ENABLE 0x80 |
| #define TOPIC97_MISC1_CLOCKRUN_MODE 0x40 |
| #define TOPIC97_MISC1_DETECT_REQ_ENA 0x10 |
| #define TOPIC97_MISC1_R2_LOW_ENABLE 0x10 |
| #define TOPIC97_MISC1_SCK_CLEAR_DIS 0x04 |
| #define TOPIC97_MISC2 0x00ae /* 8 bit */ |
| #define TOPIC97_MISC2_SPWR_ENABLE 0x04 |
| #define TOPIC97_MISC2_SPWRCLK_MASK 0x70 |
| #define TOPIC97_MISC2_SPWRMOD 0x08 |
| #define TOPIC97_MISC2_ZV_ENABLE 0x01 |
| #define TOPIC97_MISC2_ZV_MODE 0x02 |
| #define TOPIC97_RCR_CAUDIO_OFF 0x00000002 |
| #define TOPIC97_RCR_CB_DEV_MASK 0x0000f800 |
| #define TOPIC97_RCR_CB_DEV_SHIFT 11 |
| #define TOPIC97_RCR_CLKRUN_ENA 0x20000000 |
| #define TOPIC97_RCR_IOPLUP 0x08000000 |
| #define TOPIC97_RCR_RI_DISABLE 0x00000004 |
| #define TOPIC97_RCR_TESTMODE 0x10000000 |
| #define TOPIC97_ZOOM_VIDEO_CONTROL 0x009c /* 8 bit */ |
| #define TOPIC97_ZV_CONTROL_ENABLE 0x01 |
| #define TOPIC_CARD_CONTROL 0x00a1 /* 8 bit */ |
| #define TOPIC_CARD_DETECT 0x00a3 /* 8 bit */ |
| #define TOPIC_CCR_CCLK 0x04 |
| #define TOPIC_CCR_CLOCK 0x0c |
| #define TOPIC_CCR_INTA 0x10 |
| #define TOPIC_CCR_INTB 0x20 |
| #define TOPIC_CCR_PCICLK 0x0c |
| #define TOPIC_CCR_PCICLK_2 0x08 |
| #define TOPIC_CDR_MODE_PC32 0x80 |
| #define TOPIC_CDR_SW_DETECT 0x01 |
| #define TOPIC_CDR_VS1 0x04 |
| #define TOPIC_CDR_VS2 0x02 |
| #define TOPIC_EXCA_IF_CONTROL 0x3e /* 8 bit */ |
| #define TOPIC_EXCA_IFC_33V_ENA 0x01 |
| #define TOPIC_RCR_BUFOFF_PWROFF 0x02000000 |
| #define TOPIC_RCR_BUFOFF_SIGOFF 0x01000000 |
| #define TOPIC_RCR_CAUDIO_INVERT 0x00000001 |
| #define TOPIC_RCR_REMOVE_RESET 0x40000000 |
| #define TOPIC_RCR_RESUME_RESET 0x80000000 |
| #define TOPIC_REGISTER_CONTROL 0x00a4 /* 32 bit */ |
| #define TOPIC_SCR_IRQSEL 0x00000001 |
| #define TOPIC_SLOT_CONTROL 0x00a0 /* 8 bit */ |
| #define TOPIC_SLOT_ID_LOCK 0x20 |
| #define TOPIC_SLOT_ID_WP 0x10 |
| #define TOPIC_SLOT_OFS_MASK 0x03 |
| #define TOPIC_SLOT_PORT_MASK 0x0c |
| #define TOPIC_SLOT_PORT_SHIFT 2 |
| #define TOPIC_SLOT_SLOTEN 0x40 |
| #define TOPIC_SLOT_SLOTON 0x80 |
| #define TOPIC_SOCKET_CONTROL 0x0090 /* 32 bit */ |
1.8.2