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arch
tile
include
arch
trio_pcie_intfc.h
Go to the documentation of this file.
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/*
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* Copyright 2012 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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/* Machine-generated file; do not edit. */
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#ifndef __ARCH_TRIO_PCIE_INTFC_H__
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#define __ARCH_TRIO_PCIE_INTFC_H__
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#include <
arch/abi.h
>
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#include <
arch/trio_pcie_intfc_def.h
>
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#ifndef __ASSEMBLER__
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/*
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* Port Configuration.
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* Configuration of the PCIe Port
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*/
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__extension__
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typedef
union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/* Provides the state of the strapping pins for this port. */
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uint_reg_t
strap_state : 3;
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/* Reserved. */
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uint_reg_t
__reserved_0 : 1;
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/*
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* When 1, the device type will be overridden using OVD_DEV_TYPE_VAL.
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* When 0, the device type is determined based on the STRAP_STATE.
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*/
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uint_reg_t
ovd_dev_type : 1;
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/* Provides the device type when OVD_DEV_TYPE is 1. */
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uint_reg_t
ovd_dev_type_val : 4;
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/* Determines how link is trained. */
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uint_reg_t
train_mode : 2;
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/* Reserved. */
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uint_reg_t
__reserved_1
: 1;
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/*
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* For PCIe, used to flip physical RX lanes that were not properly wired.
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* This is not the same as lane reversal which is handled automatically
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* during link training. When 0, RX Lane0 must be wired to the link
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* partner (either to its Lane0 or it's LaneN). When RX_LANE_FLIP is 1,
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* the highest numbered lane for this port becomes Lane0 and Lane0 does
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* NOT have to be wired to the link partner.
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*/
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uint_reg_t
rx_lane_flip : 1;
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/*
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* For PCIe, used to flip physical TX lanes that were not properly wired.
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* This is not the same as lane reversal which is handled automatically
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* during link training. When 0, TX Lane0 must be wired to the link
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* partner (either to its Lane0 or it's LaneN). When TX_LANE_FLIP is 1,
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* the highest numbered lane for this port becomes Lane0 and Lane0 does
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* NOT have to be wired to the link partner.
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*/
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uint_reg_t
tx_lane_flip : 1;
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/*
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* For StreamIO port, configures the width of the port when TRAIN_MODE is
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* not STRAP.
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*/
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uint_reg_t
stream_width : 2;
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/*
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* For StreamIO port, configures the rate of the port when TRAIN_MODE is
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* not STRAP.
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*/
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uint_reg_t
stream_rate : 2;
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/* Reserved. */
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uint_reg_t
__reserved_2
: 46;
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#else
/* __BIG_ENDIAN__ */
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uint_reg_t
__reserved_2
: 46;
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uint_reg_t
stream_rate : 2;
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uint_reg_t
stream_width : 2;
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uint_reg_t
tx_lane_flip : 1;
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uint_reg_t
rx_lane_flip : 1;
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uint_reg_t
__reserved_1
: 1;
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uint_reg_t
train_mode : 2;
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uint_reg_t
ovd_dev_type_val : 4;
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uint_reg_t
ovd_dev_type : 1;
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uint_reg_t
__reserved_0 : 1;
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uint_reg_t
strap_state : 3;
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#endif
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};
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uint_reg_t
word
;
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}
TRIO_PCIE_INTFC_PORT_CONFIG_t
;
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/*
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* Port Status.
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* Status of the PCIe Port. This register applies to the StreamIO port when
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* StreamIO is enabled.
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*/
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__extension__
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typedef
union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/*
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* Indicates the DL state of the port. When 1, the port is up and ready
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* to receive traffic.
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*/
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uint_reg_t
dl_up : 1;
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/*
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* Indicates the number of times the link has gone down. Clears on read.
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*/
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uint_reg_t
dl_down_cnt : 7;
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/* Indicates the SERDES PLL has spun up and is providing a valid clock. */
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uint_reg_t
clock_ready : 1;
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/* Reserved. */
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uint_reg_t
__reserved_0 : 7;
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/* Device revision ID. */
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uint_reg_t
device_rev : 8;
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/* Link state (PCIe). */
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uint_reg_t
ltssm_state : 6;
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/* Link power management state (PCIe). */
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uint_reg_t
pm_state : 3;
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/* Reserved. */
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uint_reg_t
__reserved_1
: 31;
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#else
/* __BIG_ENDIAN__ */
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uint_reg_t
__reserved_1
: 31;
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uint_reg_t
pm_state : 3;
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uint_reg_t
ltssm_state : 6;
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uint_reg_t
device_rev : 8;
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uint_reg_t
__reserved_0 : 7;
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uint_reg_t
clock_ready : 1;
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uint_reg_t
dl_down_cnt : 7;
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uint_reg_t
dl_up : 1;
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#endif
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};
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uint_reg_t
word
;
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}
TRIO_PCIE_INTFC_PORT_STATUS_t
;
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/*
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* Transmit FIFO Control.
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* Contains TX FIFO thresholds. These registers are for diagnostics purposes
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* only. Changing these values causes undefined behavior.
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*/
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__extension__
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typedef
union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/*
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* Almost-Empty level for TX0 data. Typically set to at least
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* roundup(38.0*M/N) where N=tclk frequency and M=MAC symbol rate in MHz
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* for a x4 port (250MHz).
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*/
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uint_reg_t
tx0_data_ae_lvl : 7;
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/* Reserved. */
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uint_reg_t
__reserved_0 : 1;
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/* Almost-Empty level for TX1 data. */
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uint_reg_t
tx1_data_ae_lvl : 7;
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/* Reserved. */
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uint_reg_t
__reserved_1
: 1;
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/* Almost-Full level for TX0 data. */
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uint_reg_t
tx0_data_af_lvl : 7;
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/* Reserved. */
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uint_reg_t
__reserved_2
: 1;
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/* Almost-Full level for TX1 data. */
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uint_reg_t
tx1_data_af_lvl : 7;
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/* Reserved. */
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uint_reg_t
__reserved_3
: 1;
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/* Almost-Full level for TX0 info. */
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uint_reg_t
tx0_info_af_lvl : 5;
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/* Reserved. */
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uint_reg_t
__reserved_4
: 3;
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/* Almost-Full level for TX1 info. */
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uint_reg_t
tx1_info_af_lvl : 5;
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/* Reserved. */
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uint_reg_t
__reserved_5 : 3;
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/*
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* This register provides performance adjustment for high bandwidth
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* flows. The MAC will assert almost-full to TRIO if non-posted credits
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* fall below this level. Note that setting this larger than the initial
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* PORT_CREDIT.NPH value will cause READS to never be sent. If the
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* initial credit value from the link partner is smaller than this value
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* when the link comes up, the value will be reset to the initial credit
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* value to prevent lockup.
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*/
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uint_reg_t
min_np_credits : 8;
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/*
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* This register provides performance adjustment for high bandwidth
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* flows. The MAC will assert almost-full to TRIO if posted credits fall
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* below this level. Note that setting this larger than the initial
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* PORT_CREDIT.PH value will cause WRITES to never be sent. If the
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* initial credit value from the link partner is smaller than this value
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* when the link comes up, the value will be reset to the initial credit
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* value to prevent lockup.
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*/
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uint_reg_t
min_p_credits : 8;
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#else
/* __BIG_ENDIAN__ */
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uint_reg_t
min_p_credits : 8;
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uint_reg_t
min_np_credits : 8;
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uint_reg_t
__reserved_5 : 3;
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uint_reg_t
tx1_info_af_lvl : 5;
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uint_reg_t
__reserved_4
: 3;
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uint_reg_t
tx0_info_af_lvl : 5;
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uint_reg_t
__reserved_3
: 1;
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uint_reg_t
tx1_data_af_lvl : 7;
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uint_reg_t
__reserved_2
: 1;
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uint_reg_t
tx0_data_af_lvl : 7;
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uint_reg_t
__reserved_1
: 1;
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uint_reg_t
tx1_data_ae_lvl : 7;
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uint_reg_t
__reserved_0 : 1;
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uint_reg_t
tx0_data_ae_lvl : 7;
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#endif
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};
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uint_reg_t
word
;
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}
TRIO_PCIE_INTFC_TX_FIFO_CTL_t
;
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#endif
/* !defined(__ASSEMBLER__) */
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#endif
/* !defined(__ARCH_TRIO_PCIE_INTFC_H__) */
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