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tsb.h
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1 #ifndef _SPARC64_TSB_H
2 #define _SPARC64_TSB_H
3 
4 /* The sparc64 TSB is similar to the powerpc hashtables. It's a
5  * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
6  * pointers into this table for 8K and 64K page sizes, and also a
7  * comparison TAG based upon the virtual address and context which
8  * faults.
9  *
10  * TLB miss trap handler software does the actual lookup via something
11  * of the form:
12  *
13  * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
14  * ldxa [%g0] ASI_{D,I}MMU, %g6
15  * sllx %g6, 22, %g6
16  * srlx %g6, 22, %g6
17  * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
18  * cmp %g4, %g6
19  * bne,pn %xcc, tsb_miss_{d,i}tlb
20  * mov FAULT_CODE_{D,I}TLB, %g3
21  * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
22  * retry
23  *
24  *
25  * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
26  * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
27  * register which is:
28  *
29  * -------------------------------------------------
30  * | - | CONTEXT | - | VADDR bits 63:22 |
31  * -------------------------------------------------
32  * 63 61 60 48 47 42 41 0
33  *
34  * But actually, since we use per-mm TSB's, we zero out the CONTEXT
35  * field.
36  *
37  * Like the powerpc hashtables we need to use locking in order to
38  * synchronize while we update the entries. PTE updates need locking
39  * as well.
40  *
41  * We need to carefully choose a lock bits for the TSB entry. We
42  * choose to use bit 47 in the tag. Also, since we never map anything
43  * at page zero in context zero, we use zero as an invalid tag entry.
44  * When the lock bit is set, this forces a tag comparison failure.
45  */
46 
47 #define TSB_TAG_LOCK_BIT 47
48 #define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
49 
50 #define TSB_TAG_INVALID_BIT 46
51 #define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
52 
53 /* Some cpus support physical address quad loads. We want to use
54  * those if possible so we don't need to hard-lock the TSB mapping
55  * into the TLB. We encode some instruction patching in order to
56  * support this.
57  *
58  * The kernel TSB is locked into the TLB by virtue of being in the
59  * kernel image, so we don't play these games for swapper_tsb access.
60  */
61 #ifndef __ASSEMBLY__
62 struct tsb_ldquad_phys_patch_entry {
63  unsigned int addr;
64  unsigned int sun4u_insn;
65  unsigned int sun4v_insn;
66 };
67 extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
68  __tsb_ldquad_phys_patch_end;
69 
70 struct tsb_phys_patch_entry {
71  unsigned int addr;
72  unsigned int insn;
73 };
74 extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
75 #endif
76 #define TSB_LOAD_QUAD(TSB, REG) \
77 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
78  .section .tsb_ldquad_phys_patch, "ax"; \
79  .word 661b; \
80  ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
81  ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
82  .previous
83 
84 #define TSB_LOAD_TAG_HIGH(TSB, REG) \
85 661: lduwa [TSB] ASI_N, REG; \
86  .section .tsb_phys_patch, "ax"; \
87  .word 661b; \
88  lduwa [TSB] ASI_PHYS_USE_EC, REG; \
89  .previous
90 
91 #define TSB_LOAD_TAG(TSB, REG) \
92 661: ldxa [TSB] ASI_N, REG; \
93  .section .tsb_phys_patch, "ax"; \
94  .word 661b; \
95  ldxa [TSB] ASI_PHYS_USE_EC, REG; \
96  .previous
97 
98 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
99 661: casa [TSB] ASI_N, REG1, REG2; \
100  .section .tsb_phys_patch, "ax"; \
101  .word 661b; \
102  casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
103  .previous
104 
105 #define TSB_CAS_TAG(TSB, REG1, REG2) \
106 661: casxa [TSB] ASI_N, REG1, REG2; \
107  .section .tsb_phys_patch, "ax"; \
108  .word 661b; \
109  casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
110  .previous
111 
112 #define TSB_STORE(ADDR, VAL) \
113 661: stxa VAL, [ADDR] ASI_N; \
114  .section .tsb_phys_patch, "ax"; \
115  .word 661b; \
116  stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
117  .previous
118 
119 #define TSB_LOCK_TAG(TSB, REG1, REG2) \
120 99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
121  sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
122  andcc REG1, REG2, %g0; \
123  bne,pn %icc, 99b; \
124  nop; \
125  TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
126  cmp REG1, REG2; \
127  bne,pn %icc, 99b; \
128  nop; \
129 
130 #define TSB_WRITE(TSB, TTE, TAG) \
131  add TSB, 0x8, TSB; \
132  TSB_STORE(TSB, TTE); \
133  sub TSB, 0x8, TSB; \
134  TSB_STORE(TSB, TAG);
135 
136  /* Do a kernel page table walk. Leaves physical PTE pointer in
137  * REG1. Jumps to FAIL_LABEL on early page table walk termination.
138  * VADDR will not be clobbered, but REG2 will.
139  */
140 #define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
141  sethi %hi(swapper_pg_dir), REG1; \
142  or REG1, %lo(swapper_pg_dir), REG1; \
143  sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
144  srlx REG2, 64 - PAGE_SHIFT, REG2; \
145  andn REG2, 0x3, REG2; \
146  lduw [REG1 + REG2], REG1; \
147  brz,pn REG1, FAIL_LABEL; \
148  sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
149  srlx REG2, 64 - PAGE_SHIFT, REG2; \
150  sllx REG1, PGD_PADDR_SHIFT, REG1; \
151  andn REG2, 0x3, REG2; \
152  lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
153  brz,pn REG1, FAIL_LABEL; \
154  sllx VADDR, 64 - PMD_SHIFT, REG2; \
155  srlx REG2, 64 - (PAGE_SHIFT - 1), REG2; \
156  sllx REG1, PMD_PADDR_SHIFT, REG1; \
157  andn REG2, 0x7, REG2; \
158  add REG1, REG2, REG1;
159 
160  /* This macro exists only to make the PMD translator below easier
161  * to read. It hides the ELF section switch for the sun4v code
162  * patching.
163  */
164 #define OR_PTE_BIT(REG, NAME) \
165 661: or REG, _PAGE_##NAME##_4U, REG; \
166  .section .sun4v_1insn_patch, "ax"; \
167  .word 661b; \
168  or REG, _PAGE_##NAME##_4V, REG; \
169  .previous;
170 
171  /* Load into REG the PTE value for VALID, CACHE, and SZHUGE. */
172 #define BUILD_PTE_VALID_SZHUGE_CACHE(REG) \
173 661: sethi %uhi(_PAGE_VALID|_PAGE_SZHUGE_4U), REG; \
174  .section .sun4v_1insn_patch, "ax"; \
175  .word 661b; \
176  sethi %uhi(_PAGE_VALID), REG; \
177  .previous; \
178  sllx REG, 32, REG; \
179 661: or REG, _PAGE_CP_4U|_PAGE_CV_4U, REG; \
180  .section .sun4v_1insn_patch, "ax"; \
181  .word 661b; \
182  or REG, _PAGE_CP_4V|_PAGE_CV_4V|_PAGE_SZHUGE_4V, REG; \
183  .previous;
184 
185  /* PMD has been loaded into REG1, interpret the value, seeing
186  * if it is a HUGE PMD or a normal one. If it is not valid
187  * then jump to FAIL_LABEL. If it is a HUGE PMD, and it
188  * translates to a valid PTE, branch to PTE_LABEL.
189  *
190  * We translate the PMD by hand, one bit at a time,
191  * constructing the huge PTE.
192  *
193  * So we construct the PTE in REG2 as follows:
194  *
195  * 1) Extract the PMD PFN from REG1 and place it into REG2.
196  *
197  * 2) Translate PMD protection bits in REG1 into REG2, one bit
198  * at a time using andcc tests on REG1 and OR's into REG2.
199  *
200  * Only two bits to be concerned with here, EXEC and WRITE.
201  * Now REG1 is freed up and we can use it as a temporary.
202  *
203  * 3) Construct the VALID, CACHE, and page size PTE bits in
204  * REG1, OR with REG2 to form final PTE.
205  */
206 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
207 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
208  brz,pn REG1, FAIL_LABEL; \
209  andcc REG1, PMD_ISHUGE, %g0; \
210  be,pt %xcc, 700f; \
211  and REG1, PMD_HUGE_PRESENT|PMD_HUGE_ACCESSED, REG2; \
212  cmp REG2, PMD_HUGE_PRESENT|PMD_HUGE_ACCESSED; \
213  bne,pn %xcc, FAIL_LABEL; \
214  andn REG1, PMD_HUGE_PROTBITS, REG2; \
215  sllx REG2, PMD_PADDR_SHIFT, REG2; \
216  /* REG2 now holds PFN << PAGE_SHIFT */ \
217  andcc REG1, PMD_HUGE_EXEC, %g0; \
218  bne,a,pt %xcc, 1f; \
219  OR_PTE_BIT(REG2, EXEC); \
220 1: andcc REG1, PMD_HUGE_WRITE, %g0; \
221  bne,a,pt %xcc, 1f; \
222  OR_PTE_BIT(REG2, W); \
223  /* REG1 can now be clobbered, build final PTE */ \
224 1: BUILD_PTE_VALID_SZHUGE_CACHE(REG1); \
225  ba,pt %xcc, PTE_LABEL; \
226  or REG1, REG2, REG1; \
227 700:
228 #else
229 #define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
230  brz,pn REG1, FAIL_LABEL; \
231  nop;
232 #endif
233 
234  /* Do a user page table walk in MMU globals. Leaves final,
235  * valid, PTE value in REG1. Jumps to FAIL_LABEL on early
236  * page table walk termination or if the PTE is not valid.
237  *
238  * Physical base of page tables is in PHYS_PGD which will not
239  * be modified.
240  *
241  * VADDR will not be clobbered, but REG1 and REG2 will.
242  */
243 #define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
244  sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
245  srlx REG2, 64 - PAGE_SHIFT, REG2; \
246  andn REG2, 0x3, REG2; \
247  lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
248  brz,pn REG1, FAIL_LABEL; \
249  sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
250  srlx REG2, 64 - PAGE_SHIFT, REG2; \
251  sllx REG1, PGD_PADDR_SHIFT, REG1; \
252  andn REG2, 0x3, REG2; \
253  lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
254  USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
255  sllx VADDR, 64 - PMD_SHIFT, REG2; \
256  srlx REG2, 64 - (PAGE_SHIFT - 1), REG2; \
257  sllx REG1, PMD_PADDR_SHIFT, REG1; \
258  andn REG2, 0x7, REG2; \
259  add REG1, REG2, REG1; \
260  ldxa [REG1] ASI_PHYS_USE_EC, REG1; \
261  brgez,pn REG1, FAIL_LABEL; \
262  nop; \
263 800:
264 
265 /* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
266  * If no entry is found, FAIL_LABEL will be branched to. On success
267  * the resulting PTE value will be left in REG1. VADDR is preserved
268  * by this routine.
269  */
270 #define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
271  sethi %hi(prom_trans), REG1; \
272  or REG1, %lo(prom_trans), REG1; \
273 97: ldx [REG1 + 0x00], REG2; \
274  brz,pn REG2, FAIL_LABEL; \
275  nop; \
276  ldx [REG1 + 0x08], REG3; \
277  add REG2, REG3, REG3; \
278  cmp REG2, VADDR; \
279  bgu,pt %xcc, 98f; \
280  cmp VADDR, REG3; \
281  bgeu,pt %xcc, 98f; \
282  ldx [REG1 + 0x10], REG3; \
283  sub VADDR, REG2, REG2; \
284  ba,pt %xcc, 99f; \
285  add REG3, REG2, REG1; \
286 98: ba,pt %xcc, 97b; \
287  add REG1, (3 * 8), REG1; \
288 99:
289 
290  /* We use a 32K TSB for the whole kernel, this allows to
291  * handle about 16MB of modules and vmalloc mappings without
292  * incurring many hash conflicts.
293  */
294 #define KERNEL_TSB_SIZE_BYTES (32 * 1024)
295 #define KERNEL_TSB_NENTRIES \
296  (KERNEL_TSB_SIZE_BYTES / 16)
297 #define KERNEL_TSB4M_NENTRIES 4096
298 
299 #define KTSB_PHYS_SHIFT 15
300 
301  /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
302  * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
303  * and the found TTE will be left in REG1. REG3 and REG4 must
304  * be an even/odd pair of registers.
305  *
306  * VADDR and TAG will be preserved and not clobbered by this macro.
307  */
308 #define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
309 661: sethi %hi(swapper_tsb), REG1; \
310  or REG1, %lo(swapper_tsb), REG1; \
311  .section .swapper_tsb_phys_patch, "ax"; \
312  .word 661b; \
313  .previous; \
314 661: nop; \
315  .section .tsb_ldquad_phys_patch, "ax"; \
316  .word 661b; \
317  sllx REG1, KTSB_PHYS_SHIFT, REG1; \
318  sllx REG1, KTSB_PHYS_SHIFT, REG1; \
319  .previous; \
320  srlx VADDR, PAGE_SHIFT, REG2; \
321  and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
322  sllx REG2, 4, REG2; \
323  add REG1, REG2, REG2; \
324  TSB_LOAD_QUAD(REG2, REG3); \
325  cmp REG3, TAG; \
326  be,a,pt %xcc, OK_LABEL; \
327  mov REG4, REG1;
328 
329 #ifndef CONFIG_DEBUG_PAGEALLOC
330  /* This version uses a trick, the TAG is already (VADDR >> 22) so
331  * we can make use of that for the index computation.
332  */
333 #define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
334 661: sethi %hi(swapper_4m_tsb), REG1; \
335  or REG1, %lo(swapper_4m_tsb), REG1; \
336  .section .swapper_4m_tsb_phys_patch, "ax"; \
337  .word 661b; \
338  .previous; \
339 661: nop; \
340  .section .tsb_ldquad_phys_patch, "ax"; \
341  .word 661b; \
342  sllx REG1, KTSB_PHYS_SHIFT, REG1; \
343  sllx REG1, KTSB_PHYS_SHIFT, REG1; \
344  .previous; \
345  and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
346  sllx REG2, 4, REG2; \
347  add REG1, REG2, REG2; \
348  TSB_LOAD_QUAD(REG2, REG3); \
349  cmp REG3, TAG; \
350  be,a,pt %xcc, OK_LABEL; \
351  mov REG4, REG1;
352 #endif
353 
354 #endif /* !(_SPARC64_TSB_H) */
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