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Data Structures | Macros | Variables
tsb.h File Reference

Go to the source code of this file.

Data Structures

struct  tsb_ldquad_phys_patch_entry
 
struct  tsb_phys_patch_entry
 

Macros

#define TSB_TAG_LOCK_BIT   47
 
#define TSB_TAG_LOCK_HIGH   (1 << (TSB_TAG_LOCK_BIT - 32))
 
#define TSB_TAG_INVALID_BIT   46
 
#define TSB_TAG_INVALID_HIGH   (1 << (TSB_TAG_INVALID_BIT - 32))
 
#define TSB_LOAD_QUAD(TSB, REG)
 
#define TSB_LOAD_TAG_HIGH(TSB, REG)
 
#define TSB_LOAD_TAG(TSB, REG)
 
#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2)
 
#define TSB_CAS_TAG(TSB, REG1, REG2)
 
#define TSB_STORE(ADDR, VAL)
 
#define TSB_LOCK_TAG(TSB, REG1, REG2)
 
#define TSB_WRITE(TSB, TTE, TAG)
 
#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL)
 
#define OR_PTE_BIT(REG, NAME)
 
#define BUILD_PTE_VALID_SZHUGE_CACHE(REG)
 
#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL)
 
#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL)
 
#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL)
 
#define KERNEL_TSB_SIZE_BYTES   (32 * 1024)
 
#define KERNEL_TSB_NENTRIES   (KERNEL_TSB_SIZE_BYTES / 16)
 
#define KERNEL_TSB4M_NENTRIES   4096
 
#define KTSB_PHYS_SHIFT   15
 
#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL)
 
#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL)
 

Variables

struct
tsb_ldquad_phys_patch_entry
__tsb_ldquad_phys_patch 
__tsb_ldquad_phys_patch_end
 
struct tsb_phys_patch_entry
__tsb_phys_patch 
__tsb_phys_patch_end
 

Macro Definition Documentation

#define BUILD_PTE_VALID_SZHUGE_CACHE (   REG)
Value:
661: sethi %uhi(_PAGE_VALID|_PAGE_SZHUGE_4U), REG; \
.section .sun4v_1insn_patch, "ax"; \
.word 661b; \
sethi %uhi(_PAGE_VALID), REG; \
.previous; \
sllx REG, 32, REG; \
.section .sun4v_1insn_patch, "ax"; \
.word 661b; \
.previous;

Definition at line 172 of file tsb.h.

#define KERN_PGTABLE_WALK (   VADDR,
  REG1,
  REG2,
  FAIL_LABEL 
)
Value:
sethi %hi(swapper_pg_dir), REG1; \
sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
srlx REG2, 64 - PAGE_SHIFT, REG2; \
andn REG2, 0x3, REG2; \
lduw [REG1 + REG2], REG1; \
brz,pn REG1, FAIL_LABEL; \
sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
srlx REG2, 64 - PAGE_SHIFT, REG2; \
andn REG2, 0x3, REG2; \
lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
brz,pn REG1, FAIL_LABEL; \
sllx VADDR, 64 - PMD_SHIFT, REG2; \
srlx REG2, 64 - (PAGE_SHIFT - 1), REG2; \
andn REG2, 0x7, REG2; \
add REG1, REG2, REG1;

Definition at line 140 of file tsb.h.

#define KERN_TSB4M_LOOKUP_TL1 (   TAG,
  REG1,
  REG2,
  REG3,
  REG4,
  OK_LABEL 
)
Value:
661: sethi %hi(swapper_4m_tsb), REG1; \
or REG1, %lo(swapper_4m_tsb), REG1; \
.section .swapper_4m_tsb_phys_patch, "ax"; \
.word 661b; \
.previous; \
661: nop; \
.section .tsb_ldquad_phys_patch, "ax"; \
.word 661b; \
.previous; \
sllx REG2, 4, REG2; \
add REG1, REG2, REG2; \
TSB_LOAD_QUAD(REG2, REG3); \
cmp REG3, TAG; \
be,a,pt %xcc, OK_LABEL; \
mov REG4, REG1;

Definition at line 333 of file tsb.h.

#define KERN_TSB_LOOKUP_TL1 (   VADDR,
  TAG,
  REG1,
  REG2,
  REG3,
  REG4,
  OK_LABEL 
)
Value:
661: sethi %hi(swapper_tsb), REG1; \
or REG1, %lo(swapper_tsb), REG1; \
.section .swapper_tsb_phys_patch, "ax"; \
.word 661b; \
.previous; \
661: nop; \
.section .tsb_ldquad_phys_patch, "ax"; \
.word 661b; \
.previous; \
srlx VADDR, PAGE_SHIFT, REG2; \
and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
sllx REG2, 4, REG2; \
add REG1, REG2, REG2; \
TSB_LOAD_QUAD(REG2, REG3); \
cmp REG3, TAG; \
be,a,pt %xcc, OK_LABEL; \
mov REG4, REG1;

Definition at line 308 of file tsb.h.

#define KERNEL_TSB4M_NENTRIES   4096

Definition at line 297 of file tsb.h.

#define KERNEL_TSB_NENTRIES   (KERNEL_TSB_SIZE_BYTES / 16)

Definition at line 295 of file tsb.h.

#define KERNEL_TSB_SIZE_BYTES   (32 * 1024)

Definition at line 294 of file tsb.h.

#define KTSB_PHYS_SHIFT   15

Definition at line 299 of file tsb.h.

#define OBP_TRANS_LOOKUP (   VADDR,
  REG1,
  REG2,
  REG3,
  FAIL_LABEL 
)
Value:
sethi %hi(prom_trans), REG1; \
or REG1, %lo(prom_trans), REG1; \
97: ldx [REG1 + 0x00], REG2; \
brz,pn REG2, FAIL_LABEL; \
nop; \
ldx [REG1 + 0x08], REG3; \
add REG2, REG3, REG3; \
cmp REG2, VADDR; \
bgu,pt %xcc, 98f; \
cmp VADDR, REG3; \
bgeu,pt %xcc, 98f; \
ldx [REG1 + 0x10], REG3; \
sub VADDR, REG2, REG2; \
ba,pt %xcc, 99f; \
add REG3, REG2, REG1; \
98: ba,pt %xcc, 97b; \
add REG1, (3 * 8), REG1; \
99:

Definition at line 270 of file tsb.h.

#define OR_PTE_BIT (   REG,
  NAME 
)
Value:
661: or REG, _PAGE_##NAME##_4U, REG; \
.section .sun4v_1insn_patch, "ax"; \
.word 661b; \
or REG, _PAGE_##NAME##_4V, REG; \
.previous;

Definition at line 164 of file tsb.h.

#define TSB_CAS_TAG (   TSB,
  REG1,
  REG2 
)
Value:
661: casxa [TSB] ASI_N, REG1, REG2; \
.section .tsb_phys_patch, "ax"; \
.word 661b; \
casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
.previous

Definition at line 105 of file tsb.h.

#define TSB_CAS_TAG_HIGH (   TSB,
  REG1,
  REG2 
)
Value:
661: casa [TSB] ASI_N, REG1, REG2; \
.section .tsb_phys_patch, "ax"; \
.word 661b; \
casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
.previous

Definition at line 98 of file tsb.h.

#define TSB_LOAD_QUAD (   TSB,
  REG 
)
Value:
661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
.section .tsb_ldquad_phys_patch, "ax"; \
.word 661b; \
ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
.previous

Definition at line 76 of file tsb.h.

#define TSB_LOAD_TAG (   TSB,
  REG 
)
Value:
661: ldxa [TSB] ASI_N, REG; \
.section .tsb_phys_patch, "ax"; \
.word 661b; \
ldxa [TSB] ASI_PHYS_USE_EC, REG; \
.previous

Definition at line 91 of file tsb.h.

#define TSB_LOAD_TAG_HIGH (   TSB,
  REG 
)
Value:
661: lduwa [TSB] ASI_N, REG; \
.section .tsb_phys_patch, "ax"; \
.word 661b; \
lduwa [TSB] ASI_PHYS_USE_EC, REG; \
.previous

Definition at line 84 of file tsb.h.

#define TSB_LOCK_TAG (   TSB,
  REG1,
  REG2 
)
Value:
99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
andcc REG1, REG2, %g0; \
bne,pn %icc, 99b; \
nop; \
TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
cmp REG1, REG2; \
bne,pn %icc, 99b; \
nop; \

Definition at line 119 of file tsb.h.

#define TSB_STORE (   ADDR,
  VAL 
)
Value:
661: stxa VAL, [ADDR] ASI_N; \
.section .tsb_phys_patch, "ax"; \
.word 661b; \
.previous

Definition at line 112 of file tsb.h.

#define TSB_TAG_INVALID_BIT   46

Definition at line 50 of file tsb.h.

#define TSB_TAG_INVALID_HIGH   (1 << (TSB_TAG_INVALID_BIT - 32))

Definition at line 51 of file tsb.h.

#define TSB_TAG_LOCK_BIT   47

Definition at line 47 of file tsb.h.

#define TSB_TAG_LOCK_HIGH   (1 << (TSB_TAG_LOCK_BIT - 32))

Definition at line 48 of file tsb.h.

#define TSB_WRITE (   TSB,
  TTE,
  TAG 
)
Value:
add TSB, 0x8, TSB; \
TSB_STORE(TSB, TTE); \
sub TSB, 0x8, TSB; \
TSB_STORE(TSB, TAG);

Definition at line 130 of file tsb.h.

#define USER_PGTABLE_CHECK_PMD_HUGE (   VADDR,
  REG1,
  REG2,
  FAIL_LABEL,
  PTE_LABEL 
)
Value:
brz,pn REG1, FAIL_LABEL; \
nop;

Definition at line 229 of file tsb.h.

#define USER_PGTABLE_WALK_TL1 (   VADDR,
  PHYS_PGD,
  REG1,
  REG2,
  FAIL_LABEL 
)
Value:
sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
srlx REG2, 64 - PAGE_SHIFT, REG2; \
andn REG2, 0x3, REG2; \
lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
brz,pn REG1, FAIL_LABEL; \
sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
srlx REG2, 64 - PAGE_SHIFT, REG2; \
andn REG2, 0x3, REG2; \
lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
sllx VADDR, 64 - PMD_SHIFT, REG2; \
srlx REG2, 64 - (PAGE_SHIFT - 1), REG2; \
andn REG2, 0x7, REG2; \
add REG1, REG2, REG1; \
brgez,pn REG1, FAIL_LABEL; \
nop; \
800:

Definition at line 243 of file tsb.h.

Variable Documentation

struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch __tsb_ldquad_phys_patch_end
struct tsb_phys_patch_entry __tsb_phys_patch __tsb_phys_patch_end